Display substrate and display module

Abstract

The embodiment of the utility model discloses a display substrate and a display module. In one specific implementation mode, the display substrate comprises a substrate body, an isolation layer, a shading layer, a buffer layer and a driving circuit layer, the isolation layer, the shading layer, the buffer layer and the driving circuit layer are sequentially stacked on the substrate body, the driving circuit layer comprises an active layer, a gate insulation layer, a gate, a dielectric layer and a source-drain metal layer which are sequentially stacked, and the display substrate comprises a display area and a fan-out area. In the display area, the source-drain metal layer is in contact with the isolation layer through a first via hole penetrating through the dielectric layer, the gate insulation layer, the active layer and the buffer layer. According to the embodiment, the problem of impurity ion precipitation in the substrate can be effectively solved, the ion pollution resistance of a product is improved, and the product characteristic and the display performance are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and more specifically, to a display substrate and a display module. Background Art

[0002] Currently, due to process design reasons, the source and drain metal layers in the display area of some display substrates pass through the active layer to contact the substrate. In this way, the high temperature and other processes in the preparation process may cause impurity ions in the substrate to precipitate into the display substrate, affecting product characteristics and display performance. Utility Model Content

[0003] The present disclosure aims to provide a display substrate and a display module to solve at least one of the problems existing in the prior art.

[0004] To achieve the above objectives, the present disclosure adopts the following technical solutions:

[0005] A first aspect of the present disclosure provides a display substrate, comprising a substrate and an isolation layer, a light-shielding layer, a buffer layer, and a driving circuit layer stacked in sequence on the substrate, wherein the driving circuit layer comprises an active layer, a gate insulating layer, a gate, a dielectric layer, and a source-drain metal layer stacked in sequence, and the display substrate comprises a display area and a fan-out area. In the display area, the source-drain metal layer contacts the isolation layer through a first via hole penetrating the dielectric layer, the gate insulating layer, the active layer, and the buffer layer.

[0006] Optionally, the thickness of the isolation layer is greater than and less than

[0007] Optionally, the isolation layer includes silicon nitride.

[0008] Optionally, in the fan-out area, part of the first metal layer is connected to the second metal layer through a second via penetrating the dielectric layer, the gate insulation layer and the buffer layer, the first metal layer is arranged on the same layer as the source and drain metal layer, the light-shielding layer is a metal light-shielding layer, and the second metal layer is arranged on the same layer as the metal light-shielding layer.

[0009] Optionally, in the fan-out region, part of the first metal layer is connected to a third metal layer through a third via penetrating the dielectric layer, and the third metal layer is provided in the same layer as the gate.

[0010] Optionally, an orthographic projection of the light shielding layer on the substrate does not overlap with an orthographic projection of the first via hole on the substrate.

[0011] Optionally, the substrate includes a glass substrate.

[0012] Optionally, the display substrate further includes a planar layer and a pixel electrode sequentially stacked on the driving circuit layer, and the pixel electrode is connected to the source-drain metal layer through a fourth via hole penetrating the planar layer.

[0013] A second aspect of the present disclosure provides a display module, comprising the display substrate.

[0014] Optionally, the display module further includes a cell-matching substrate and a liquid crystal layer arranged between the display substrate and the cell-matching substrate.

[0015] The beneficial effects of the present disclosure are as follows:

[0016] The technical solution disclosed in the present invention can effectively solve the problem of impurity ion precipitation in the substrate by adding an isolation layer between the substrate and the buffer layer to completely isolate the substrate from the driving circuit layer, thereby improving the product's resistance to ion contamination and enhancing product characteristics and display performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The specific embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0018] Figure 1 A schematic structural diagram of a display module in related art is shown.

[0019] Figure 2 A cross-sectional schematic diagram of a display module in the related art is shown.

[0020] Figure 3 A cross-sectional schematic diagram of a display module provided by an embodiment of the present disclosure is shown.

[0021] Figures 4 to 19 A schematic diagram showing a process for preparing a display substrate provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] The terms “on,” “formed on,” and “disposed on” used in the present disclosure may mean that one layer is directly formed or disposed on another layer, or may mean that one layer is indirectly formed or disposed on another layer, i.e., there are other layers between the two layers.

[0023] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0024] In this disclosure, unless otherwise specified, the term "co-layer arrangement" refers to two layers, components, members, elements, or parts that can be formed by the same manufacturing process (e.g., patterning process, etc.), and the two layers, components, members, elements, or parts are generally formed from the same material. For example, co-layer arrangement of two or more functional layers means that these co-layered functional layers can be formed using the same material layer and the same manufacturing process, thereby simplifying the manufacturing process of the display substrate.

[0025] In this disclosure, unless otherwise specified, the expression "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, and photoresist stripping. The expression "one-time patterning process" means a process of forming patterned layers, components, members, etc. using one mask.

[0026] In related technologies, taking the Low Temperature Poly-silicon (LTPS) process as an example, the fan-out area of conventional LTPS products uses a two-layer wiring design of source and drain metal layers and gate metal layers. Due to the limitation of process capabilities, it is difficult to reduce the wiring space of LTPS products, resulting in the inability to narrow the border of LTPS products.

[0027] Therefore, by implementing a three-layer wiring design of a light-shielding metal layer, a gate metal layer, and a source-drain metal layer in the fan-out area, the wiring problem of the fan-out area existing in the related technology is solved. By reducing the horizontal wiring space by vertically jumping the wires, the wiring space of the fan-out area is reduced, thereby making it possible to produce products with extremely narrow bezels.

[0028] like Figure 1-Figure 2 As shown, taking the low-temperature polysilicon technology as an example, Figure 2 It includes display area (AA area) 1 and fan-out area (Fanout) 2. Figure 2 The area 103 in the display area 1 is Figure 1 BB cross-section diagram in Figure 2 The area 102 in the display area 1 is Figure 1 The CC cross-section diagram in Figure 2The area 101 in the display area 1 is Figure 1 The DD cross-sectional view in the fan-out area 2 is a cross-sectional view in the fan-out area of the display module. The display module includes a substrate 10; a light shielding layer (LS) provided on the substrate 10, the light shielding layer includes a metal light shielding layer 201 located in the display area 1 and a second metal layer 202 located in the fan-out area 2, the metal light shielding layer 201 and the second metal layer 202 are provided in the same layer; a buffer layer 20 (Buffer) provided on the light shielding layer, the light shielding layer is provided between the substrate 10 and the buffer layer 20; a polysilicon active layer 301 (Poly-silicon) provided on the buffer layer 20, the active layer 301 includes a channel region of the transistor, and the channel The orthographic projection of the active layer 301 on the substrate 10 is at least partially overlapped with the orthographic projection of the metal light shielding layer 201 on the substrate 10; a gate insulating layer 30 (Gate Insulator, GI) is provided on the active layer 301, and the active layer 301 is provided between the buffer layer 20 and the gate insulating layer 30; a gate layer is provided on the gate insulating layer 30, and the gate layer includes a gate 401 (Gate) located in the display area 1 and a third metal layer 402 located in the fan-out area 2, and the gate 401 and the third metal layer 402 are provided in the same layer; an interlayer dielectric layer 40 (Inter a plurality of contact holes (CNTs) are formed by etching the display area 1 and the fan-out area 2 simultaneously through a single patterning process. The contact holes include a first via hole penetrating the dielectric layer 40, the gate insulating layer 30, the active layer 301 and the buffer layer 20 in the display area 1, a second via hole penetrating the dielectric layer 40, the gate insulating layer 30 and the buffer layer 20 in the fan-out area 2, and a third via hole penetrating the dielectric layer 40 in the fan-out area 2. The source drain metal layer 501 (SD) contacts the substrate 10 through the first via hole, a portion of the first metal layer 502 is connected to the second metal layer 202 through the second via hole, and a portion of the first metal layer 503 is connected to the third metal layer 402 through the third via hole. A planarization layer 50 (PLN) is provided on the interlayer dielectric layer 40. A fourth via hole penetrating the planarization layer 50 is formed by etching the planarization layer 50. A pixel electrode 601 (Pixel Indium Tin) Oxide, P-ITO) is connected to the source and drain metal layer 501 through a fourth via hole; a common electrode 602 is provided on the flat layer 50; a passivation layer 60 (Passivation, PVX) is provided on the flat layer 50; a cell substrate is provided on the pixel electrode 601, the cell substrate includes a first alignment layer 70, the display substrate includes a second alignment layer 90, and a liquid crystal layer 80 is provided between the first alignment layer 70 and the second alignment layer 90. In addition, the cell substrate also includes a second substrate, etc. ( Figure 2 not shown).

[0029] Depend on Figure 2 It can be seen that, taking the substrate 10 as a glass substrate as an example, in a single patterning process, the three-layer wiring product will etch through the interlayer dielectric layer 40, the gate insulating layer 30 and the buffer layer 20 of the display area 1 when etching the contact hole. This is because when etching the first via hole and the second via hole at the same time, in order to fully connect part of the first metal layer 502 and the second metal layer 202 of the fan-out area 2, the second via hole needs to be over-etched when etching the second via hole. Since the orthographic projection of the metal shading layer 201 of the display area 1 on the substrate 10 does not overlap with the orthographic projection of the first via hole on the substrate 10, the first via hole in the display area 1 penetrates the buffer layer 20 when over-etching, thereby causing the subsequent drain-source metal layer 501 of the display area 1 and the substrate 10 to contact each other; at the same time, part of the first metal layer 502 and the second metal layer 202 of the fan-out area 2 are connected to each other, and part of the first metal layer 503 and the third metal layer 402 of the fan-out area 2 are connected to each other. Since the buffer layer 20 of the display area 1 cannot completely isolate the substrate 10 from the source / drain metal layer 501 in the thin film field effect transistor (TFT), the high temperature and other processes in the process of preparing the thin film field effect transistor can easily cause the impurity ions in the substrate 10 to be precipitated into the active layer 301 of the thin film field effect transistor, thereby affecting the switching characteristics of the thin film field effect transistor.

[0030] Furthermore, due to the influence of the nearby light-shielding layer, impurity ions precipitated within the display substrate attract the impurity ions to portions of the first metal layer 502 and 503 located in the fan-out region 2. This further causes impurity ions in the substrate 10 to precipitate through the source / drain metal layer 501 and its vias onto the display substrate, affecting product characteristics and display performance. Furthermore, for liquid crystal displays (LCDs), impurity ions in the substrate 10 can also diffuse upward along the source / drain metal layer 501 and its vias into the cell-matching substrate, affecting the deflection of the liquid crystal 80 and resulting in display defects.

[0031] In summary, due to process design reasons, the source and drain metal layers in the display area of some display substrates will pass through the active layer and contact the substrate. In this way, high temperatures and other processes in the preparation process may cause impurity ions in the substrate to precipitate into the display substrate, affecting product characteristics and display performance.

[0032] In view of this, an embodiment of the present disclosure provides a display substrate, comprising a substrate and an isolation layer, a light-shielding layer, a buffer layer and a driving circuit layer stacked in sequence on the substrate, the driving circuit layer comprising an active layer, a gate insulating layer, a gate, a dielectric layer and a source-drain metal layer stacked in sequence, the display substrate comprising a display area and a fan-out area, in the display area, the source-drain metal layer contacts the isolation layer through a first via hole penetrating the dielectric layer, the gate insulating layer, the active layer and the buffer layer.

[0033] In a specific example, Figure 3 As shown, it includes a substrate 100, which includes a display area 11 and a fan-out area 12. Figure 3 The middle area 110, area 120 and area 130 are respectively Figure 2 Regions 101, 102, and 103 in the display area correspond one to one; an isolation layer 2000 is provided on the substrate 100; a light-shielding layer is provided on the isolation layer 2000, the light-shielding layer includes a metal light-shielding layer 210 located in the display area 11 and a second metal layer 220 located in the fan-out area 12, and the metal light-shielding layer 210 and the second metal layer 220 are provided on the same layer; a buffer layer 200 is provided on the light-shielding layer 2000; and a driving circuit layer is provided on the buffer layer 200.

[0034] In a specific example, Figure 3 As shown, the driving circuit layer includes an active layer 310 arranged on the buffer layer 200; a gate insulating layer 300 arranged on the active layer 310; a gate 410 arranged on the gate insulating layer 300; a dielectric layer 400 arranged on the gate 410; and a source / drain metal layer 510 arranged on the dielectric layer 400.

[0035] Further, such as Figure 3 As shown, the gate 410 is disposed in the same layer as the third metal layer 420 located in the fan-out region 12 ; the source / drain metal layer 510 is disposed in the same layer as a portion of the first metal layer 520 and a portion of the first metal layer 530 located in the fan-out region 12 .

[0036] In a specific example, Figure 3 As shown, in the display area 11 , the source / drain metal layer 510 contacts the isolation layer 2000 through a first via hole penetrating the dielectric layer 400 , the gate insulating layer 300 , the active layer 310 and the buffer layer 200 .

[0037] This embodiment completely isolates the substrate from the driving circuit layer by adding an isolation layer between the substrate and the buffer layer, which can effectively solve the problem of impurity ion precipitation in the substrate, enhance the product's resistance to ion contamination, and improve product characteristics and display performance.

[0038] The technical solution of this embodiment will be further illustrated below using the preparation process of the display substrate of this embodiment. The "patterning process" referred to in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature preparation process in the relevant art. Deposition can be performed using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can use known coating processes; and etching can use known methods, and no specific limitations are given here.

[0039] In a specific example, Figures 4 to 19 A schematic diagram illustrating a process for preparing a display substrate according to an embodiment of the present disclosure is shown. Furthermore, the process for preparing the display substrate includes:

[0040] Step S1: providing a substrate;

[0041] In a possible implementation, the substrate includes a glass substrate.

[0042] In a specific example, Figure 4 As shown, substrate 10 is used to form the LTPS array substrate of the display panel. The substrate can be a rigid substrate, such as a glass substrate or a polymethyl methacrylate (PMMA) substrate, or a flexible substrate, such as a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate diformic acid glycolster (PEN) substrate, or a polyimide (PI) substrate. When a flexible substrate is used, the corresponding display panel is a flexible display panel.

[0043] Step S2: forming an isolation layer on the substrate;

[0044] In a specific example, Figure 5 As shown, step S2 includes depositing an isolation layer 2000 on the substrate 100 .

[0045] In a specific example, Figure 5 As shown, the isolation layer may be a single-layer structure of silicon nitride, silicon oxide, or silicon oxynitride; or a multi-layer structure of silicon nitride, silicon oxide, and silicon oxynitride; or a combination of other non-conductive materials.

[0046] The isolation layer in this example can be used to prevent impurities in the substrate from diffusing upward in subsequent processes and affecting the quality of the polysilicon pattern formed subsequently, and can also be used to improve the substrate's resistance to water and oxygen.

[0047] In a possible implementation, the isolation layer includes silicon nitride.

[0048] In a specific example, Figure 5 As shown, a whole isolation layer 2000 is manufactured on the substrate 100 , and the material of the buffer layer 2000 is silicon nitride.

[0049] This example improves the ability of the isolation layer to completely isolate the substrate from the driving circuit layer by using silicon nitride material with the best isolation capability.

[0050] In a possible implementation, the thickness of the isolation layer is greater than and less than

[0051] In a specific example, Figure 5 As shown, the thickness of the isolation layer 2000 is

[0052] and

[0053] The isolation layers of different thicknesses provided in this example can all achieve complete isolation of the substrate from the driving circuit layer, thereby increasing the flexibility of selecting the thickness of the isolation layer.

[0054] Step S3: forming a light shielding layer on a side of the isolation layer away from the substrate;

[0055] In a specific example, Figure 6 As shown, step S3 includes depositing a light shielding material layer on the isolation layer 2000, coating a photoresist, exposing a mask, developing, etching and stripping the photoresist to form a metal light shielding layer 210 in the display area and a second metal layer 220 in the fan-out area.

[0056] In a specific example, Figure 6 As shown, the material of the metal light-shielding layer 210 and the second metal layer 220 can be metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), gold (Au), copper (Cu), hafnium (Hf), and tantalum (Ta), or can be aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb).

[0057] In a specific example, Figure 6 As shown, the metal light-shielding layer 210 is used to shield the active layer 301 or the channel region of the transistor to prevent light from irradiating the transistor from the backlight side of the substrate 100, thereby reducing the risk of leakage of the transistor caused by light, which is beneficial to reducing power consumption and improving the stability of the picture display.

[0058] In a specific example, Figure 6As shown, the second metal layer 220 serves as a part of the signal line of the fan-out region and is used to transmit data signals.

[0059] In this example, a light-shielding layer is provided in both the display area and the fan-out area. By performing second metal layer wiring in the fan-out area, the light-shielding layer is fully utilized, the wiring space is reduced, and the lower frame of the display panel is further reduced.

[0060] In a specific example, Figure 6 As shown, when the metal light shielding layer 210 and the second metal layer 220 are made of aluminum and molybdenum double-layer metal, the thickness of the aluminum metal layer is The thickness of the molybdenum metal layer is

[0061] Step S4: forming a buffer layer on a side of the light shielding layer away from the substrate;

[0062] In a specific example, Figure 7 As shown, step S4 includes depositing a buffer layer 200 on the side of the light shielding layer away from the substrate 100 , and the buffer layer 200 covers the metal light shielding layer 210 in the display area, the second metal layer 220 in the fan-out area, and the isolation layer 2000 .

[0063] In a specific example, Figure 7 As shown, the buffer layer 200 is made of insulating materials such as silicon oxide, silicon nitride or silicon oxynitride. Furthermore, the buffer layer 200 can be formed by chemical vapor deposition, plasma chemical vapor deposition, sputtering, vacuum evaporation or low pressure chemical vapor deposition.

[0064] The buffer layer in this example covers the metal light shielding layer, the second metal layer and the isolation layer, and plays the role of insulating the metal light shielding layer, the second metal layer and planarizing.

[0065] Step S5: forming an active layer on a side of the buffer layer away from the substrate;

[0066] In a specific example, Figure 8 As shown, step S5 includes depositing an active layer thin film on the side of the buffer layer 200 away from the substrate 100, and forming an active layer 310 after coating photoresist, mask exposure, development, etching and stripping the photoresist.

[0067] In a specific example, Figure 8 As shown, the orthographic projection of the channel region of the active layer 310 on the substrate 100 at least partially overlaps with the orthographic projection of the light-shielding metal layer 210 on the substrate 100 .

[0068] In a specific example, Figure 8As shown, the active layer 310 can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), amorphous silicon (a-Si), polysilicon (Poly-silicon), sexithiophene or polythiophene.

[0069] In another specific example, Figure 8 As shown, the material of the active layer 310 can be a semiconductor oxide material, such as any one or more of indium gallium zinc oxide (IGZO), amorphous or polycrystalline zinc oxide (ZnO), indium zinc oxide (IZO), zinc tin oxide (ZTO), zinc tin oxide (IZTO), gallium zinc tin oxide (IGZTO), and indium gallium oxide (IGO).

[0070] This example is applicable to display substrates based on top-gate thin film transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0071] In a specific example, Figure 8 As shown, the active layer 310 is made of low temperature polysilicon (LTPS). The active layer includes a channel region and doped regions located at both ends of the channel region, wherein the doped regions include a heavily doped region and a lightly doped region located between the heavily doped region and the channel region.

[0072] In a specific example, Figure 8 As shown, the heavily doped region is a high-concentration N-type doping region, which can make the thin film transistor easy to form an ohmic contact; the lightly doped region is used to reduce the electric field strength of the source-drain junction region and improve the stability of the device.

[0073] Step S6: forming a gate insulating layer on a side of the active layer away from the substrate;

[0074] In a specific example, Figure 9 As shown, step S6 includes depositing a gate insulating layer 300 on a side of the active layer 310 away from the buffer layer 200 , and the gate insulating layer 300 covers the active layer 310 and the buffer layer 200 .

[0075] In a specific example, Figure 9 As shown, the gate insulating layer 300 may be made of at least one of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, or a high dielectric constant material such as aluminum oxide (AlOx), hafnium oxide (HfOx), or tantalum oxide (TaOx). Furthermore, the gate insulating layer 300 may be a single layer, multiple layers, or a composite layer.

[0076] In a specific example, Figure 9 As shown, the gate insulating layer can be deposited by chemical vapor deposition, plasma chemical vapor deposition, sputtering, vacuum evaporation, etc.

[0077] The gate insulating layer in this example can improve wear resistance and insulation performance.

[0078] Step S7: forming a gate layer on a side of the gate insulating layer away from the substrate;

[0079] In a specific example, Figure 10 As shown, step S7 includes depositing a gate material film layer on the side of the gate insulation layer 300 away from the substrate 100, and after coating photoresist, mask exposure, development, etching and stripping the photoresist, forming a gate 410 located in the display area and a third metal layer 420 in the fan-out area.

[0080] In a specific example, Figure 10 As shown, a whole metal conductive layer is formed on the gate insulating layer 300. The material of the whole metal conductive layer is metal, such as aluminum, molybdenum, titanium, chromium or copper; or the material of the whole metal conductive layer is metal oxide, such as titanium oxide; or the material of the whole metal conductive layer is metal alloy or other conductive materials, which can be multi-layer metal, such as Mo / Cu / Mo, or a stack structure formed by metal and transparent conductive material, such as ITO / Ag / ITO; then the whole metal conductive layer is patterned to obtain a gate 410 located in the display area and a third metal layer 420 in the fan-out area with a predetermined pattern.

[0081] Step S8: forming a dielectric layer on a side of the gate layer away from the substrate;

[0082] In a specific example, Figure 11 As shown, step S8 includes depositing a dielectric layer 400 on a side of the gate layer away from the substrate 100 , wherein the dielectric layer 400 covers the gate 410 in the display area, the third metal layer 420 in the fan-out area, and the gate insulating layer 300 .

[0083] In a specific example, Figure 11 As shown, the material of the dielectric layer 400 may be at least one of silicon nitride or silicon oxide, but is not limited thereto.

[0084] Step S9: forming a first via hole, a second via hole, and a third via hole in the dielectric layer, the gate insulating layer, the active layer, and the buffer layer;

[0085] In a specific example, Figure 12 As shown, step S9 includes coating the dielectric layer with photoresist, exposing the dielectric layer through a mask, developing, etching, and stripping the photoresist to form a first via hole 540 , a second via hole 550 , and a third via hole 560 .

[0086] In a specific example, Figure 12As shown, the first via hole 540 penetrates the dielectric layer 400 , the gate insulating layer 300 , the active layer 310 and the buffer layer 200 in the display area, so that the first via hole 540 exposes the isolation layer 2000 corresponding to the first via hole 540 in the display area.

[0087] In a specific example, Figure 12 As shown, the second via hole 550 penetrates the dielectric layer 400 , the gate insulating layer 300 and the buffer layer 200 , so that the second via hole 550 exposes the second metal layer 220 corresponding to the second via hole 550 in the fan-out region.

[0088] When etching the first via and the second via at the same time, in order to fully connect part of the first metal layer 502 and the second metal layer 202 of the fan-out area 2, the second via needs to be over-etched when etching the second via. Since the orthographic projection of the metal shading layer 201 of the display area 1 on the substrate 10 does not overlap with the orthographic projection of the first via on the substrate 10, the first via in the display area 1 penetrates the buffer layer 20 during over-etching, thereby causing the subsequent drain-source metal layer 501 of the display area 1 and the substrate 10 to contact each other.

[0089] In a specific example, Figure 12 As shown, the third via hole 560 penetrates the dielectric layer 400 , so that the third via hole 560 exposes the third metal layer 420 corresponding to the third via hole 560 in the fan-out region.

[0090] Depend on Figure 12 It can be seen that when the first via 540, the second via 550 and the third via 560 are simultaneously etched, the second via 550 in the fan-out area needs to be etched through the dielectric layer 400, the gate insulating layer 300 and the buffer layer 200 to the second metal layer 220, and the first via 540 in the display area simultaneously penetrates the dielectric layer 400, the gate insulating layer 300, the active layer 310 and the buffer layer 200 to the isolation layer 2000, thereby blocking the impurity ions in the glass substrate 100 from diffusing into the thin film transistor and the box substrate through the isolation layer 200.

[0091] In a possible implementation, an orthographic projection of the light shielding layer on the substrate does not overlap with an orthographic projection of the first via hole on the substrate.

[0092] In a specific example, Figure 12 As shown, the orthographic projection of the metal light shielding layer 210 on the substrate 100 does not overlap with the orthographic projection of the first via hole 540 on the substrate 100 .

[0093] In this example, the metal light shielding layer of the display area is designed to avoid the first via hole, which can prevent uneven etching of the dielectric layer.

[0094] Step S10: forming a source / drain metal layer and a plurality of partial first metal layers on a side of the dielectric layer away from the substrate;

[0095] In a specific example, Figure 13 As shown, step S10 includes depositing a source-drain metal material layer on the side of the dielectric layer 400 away from the substrate 100, and after coating photoresist, mask exposure, development, etching and stripping the photoresist, forming a source-drain metal layer 510 located in the display area, a portion of the first metal layer 520 located in the fan-out area, and a portion of the first metal layer 530 located in the fan-out area.

[0096] In a specific example, Figure 13 As shown, the materials of the source / drain metal layer 510 , a portion of the first metal layer 520 and a portion of the first metal layer 530 may be metals such as Mo / Al / Mo, Ti / Al / Ti, etc., but are not limited thereto.

[0097] In a specific example, Figure 13 As shown, the source / drain metal layer 510 contacts the isolation layer 2000 through a first via hole penetrating the dielectric layer 400 , the gate insulating layer 300 , the active layer 310 and the buffer layer 200 .

[0098] In one possible implementation, in the fan-out area, part of the first metal layer is connected to the second metal layer through a second via penetrating the dielectric layer, the gate insulation layer and the buffer layer, the first metal layer is arranged on the same layer as the source and drain metal layer, the light-shielding layer is a metal light-shielding layer, and the second metal layer is arranged on the same layer as the metal light-shielding layer.

[0099] In a specific example, Figure 13 As shown, in the fan-out area, part of the first metal layer 520 is connected to the second metal layer 220 through a second via penetrating the dielectric layer 400, the gate insulation layer 300 and the buffer layer 200; part of the first metal layer 520 is arranged on the same layer as the source and drain metal layer 510; and the second metal layer 220 is arranged on the same layer as the metal light shielding layer 210.

[0100] In this example, overlapping wiring is performed in the fan-out area through part of the first metal layer and the second metal layer to achieve overlapping settings of multiple signal traces and reduce the occupied area of the signal traces.

[0101] In a possible implementation, in the fan-out region, a portion of the first metal layer is connected to a third metal layer through a third via penetrating the dielectric layer, and the third metal layer is provided in the same layer as the gate.

[0102] In a specific example, Figure 13As shown, in the fan-out region, part of the first metal layer 530 is connected to the third metal layer 420 through a third via penetrating the dielectric layer 400 ; the third metal layer 420 is disposed on the same layer as the gate 410 .

[0103] In this example, overlapping routing is performed in the fan-out area through part of the first metal layer and the third metal layer to achieve overlapping settings for multiple signal traces and reduce the area occupied by the signal traces.

[0104] like Figure 13 As shown, in the fan-out area, part of the first metal layer is electrically connected to the second metal layer, and part of the first metal layer is electrically connected to the third metal layer, so that multiple signal lines are arranged in each layer, and the lead-out of the source and drain metal layers includes the lead-out of the first metal layer, the lead-out of the second metal layer, and the lead-out of the third metal layer. By arranging multiple signal lines in the three-layer conductive layers arranged in a stacked manner, the overlapping arrangement of multiple signal lines can be achieved, the occupied area of the signal lines can be reduced, the wiring space can be reduced, the bottom frame of the display panel can be reduced, and an extremely narrow frame design can be achieved.

[0105] Step S11: forming a planar layer on a side of the source / drain metal layer and a plurality of portions of the first metal layer away from the substrate;

[0106] In a specific example, Figure 14 As shown, step S11 includes forming a flat layer 500 on the side of the source / drain metal layer 510, a portion of the first metal layer 520 and a portion of the first metal layer 530 away from the substrate 100, and the flat layer 500 covers the source / drain metal layer 510, a portion of the first metal layer 520, a portion of the first metal layer 530 and the dielectric layer 400.

[0107] Step S12: forming a common electrode on a side of the planar layer away from the substrate;

[0108] In a specific example, Figure 15 As shown, step S12 includes depositing a common electrode material film layer on the side of the flat layer 500 away from the substrate 100, and forming a common electrode 620 after coating with photoresist, mask exposure, development, etching and stripping of the photoresist. The common electrode 620 includes a groove 630 located in the display area, and the groove 630 exposes the flat layer 500 corresponding to the groove 630 in the display area, and the orthographic projection of the groove 630 on the substrate 100 covers the orthographic projection of the source and drain metal layer 510 on the substrate 100.

[0109] In a specific example, Figure 15 As shown, the common electrode 620 may be made of a transparent conductive material, such as indium tin oxide material, indium zinc oxide material, carbon nanotubes or graphene, etc.

[0110] Step S13: forming a through hole in the flat layer;

[0111] In a specific example, Figure 16 As shown, step S13 includes forming a through hole 631 in the position corresponding to the groove 630 in the planar layer 500 after coating photoresist, mask exposure, development, etching and stripping the photoresist, and exposing the source and drain metal layer 510 corresponding to the through hole 631 in the display area.

[0112] Step S14: forming a passivation layer on a side of the common electrode away from the substrate;

[0113] In a specific example, Figure 17 As shown, step S14 includes forming a passivation layer 600 on a side of the common electrode 620 away from the substrate 100 ; the passivation layer 600 covers the common electrode 620 , the groove 630 of the common electrode 620 , the planar layer 500 and the through hole 631 of the planar layer 500 .

[0114] Step S15: forming a fourth via hole in the passivation layer and the planarization layer;

[0115] In a specific example, Figure 18 As shown, step S15 includes coating the passivation layer 600 in the display area with photoresist, exposing the mask, developing, etching and stripping the photoresist to form a fourth via hole 640; the fourth via hole 640 penetrates the passivation layer 600 and the planar layer 500, so that the fourth via hole 640 is exposed to the source and drain metal layer 510 corresponding to the fourth via hole 640 in the display area.

[0116] In a specific example, Figure 18 As shown, the orthographic projection of the fourth via hole 640 on the substrate is located within the orthographic projection of the groove 630 on the substrate.

[0117] In a specific example, Figure 18 As shown, the orthographic projection of the fourth via hole 640 on the substrate covers the orthographic projection of the source / drain metal layer 510 on the substrate.

[0118] Step S16: forming a pixel electrode on a side of the dimming layer away from the substrate;

[0119] In a specific example, Figure 19 As shown, step S16 includes depositing a pixel electrode material film layer on the passivation layer 600, coating a photoresist, exposing through a mask, developing, etching, and stripping the photoresist to form a pixel electrode 610.

[0120] In a specific example, Figure 19 As shown, the pixel electrode 610 is electrically connected to the source-drain metal layer 510 through the fourth via hole.

[0121] In a specific example, Figure 19As shown, the pixel electrode 610 may be made of a transparent conductive material, such as indium tin oxide material, indium zinc oxide material, carbon nanotube or graphene, etc., which is not specifically limited here.

[0122] In a possible implementation, the display substrate further includes a planar layer and a pixel electrode sequentially stacked on the driving circuit layer, and the pixel electrode is connected to the source / drain metal layer through a fourth via hole penetrating the planar layer.

[0123] In a specific example, Figure 19 As shown, a planar layer 500 and a pixel electrode 610 are sequentially stacked on the source-drain metal layer 510, a portion of the first metal layer 520, and a portion of the first metal layer 530. The pixel electrode 610 is connected to the source-drain metal layer 510 via a fourth via hole penetrating the planar layer 500. In this example, the pixel electrode is connected to the source and drain of the transistor through the fourth via hole.

[0124] In a specific example, Figure 19 As shown, there is no electrical connection between the pixel electrode 610 and the metal light shielding layer 210 .

[0125] This example solves the problem in the related art that the metal light-shielding layer and the pixel electrode are either connected or not connected, which causes inconsistent parasitic capacitance between the gate and drain of the thin-film transistor, resulting in inconsistent voltage difference (△Vp), and ultimately leading to inconsistent voltage of the common electrode, stains and other defects.

[0126] Another embodiment of the present disclosure provides a display module including the above-mentioned display substrate.

[0127] In a specific example, the manufacturing process of the display module includes providing a cell-aligning substrate and a liquid crystal layer located between the cell-aligning substrate and the display substrate.

[0128] Step S17: aligning the display substrate with the cell-aligning substrate, wherein a liquid crystal layer is provided between the cell-aligning substrate and the display substrate after the alignment.

[0129] In a specific example, Figure 3 As shown, the cell substrate includes a first alignment layer 700, the display substrate includes a second alignment layer 900, and the liquid crystal layer 800 is located between the first alignment layer 700 and the second alignment layer 900. In addition, the cell substrate further includes a second substrate ( Figure 3 Not shown in ) etc.

[0130] In a specific example, Figure 3 As shown, the common electrode 620 and the pixel electrode 610 are disposed on one side of the substrate 100 , and can form a horizontal electric field to drive the liquid crystal 800 to flip, thereby realizing the image display function.

[0131] It should be noted that Figures 4 to 19 The example shown is only one example of the preparation process of the display substrate provided by the embodiment of the present disclosure. In different examples, multiple layer structures can be formed simultaneously in one patterning process; the order of several steps in the preparation process can also be swapped; there is no specific limitation here, as long as the display module obtained in the preparation process is Figure 3 The display module provided by the embodiment of the present disclosure is shown.

[0132] This embodiment completely isolates the substrate from the driving circuit layer by adding an isolation layer between the substrate and the buffer layer, which can effectively solve the problem of impurity ion precipitation in the substrate, enhance the product's resistance to ion contamination, and improve product characteristics and display performance.

[0133] Yet another embodiment of the present disclosure provides a display device, including the display substrate provided by the present disclosure.

[0134] In a specific example, the display device may be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator, and this embodiment does not limit this.

[0135] This embodiment completely isolates the substrate from the driving circuit layer by adding an isolation layer between the substrate and the buffer layer, which can effectively solve the problem of impurity ion precipitation in the substrate, enhance the product's resistance to ion contamination, and improve product characteristics and display performance.

[0136] Obviously, the above embodiments of the present disclosure are merely examples for clearly illustrating the present disclosure, and are not intended to limit the implementation methods of the present disclosure. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is impossible to enumerate all the implementation methods here. Any obvious changes or modifications derived from the technical solution of the present disclosure are still within the scope of protection of the present disclosure.

Claims

1. A display substrate, characterized in that: The display substrate includes a substrate and an isolation layer, a light shielding layer, a buffer layer and a driving circuit layer stacked in sequence on the substrate. The driving circuit layer includes an active layer, a gate insulating layer, a gate, a dielectric layer and a source-drain metal layer stacked in sequence. The display substrate includes a display area and a fan-out area. In the display area, the source-drain metal layer contacts the isolation layer through a first via hole penetrating the dielectric layer, the gate insulating layer, the active layer and the buffer layer.

2. The display substrate according to claim 1, wherein: The thickness of the isolation layer is greater than and less than 3. The display substrate according to claim 1, wherein The isolation layer includes silicon nitride.

4. The display substrate according to claim 1, wherein In the fan-out area, part of the first metal layer is connected to the second metal layer through a second via penetrating the dielectric layer, the gate insulation layer and the buffer layer, the first metal layer is arranged on the same layer as the source and drain metal layer, the light-shielding layer is a metal light-shielding layer, and the second metal layer is arranged on the same layer as the metal light-shielding layer.

5. The display substrate according to claim 4, wherein: In the fan-out region, a portion of the first metal layer is connected to a third metal layer through a third via penetrating the dielectric layer, and the third metal layer is provided in the same layer as the gate.

6. The display substrate according to claim 1, wherein: An orthographic projection of the light shielding layer on the substrate does not overlap with an orthographic projection of the first via hole on the substrate.

7. The display substrate according to claim 1, wherein: The substrate is a glass substrate.

8. The display substrate according to claim 1, wherein: The display substrate further includes a planar layer and a pixel electrode sequentially stacked on the driving circuit layer, and the pixel electrode is connected to the source-drain metal layer through a fourth via hole penetrating the planar layer.

9. A display module, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 8.

10. The display module according to claim 9, wherein: The display module further includes a cell-matching substrate and a liquid crystal layer arranged between the display substrate and the cell-matching substrate.

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