Semiconductor photonic device

Abstract

The utility model provides a semiconductor photon device comprising a plurality of grating couplers, and each grating coupler is configured to couple a specific wavelength (or wavelength range) of an optical signal to an optical waveguide of the semiconductor photon device. In some embodiments, various embodiments of multiple optical signal separators or multiple filters described herein can pass individual wavelengths (or individual wavelength ranges) to each grating coupler (while filtering out other wavelengths or other wavelength ranges), therefore, individual wavelengths (or individual wavelength ranges) of the plurality of grating couplers can be processed. This enables multiple wavelengths (or multiple wavelength ranges) to be distributed to multiple grating couplers, which can increase the bandwidth of the semiconductor photonic device relative to a semiconductor photonic device comprising only a single grating coupler.

Description

Technical Field

[0001] The utility model relates to a semiconductor photon device. Background Art

[0002] In semiconductor photonics, multiple semiconductor materials, such as silicon, are used as optical transmission media. For example, semiconductor photonic devices can be used for optical communications and may include multiple coupling systems that convert between multiple electrical signals and multiple optical signals. Additionally, some semiconductor photonic devices may include multiple integrated electronic components on the same semiconductor substrate to process the multiple optical signals being transmitted or received. Utility Model Content

[0003] The present invention provides a semiconductor photonic device, comprising an optical transceiver. The semiconductor photonic device comprises an optical waveguide coupled to the optical transceiver. The semiconductor photonic device comprises a plurality of grating couplers coupled to the optical waveguide. The semiconductor photonic device comprises a plurality of anti-reflection coatings, wherein each of the plurality of anti-reflection coatings is above a respective one of the plurality of grating couplers. The semiconductor photonic device comprises a plurality of microlenses, wherein each of the plurality of microlenses is above a respective one of the plurality of anti-reflection coatings.

[0004] The present invention provides a semiconductor photonic device, comprising an optical transceiver. The semiconductor photonic device comprises an optical waveguide coupled to the optical transceiver. The semiconductor photonic device comprises a plurality of grating couplers coupled to the optical waveguide. The semiconductor photonic device comprises a plurality of color filter layers, wherein each of the plurality of color filter layers is above a respective one of the plurality of grating couplers. The semiconductor photonic device comprises an antireflection coating above the plurality of color filter layers. The semiconductor photonic device comprises a microlens above one or more of the plurality of color filter layers.

[0005] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with the attached Figure 1 The following detailed description will best illustrate the present invention and the drawings. It should be noted that, in accordance with standard industry practice, the features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased for clarity of discussion.

[0007] Figure 1 is a diagram of an example environment in which the systems and / or methods described herein may be implemented.

[0008] Figures 2A to 2F are multiple diagrams of example semiconductor photonic devices described herein.

[0009] Figures 3A to 3H are diagrams of an example embodiment of forming a first semiconductor die described herein.

[0010] Figures 4A to 4J are diagrams of an example embodiment of forming a second semiconductor die described herein.

[0011] Figures 5A to 5F are diagrams of example embodiments of forming semiconductor photonic devices described herein.

[0012] Figures 6A to 6C are multiple diagrams of example semiconductor photonic devices described herein.

[0013] Figures 7A to 7E are diagrams of an example embodiment of forming a second semiconductor die described herein.

[0014] Figures 8A to 8C are multiple diagrams of example semiconductor photonic devices described herein.

[0015] Figures 9A to 9D are diagrams of an example embodiment of forming a second semiconductor die described herein.

[0016] Figures 10A to 10C are multiple diagrams of example semiconductor photonic devices described herein.

[0017] Figures 11A to 11E are diagrams of an example embodiment of forming a second semiconductor die described herein.

[0018] Figure 12 is a diagram of several example components of the devices described herein.

[0019] Figure 13 is a flow chart of an example process associated with forming the semiconductor photonic devices described herein.

[0020] Description of Reference Numerals

[0021] 100: Example Environment

[0022] 102: Deposition Tools

[0023] 104: Exposure Tools

[0024] 106: Development Tools

[0025] 108: Etching tools

[0026] 110: Flattening tool

[0027] 112: Electroplating tools

[0028] 114: Ion implantation tools

[0029] 116: Wafer / die transfer tool

[0030] 200, 600, 800, 1000: semiconductor photonic devices

[0031] 202: First semiconductor die

[0032] 204: Second semiconductor die

[0033] 206: Bonding interface

[0034] 208, 246: Semiconductor substrate

[0035] 210: Installation area

[0036] 212, 234, 236, 238, 264, 270: Dielectric layer

[0037] 214, 226, 266: Metallization layer

[0038] 216: Optical transceiver

[0039] 218: Optical waveguide

[0040] 220, 220a to 220d: Grating coupler

[0041] 222: Rewiring layer

[0042] 224: Electrical insulation layer

[0043] 228: Conductive pad

[0044] 230, 240: connection structure

[0045] 232: Die connection area

[0046] 242: Contact

[0047] 244, 268: Bonding pads

[0048] 248, 248a to 248d: Microlenses

[0049] 250: Layer Stack

[0050] 252, 254, 256, 258: layers

[0051] 260, 260a to 260d: Anti-reflective coating

[0052] 262: Oxide filling area

[0053] 272: Protective layer

[0054] 274, 274a to 274d: Optical signal

[0055] 276: First Floor

[0056] 278: Second Floor

[0057] 280: Electrical output signal

[0058] 282: Electrical input signal

[0059] 300, 400, 500, 700, 900, 1100: Example embodiments

[0060] 302: Semiconductor layer

[0061] 602, 602a to 602d: color filter layer

[0062] 702, 706: Color filter material layer

[0063] 704, 708: Photoresist layer

[0064] 902: Depression

[0065] 1002: Grating structure

[0066] 1102: Grating material layer

[0067] 1104: Raster

[0068] 1200: Device

[0069] 1210: Bus

[0070] 1220: Processor

[0071] 1230: Memory

[0072] 1240: Input component

[0073] 1250: Output component

[0074] 1260: Communication components

[0075] 1300: Example Process

[0076] 1310, 1320, 1330, 1340: Block Diagram DETAILED DESCRIPTION

[0077] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. As shown, for example, in the following description, forming a first feature or upper and second features may include embodiments in which the first and second features are directly formed in contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be directly in contact. In addition, in various examples, the present invention may be repeated reference numbers and / or letters. This repetition is for the purpose of simplicity and clarity and does not itself specify the relationship between the various embodiments and / or architectures discussed.

[0078] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another component or feature(s), as shown in the figures. Spatially relative terms are intended to encompass different orientations of a component in use or operation in orientations other than those depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0079] In some cases, a semiconductor photonic device may include a grating coupler, an optical transceiver, and an optical waveguide coupling the grating coupler and the optical transceiver. The grating coupler may be configured to guide an optical signal (e.g., a laser signal or incident light) to and / or from the optical waveguide. The detector may convert the optical signal into an electrical signal (e.g., when the optical signal is received by the semiconductor photonic device) and / or may convert the electrical signal into an optical signal (e.g., when the optical signal is transmitted by the semiconductor photonic device).

[0080] In high-bandwidth optical communications, data can be multiplexed onto different wavelengths of an optical signal. This enables larger amounts of data to be transmitted over an optical signal compared to single-frequency optical signals, thus enabling higher-bandwidth optical communications. However, the bandwidth of a semiconductor photonic device may be limited by one or more components of the semiconductor photonic device. For example, a grating coupler in a semiconductor photonic device may only be able to handle a limited bandwidth due to the multiplexing of data onto different wavelengths of the optical signal.

[0081] In some embodiments described herein, a semiconductor photonic device includes a plurality of grating couplers, each grating coupler configured to couple a specific wavelength (or wavelength range) of an optical signal to an optical waveguide of the semiconductor photonic device. In some embodiments, various embodiments of the plurality of optical signal splitters or filters described herein enable a respective wavelength (or wavelength range) to be passed to each grating coupler (while filtering out other wavelengths or wavelength ranges), thereby enabling the plurality of grating couplers to each process a respective wavelength (or wavelength range). This enables the plurality of wavelengths (or wavelength ranges) to be distributed across the plurality of grating couplers, which can increase the bandwidth of the semiconductor photonic device relative to a semiconductor photonic device including only a single grating coupler.

[0082] Figure 1 1 is a diagram of an example environment 100 in which the various systems and / or various methods described herein may be implemented. Figure 1As shown, environment 100 may include a plurality of semiconductor process tools 102 to 114 and a wafer / die transport tool 116. The plurality of semiconductor process tools 102 to 114 may include a deposition tool 102, an exposure tool 104, a developer tool 106, an etch tool 108, a planarization tool 110, a plating tool 112, an ion implantation tool 114, and / or another type of semiconductor process tool. The plurality of tools included in example environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and / or a semiconductor manufacturing facility, among other examples.

[0083] Deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing a plurality of materials of various types onto a substrate. In some embodiments, deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate, such as a wafer. In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma enhanced CVD (PECVD) tool, a low-pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or other type of PVD tool. In some embodiments, example environment 100 includes multiple deposition tools 102 of different types. As used herein, "deposition tool 102" may refer to one or more deposition tools 102, one or more deposition tools 102 of the same type, and / or one or more deposition tools 102 of different types, among other examples.

[0084] The exposure tool 104 is a semiconductor process tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep ultraviolet light source, an extreme ultraviolet light (EUV) source, and / or the like), an X-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. This pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include patterns for forming one or more structures of a semiconductor device, can include patterns for etching various portions of a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0085] The development tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source, thereby developing the pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the development tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some embodiments, the development tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, the development tool 106 develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

[0086] The etch tool 108 is a type of semiconductor processing tool capable of etching a plurality of materials of a substrate, wafer, or semiconductor device. For example, the etch tool 108 may include a wet etch tool, a dry etch tool, or the like. In some embodiments, the etch tool 108 includes a chamber filled with an etchant, and a substrate is placed in the chamber for a specific period of time to remove one or more specific amounts of the substrate. In some embodiments, the etch tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may include using an ionized gas to etch the one or more portions isotropically or directionally.

[0087] Planarization tool 110 is a semiconductor processing tool capable of grinding or planarizing layers of a wafer or semiconductor device. For example, planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that grinds or planarizes layers or surfaces of deposited or plated materials. Planarization tool 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and abrasive-free polishing) to grind or planarize the surface of a semiconductor device. Planarization tool 110 may utilize abrasive and corrosive chemical slurries in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and semiconductor device may be pressed together by a dynamic polishing head and secured by the retaining ring. The dynamic polishing head can rotate along different axes of rotation to remove material and smooth out any irregularities in the semiconductor device, thereby making the semiconductor device flat or planar.

[0088] The electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion thereof with one or more metals. For example, the electroplating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound or alloy (e.g., a wafer, a semiconductor device, and / or the like) electroplating device, and / or one or more other electroplating devices for conductive materials, metals, and / or similar materials.

[0089] The ion implantation tool 114 is a semiconductor process tool capable of implanting multiple ions into a substrate. The ion implantation tool 114 can generate multiple ions from a source material such as a gas or solid in an arc chamber. The source material can be provided to the arc chamber, and an arc voltage is discharged between a cathode and an electrode to generate a plasma containing multiple ions of the source material. One or more extraction electrodes can be used to extract multiple ions from the plasma in the arc chamber and accelerate the multiple ions to form an ion beam. The ion beam can be directed toward the substrate so that multiple ions are implanted below the surface of the substrate.

[0090] The wafer / die transfer tool 116 may be included in a cluster tool or another type of tool including multiple process chambers, and may be configured to transfer multiple substrates and / or multiple semiconductor devices between multiple process chambers, transfer multiple substrates and / or multiple semiconductor devices between a process chamber and a buffer, transfer multiple substrates and / or multiple semiconductor devices between a process chamber and an interface tool such as an equipment front end module (EFEM), and / or transfer multiple substrates and / or multiple semiconductor devices between a process chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), among other examples. In some embodiments, the wafer / die transfer tool 116 may be included in a multi-chamber (or cluster) deposition tool 102, which may include pre-clean process chambers (e.g., for cleaning or removing oxides, oxidation, and / or other types of contamination or byproducts from substrates and / or semiconductor devices) and multiple types of deposition process chambers (e.g., multiple process chambers for depositing multiple different types of materials, multiple process chambers for performing multiple different types of deposition operations).

[0091] In some embodiments, one or more of the semiconductor process tools 102 to 114 may perform one or more semiconductor process operations described herein. For example, one or more of the semiconductor process tools 102 to 114 may form an optical transceiver, an optical waveguide coupled to the optical transceiver, and a plurality of grating couplers coupled to the optical waveguide in a first semiconductor die. In another example, one or more of the semiconductor process tools 102 to 114 may form one or more anti-reflective coating (ARC) layers in a second semiconductor die. In another example, one or more of the semiconductor process tools 102 to 114 may bond the first semiconductor die to the second semiconductor die to form a semiconductor photonics device, wherein after bonding the first semiconductor die to the second semiconductor die, the one or more anti-reflective coatings are located over at least a subset of the plurality of grating couplers. As another example, one or more of the semiconductor process tools 102 to 114 may form one or more micro lenses on one or more anti-reflective coatings after bonding the first semiconductor die to the second semiconductor die. One or more of the semiconductor process tools 102 to 114 may perform other semiconductor process operations described herein, such as in conjunction with Figures 3A to 3G 、 Figures 4A to 4J 、 Figures 5A to 5F 、 Figures 7A to 7E 、 Figures 9A to 9D 、 Figures 11A to 11E , and / or Figure 13 etc.

[0092] Figure 1 The number and arrangement of devices shown are provided as one or more examples. In practice, there may be more than Figure 1 The devices shown may include additional devices, fewer devices, different devices, or devices in different arrangements. Figure 1 Two or more of the devices shown may be implemented in a single device, or Figure 1 A single device shown in the example environment 100 may be implemented as multiple distributed devices. Additionally or alternatively, one or more devices of the example environment 100 may perform one or more functions described as being performed by another set of devices of the example environment 100.

[0093] Figures 2A-2F2 are diagrams of an example semiconductor photonic device 200 described herein. The semiconductor photonic device 200 may include a photonic integrated circuit (PIC), such as an optically coupled circuit. Generally speaking, the semiconductor photonic device 200 may be configured to convert between multiple electrical signals and multiple optical signals for high-bandwidth optical communications.

[0094] Figure 2A 1 shows a cross-sectional view of a semiconductor photonic device 200. Figure 2A As shown, the semiconductor photonic device 200 may include a first semiconductor die 202 and a second semiconductor die 204. The plurality of semiconductor dies 202 and 204 may each include one or more dies or chiplets, one or more die packages, etc. The first semiconductor die 202 and the second semiconductor die 204 may be bonded at a bonding interface 206. In this manner, the first semiconductor die 202 and the second semiconductor die 204 may be stacked or vertically arranged in the semiconductor photonic device 200.

[0095] The first semiconductor die 202 may include a semiconductor substrate 208 and a device region 210 above the semiconductor substrate 208. The semiconductor substrate 208 may include a silicon (Si) substrate and / or other types of semiconductor substrates. The device region 210 may include a dielectric layer 212 and a plurality of metallization layers 214 in the dielectric layer 212. The dielectric layer 212 may include one or more dielectric materials, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials.

[0096] The plurality of metallization layers 214 may provide signal paths for propagating a plurality of electrical signals in the first semiconductor die 202 and / or between the first semiconductor die 202 and the second semiconductor die 204. The plurality of metallization layers 214 may each include a via, a trench, a contact plug, a conductive pad, a conductive pillar, and / or another type of metallization layer. The plurality of metallization layers 214 may include tungsten (W), titanium (Ti), copper (Cu), ruthenium (Ru), cobalt (Co), and / or other conductive materials. In some embodiments, the plurality of metallization layers 214 may be surrounded by one or more liners, such as an adhesion layer, a barrier layer, and / or another type of liner.

[0097] The device region 210 of the first semiconductor die 202 may further include an optical transceiver 216, an optical waveguide 218 coupled to the optical transceiver 216, and a plurality of grating couplers 220 (e.g., grating couplers 220a to 220d) coupled to the optical waveguide 218. The optical transceiver 216 may be coupled to one or more metallization layers 214 to enable a plurality of electrical signals to be provided to and / or provided from the optical transceiver 216. The optical transceiver 216 may include a photodetector, a photodiode, an optical modulator, and / or another type of semiconductor device configured to convert a plurality of electrical signals into a plurality of optical signals and / or convert a plurality of optical signals into a plurality of electrical signals.

[0098] The optical waveguide 218 may include a device configured to confine multiple optical signals and allow the multiple optical signals to propagate between the optical transceiver 216 and the multiple grating couplers 220. In some embodiments, the optical waveguide 218 includes a semiconductor optical waveguide, such as a silicon optical waveguide. In some embodiments, the optical waveguide 218 includes a dielectric optical waveguide.

[0099] The plurality of grating couplers 220 may include a plurality of semiconductor structures (e.g., a plurality of silicon (Si) structures and / or other types of semiconductor structures) configured to guide a plurality of optical signals to and / or from the optical waveguide 218. Specifically, the plurality of grating couplers 220 may be configured to diffract the optical signals from an off-plane direction to an in-plane direction within the plane of the optical waveguide 218 (e.g., for receiving the optical signals). Additionally and / or alternatively, the grating couplers 220 may be configured to diffract the optical signals from an in-plane direction to an off-plane direction (e.g., for transmitting the optical signals).

[0100] Each grating coupler 220 may include a plurality of periodic gratings. The periodicity of the plurality of periodic gratings may be selected to achieve diffraction of a specific wavelength or wavelength range of an optical signal. For example, the periodicity of the plurality of periodic gratings of the grating coupler 220a may be selected to achieve diffraction of a first wavelength or a first wavelength range of an optical signal, the periodicity of the plurality of periodic gratings of the grating coupler 220b may be selected to achieve diffraction of a second wavelength or a second wavelength range of an optical signal, and so on. The plurality of wavelength ranges may be a plurality of non-overlapping wavelength ranges and / or a plurality of partially overlapping wavelength ranges. This enables each of the plurality of grating couplers 220a to 220d to process its own wavelength or its own wavelength range, which enables the bandwidth of the optical signal to be distributed to the plurality of grating couplers 220a to 220d rather than being processed by a single grating coupler. This enables the semiconductor photonic device 200 to process multiple signals of higher bandwidth than a semiconductor photonic device comprising only a single grating coupler. Each wavelength or wavelength range can carry multiple data multiplexed in the optical signal. For example, a first data stream can be transmitted on a first wavelength or a first wavelength range, a second data stream can be transmitted on a second wavelength or a second wavelength range, and so on. Figure 2A The number of grating couplers 220 a - 220 d shown is an example, and other numbers of grating couplers 220 are also within the scope of the present invention.

[0101] like Figure 2AAs further shown, a redistribution layer (RDL) 222 can be incorporated beneath the semiconductor substrate 208. The RDL 222 can include an electrically insulating layer 224, and one or more metallization layers 226 included in the electrically insulating layer 224 can include a polymer material such as polybenzoxazole (PBO), polyimide, low temperature polyimide (LTPI), epoxy resin, acrylic resin, phenol resin, and / or benzocyclobutene (BCB). Additionally and / or alternatively, the electrically insulating layer 224 may include a dielectric material such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials. The plurality of metallization layers 226 may each include a through-hole, a trench, a contact plug, a conductive pad, a conductive pillar, and / or another type of metallization layer. The plurality of metallization layers 214 may include aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), ruthenium (Ru), cobalt (Co), and / or other conductive materials.

[0102] The plurality of metallization layers 226 can be electrically and / or physically coupled to a plurality of conductive pads 228 beneath the redistribution layer 222. The plurality of conductive pads 228 can include conductive terminals, conductive pads, conductive pillars, under bump metallization (UBM) structures, controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and / or structures that enable the semiconductor photonic device 200 to be connected to and / or mounted on another structure, such as a semiconductor device package. The plurality of conductive pads 228 can each include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and / or another type of conductive material.

[0103] The plurality of metallization layers 226 can be further electrically and / or physically coupled to the plurality of metallization layers 214 via a plurality of connection structures 230 extending through the semiconductor substrate 208 and into the dielectric layer 212 of the device region 210. The plurality of connection structures 230 can include through silicon vias (TSVs), through package vias (TPVs), through dielectric vias (TDVs), and / or other types of connection structures. The plurality of connection structures 230 can each include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and / or another type of conductive material.

[0104] The first semiconductor die 202 may further include a die connection region 232 over the device region 210. The die connection region 232 includes a region of the first semiconductor die 202 connected to the second semiconductor die 204 and may include a plurality of dielectric layers 234, 236, and 238, among others. The plurality of dielectric layers 234 , 236 , and 238 may each include a dielectric material (e.g., the same dielectric material and / or different dielectric materials), such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SixNy), silicon oxide (SiOx), silicon nitride (SixNy), silicon oxide ... etc. (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials. Dielectric layer 234 may be included over and / or on dielectric layer 212 , dielectric layer 236 may be included over and / or on dielectric layer 234 , and dielectric layer 238 may be included over and / or on dielectric layer 236 .

[0105] A plurality of connection structures 240 may extend through dielectric layers 234 and 236 and may extend between device region 210 and dielectric layer 238. In addition, a plurality of contacts 242 may be included in dielectric layers 234 and 236. Both the plurality of connection structures 240 and the plurality of contacts 242 may include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and / or another type of conductive material.

[0106] A plurality of connection structures 240 may electrically couple the plurality of metallization layers 214 with a plurality of bond pads 244 in the dielectric layer 238. Each bond pad 244 may include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and / or another type of conductive material.

[0107] like Figure 2A As further shown, the second semiconductor die 204 may include a semiconductor substrate 246, such as a silicon (Si) substrate, etc. A plurality of microlenses 248, such as a plurality of microlenses 248a to 248d, may be formed in the top surface of the semiconductor substrate 246. The plurality of microlenses 248 may be configured to receive optical signals from an external optical fiber and / or another type of optical transmission medium and / or provide optical signals to an external optical fiber and / or another type of optical transmission medium.

[0108] Each microlens 248a-248d can include one or more properties selected to enable transmission of a specific wavelength or wavelength range of an optical signal. In this way, the properties of the multiple microlenses 248a-248d can be selected to split the optical signal into different wavelengths or wavelength ranges, which are then passed to the respective grating couplers 220a-220d. For example, the properties of microlens 248a can be selected to enable transmission of an optical signal of a first wavelength or wavelength range to grating coupler 220a, the properties of microlens 248b can be selected to enable transmission of an optical signal of a second wavelength or wavelength range to grating coupler 220b, and so on. This enables each of the grating couplers 220a-220d to process a respective wavelength or wavelength range, which enables the bandwidth of the optical signal to be distributed across the multiple grating couplers 220a-220d, rather than being handled by a single grating coupler. This enables the semiconductor photonic device 200 to process multiple signals of higher bandwidth than a semiconductor photonic device including only a single grating coupler.

[0109] The properties of the plurality of microlenses 248a to 248d may include a plurality of widths of the plurality of microlenses 248a to 248d, a plurality of heights or thicknesses of the plurality of microlenses 248a to 248d, and / or a plurality of curvatures of the plurality of microlenses 248a to 248d, etc. For example, microlens 248a may have a first width, microlens 248b may have a second width, and so on, where the plurality of widths are different widths. As another example, microlens 248a may have a first thickness, microlens 248b may have a second thickness, and so on, where the thicknesses are different thicknesses. As another example, microlens 248a may have a first curvature, microlens 248b may have a second curvature, and so on, where the plurality of curvatures are different curvatures.

[0110] A layer stack 250 may be included below the semiconductor substrate 246. The layer stack 250 may include a plurality of layers 252-258, which may include adhesion layers, passivation layers, glue layers, dielectric layers, and / or other types of layers. A plurality of anti-reflective coatings 260 may be included below the layer stack 250 in an oxide-filled region 262 of the second semiconductor die 204. The plurality of anti-reflective coatings 260, including a plurality of anti-reflective coatings 260a-260d, may be located above and / or over the plurality of grating couplers 220a-220d. For example, the anti-reflective coating 260a may be located above and / or over the grating coupler 220a, the anti-reflective coating 260b may be located above and / or over the grating coupler 220b, and so on. Figure 2A The number of the plurality of anti-reflective coating layers 260 a - 260 d shown is an example, and other numbers of the plurality of anti-reflective coating layers 260 are within the scope of the present invention.

[0111] Each anti-reflective coating 260 can include one or more layers and / or materials configured to reduce multiple reflections of an optical signal. The materials and / or properties of one or more layers can be selected to enable transmission of a particular wavelength or wavelength range of an optical signal, and to enable reflection of other wavelengths or wavelength ranges of the optical signal. In this manner, the materials and / or properties of one or more layers of the plurality of anti-reflective coatings 260a to 260d can be selected to separate the optical signal into different wavelengths or wavelength ranges, which are then transmitted to the respective grating couplers 220a to 220d. For example, the materials and / or properties of one or more layers of the anti-reflective coating 260a can be selected to enable transmission of a first wavelength or wavelength range of an optical signal to the grating coupler 220a (and block other wavelengths or wavelength ranges from being transmitted to the grating coupler 220a); the materials and / or properties of one or more layers of the anti-reflective coating 260b can be selected to enable transmission of a second wavelength or wavelength range of an optical signal to the grating coupler 220b (and block other wavelengths or wavelength ranges from being transmitted to the grating coupler 220b), and so on. This enables each of the grating couplers 220a to 220d to process a respective wavelength or a respective wavelength range, which enables the bandwidth of the optical signal to be distributed across the plurality of grating couplers 220a to 220d, rather than being processed by a single grating coupler. This enables the semiconductor photonic device 200 to process multiple signals with higher bandwidths than a semiconductor photonic device including only a single grating coupler.

[0112] like Figure 2AAs further shown, the second semiconductor die 204 may include a dielectric layer 264 adjacent to the oxide-filled region 262. The dielectric layer 264 may include a plurality of metallization layers 266 that are electrically and / or physically coupled to the dielectric layer 264 and a plurality of bond pads 268 in the dielectric layer 270 below the oxide-filled region 262. The plurality of metallization layers 266 and the plurality of bond pads 244 may each include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and / or another type of conductive material. Dielectric layer 264 and dielectric layer 270 may each include a dielectric material (e.g., the same dielectric material and / or different dielectric materials), such as silicon oxide (SixNy), silicon oxynitride (SixNy), silicon oxynitride (SixNy), silicon oxynitride (SixNy), silicon oxynitride (SixNy), silicon oxynitride (SixNy), etc. (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials. A protective layer 272 may be included over the top surface of semiconductor substrate 246 and over the plurality of microlenses 248.

[0113] The first semiconductor die 202 and the second semiconductor die 204 may be bonded at the bonding interface 206 such that the plurality of bond pads 244 and the plurality of bond pads 268 are coupled, and the dielectric layer 238 and the dielectric layer 270 are coupled. Therefore, the bond between the first semiconductor die 202 and the second semiconductor die 204 may be a hybrid bond, wherein the plurality of bond pads 244 and the plurality of bond pads 268 are bonded via metal-to-metal bonding, and the dielectric layer 238 and the dielectric layer 270 are bonded via dielectric-to-dielectric bonding.

[0114] Figure 2B FIG. 2 is a top view of a portion of a semiconductor photonic device 200. Figure 2BAs shown, the semiconductor photonic device 200 may include multiple groups of grating couplers 220, multiple microlenses 248, and multiple anti-reflective coatings 260, wherein each group may be configured to process a specific wavelength or wavelength range. For example, a first group may include a first grating coupler 220, a first microlens 248, and a first anti-reflective coating 260. The first group may be configured to guide an optical signal of a first wavelength or a first wavelength range to and / or from the optical waveguide 218; a second group may include a second grating coupler 220, a second microlens 248, and a second anti-reflective coating 260. The second group may be configured to guide an optical signal of a second wavelength or a second wavelength range to and / or from the optical waveguide 218. Other groups of grating couplers 220, microlenses 248, and anti-reflective coatings 260 may be configured in a similar manner. For each set of grating couplers 220 , microlenses 248 , and anti-reflective coatings 260 , the grating couplers 220 , microlenses 248 , and anti-reflective coatings 260 may be vertically arranged and vertically aligned such that the grating couplers 220 , microlenses 248 , and anti-reflective coatings 260 vertically overlap.

[0115] Figure 2C An example of using a grating coupler 220, a microlens 248, and an anti-reflection coating 260 set to separate multiple wavelengths or multiple wavelength ranges of an optical signal 274 is shown. Figure 2C As shown, a first wavelength (or first wavelength range) 274a can be transmitted through microlens 248a and directed to grating coupler 220a via anti-reflective coating 260a, wherein anti-reflective coating 260a is configured to reduce and / or minimize multiple reflections of the first wavelength 274a and reflect other wavelengths (or other wavelength ranges) of optical signal 274. First wavelength 274a can carry a first multiplexed data signal of optical signal 274.

[0116] The second wavelength (or second wavelength range) 274b can be transmitted through the microlens 248b and directed to the grating coupler 220b via the anti-reflective coating 260b, wherein the anti-reflective coating 260b is configured to reduce and / or minimize multiple reflections of the second wavelength 274b and reflect other wavelengths (or other wavelength ranges) of the optical signal 274. The second wavelength 274b can carry a second multiplexed data signal of the optical signal 274.

[0117] The third wavelength (or third wavelength range) 274c can be transmitted through the microlens 248c and directed to the grating coupler 220c via the anti-reflective coating 260c, wherein the anti-reflective coating 260c is configured to reduce and / or minimize multiple reflections of the third wavelength 274c and reflect other wavelengths (or other wavelength ranges) of the optical signal 274. The third wavelength 274c can carry a third multiplexed data signal of the optical signal 274.

[0118] A fourth wavelength (or a fourth wavelength range) 274 d can be transmitted through the microlens 248 d and directed to the grating coupler 220 d via the anti-reflective coating 260 d, wherein the anti-reflective coating 260 d is configured to reduce and / or minimize multiple reflections of the fourth wavelength 274 d and reflect other wavelengths (or other wavelength ranges) of the optical signal 274. The fourth wavelength 274 d can carry a fourth multiplexed data signal of the optical signal 274.

[0119] Figure 2C The number of wavelength components of the optical signal 274 shown in is an example, and other numbers are within the scope of the present invention.

[0120] Figure 2D An example of an anti-reflective coating 260 is shown. Figure 2D As shown, the anti-reflective coating 260 may include a multilayer structure in which a plurality of first layers 276 and a plurality of second layers 278 are arranged perpendicularly in an alternating manner. In other words, the plurality of first layers 276 and the plurality of second layers 278 alternate in a direction substantially perpendicular to the direction in which the anti-reflective coating 260 extends. In some embodiments, one or more properties of the plurality of first layers 276 and one or more properties of the plurality of second layers 278 may be selected to allow a specific wavelength or a specific wavelength range of the optical signal 274 to be transmitted through the anti-reflective coating 260. For example, the refractive indices of the plurality of first layers 276 and the plurality of second layers 278 may be different and may be selected to allow a specific wavelength or a specific wavelength range of the optical signal 274 to be transmitted through the anti-reflective coating 260. In other words, each first layer 276 may have a first refractive index and each second layer 278 may have a second refractive index, and the first and second refractive indices may be different refractive indices and may be selected to allow a specific wavelength or a specific wavelength range of the optical signal 274 to be transmitted through the anti-reflective coating 260.

[0121] As another example, the plurality of thicknesses of the plurality of first layers 276 and the plurality of second layers 278 can be different and can be selected to allow a particular wavelength or a particular range of wavelengths of the optical signal 274 to be transmitted through the anti-reflective coating 260. In other words, each first layer 276 can have a first thickness (e.g., an individual thickness of each first layer 276), each second layer 278 can have a second thickness (e.g., an individual thickness of each second layer 278), and the first and second thicknesses can be different thicknesses and can be selected to allow a particular wavelength or a particular range of wavelengths of the optical signal 274 to be transmitted through the anti-reflective coating 260. As an example, the plurality of first layers 276 can each have a thickness corresponding to approximately half a wavelength (e.g., λ / 2) that is to be transmitted through the anti-reflective coating 260, and the plurality of second layers 278 can each have a thickness corresponding to approximately one-quarter wavelength (e.g., λ / 4) that is to be transmitted through the anti-reflective coating 260.

[0122] Figure 2E and 2F An example of the operation of the semiconductor photonic device 200 is shown. Figure 2E An example of a receiving operation of the semiconductor photonic device 200 is shown for receiving an optical signal 274 . Figure 2F An example transmission operation of the semiconductor photonic device 200 is shown for transmitting an optical signal 274 .

[0123] like Figure 2E As shown, the optical signal 274 can be received through a plurality of micro lenses 248 (e.g., from an optical fiber). Each of the plurality of micro lenses 248 can be configured to direct a specific wavelength or a specific wavelength range to an associated anti-reflection coating 260, which then transmits the specific wavelength or the specific wavelength range to an associated grating coupler 220, such as in combination with Figure 2CThe plurality of grating couplers 220 provide a plurality of wavelengths or wavelength ranges of the optical signal 274 to the optical waveguide 218, which directs the wavelengths or wavelength ranges of the optical signal 274 to the optical transceiver 216. The optical transceiver 216 converts the plurality of wavelengths or wavelength ranges of the optical signal 274 into a plurality of electrical output signals 280, and provides the plurality of electrical output signals 280 to the plurality of conductive pads 228 via the plurality of metallization layers 214, the plurality of connection structures 240, the plurality of bonding pads 244 and 268, the plurality of metallization layers 266, the plurality of connection structures 230, and the plurality of metallization layers 226. Each wavelength or wavelength range of the plurality of optical signals 274 can be converted into a separate electrical output signal 280 that carries a data stream for the associated wavelength or wavelength range of the optical signal 274. In this manner, the plurality of grating couplers 220 , the plurality of microlenses 248 , and the plurality of anti-reflective coatings 260 enable the optical signal 274 to be demultiplexed and converted into the plurality of electrical output signals 280 .

[0124] like Figure 2F As shown, a plurality of electrical input signals 282 carrying a plurality of separate data streams can be provided from a plurality of conductive pads 228 to an optical transceiver 216 through the plurality of metallization layers 214, through the plurality of connection structures 240, through the plurality of bond pads 244 and 268, through the plurality of metallization layers 266, through the plurality of connection structures 230, and through the plurality of metallization layers 226. The optical transceiver 216 converts the plurality of electrical input signals 282 into a plurality of wavelengths or wavelength ranges of optical signals 274. The plurality of wavelengths or wavelength ranges of the optical signals 274 can be provided to respective grating couplers 220 through the optical waveguide 218. The plurality of grating couplers 220 guide the respective wavelengths or wavelength ranges through the associated plurality of anti-reflective coatings 260 and the associated plurality of microlenses 248, which multiplex the plurality of wavelengths or wavelength ranges of the optical signals 274. The optical signals 274 can be transmitted through the plurality of microlenses 248 (e.g., to an optical fiber).

[0125] As mentioned above, providing Figures 2A to 2F As an example. Other examples can be found in the Figures 2A to 2F There is a difference as described.

[0126] Figures 3A to 3H1 are diagrams of an example embodiment 300 for forming the first semiconductor die 202 described herein. In some embodiments, one or more of the semiconductor process operations described in connection with the example embodiment 300 may be performed using one or more of the plurality of semiconductor process tools 102 to 114 and / or through a wafer / die transfer tool 116. In some embodiments, one or more of the semiconductor process operations described in connection with the example embodiment 300 may be performed using another semiconductor process tool.

[0127] Please refer to Figure 3A , a substrate may be provided. The substrate may include a silicon on insulator (SOI) substrate including a semiconductor substrate 208 (e.g., a silicon substrate and / or another type of semiconductor substrate), a portion of a dielectric layer 212 (e.g., a buried oxide layer or a bottom oxide layer) over and / or on the semiconductor substrate 208, and / or a semiconductor layer 302 (e.g., a silicon (Si) layer and / or another type of semiconductor layer) over and / or on the portion of the dielectric layer 212. Alternatively, the semiconductor substrate 208 may be provided as a semiconductor chip, and the deposition tool 102 may be used to form a portion of the dielectric layer 212 over and / or on the semiconductor substrate 208, and another deposition tool 102 may be used to form the semiconductor layer 302 over and / or on the portion of the dielectric layer 212. The deposition tool 102 can be used to form the dielectric layer 212 using a chemical vapor deposition technique, a physical vapor deposition technique, an oxidation technique (e.g., a thermal oxidation technique), and / or another type of deposition technique. The deposition tool 102 can be used to form the semiconductor layer 302 using a chemical vapor deposition technique, a physical vapor deposition technique, an epitaxial technique, and / or another type of deposition technique.

[0128] like Figure 3BAs shown, the optical transceiver 216, the optical waveguide 218, and the plurality of grating couplers 220 can be formed from a semiconductor layer 302 in the device region 210 of the first semiconductor die 202. Additional portions of the dielectric layer 212 can be formed around the optical transceiver 216, the optical waveguide 218, and the plurality of grating couplers 220. In some embodiments, a pattern in the photoresist layer is used to etch the semiconductor layer 302 to form the optical transceiver 216, the optical waveguide 218, and the plurality of grating couplers 220. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on the semiconductor layer 302. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch the semiconductor layer 302 based on a pattern to form the optical transceiver 216, the optical waveguide 218, and the plurality of grating couplers 220 in the semiconductor layer 302. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to etching the semiconductor layer 302 based on a pattern. The deposition tool 102 can be used to deposit additional portions of the dielectric layer 212 using a chemical vapor deposition technique, a physical vapor deposition technique, an oxidation technique (e.g., a thermal oxidation technique), and / or another type of deposition technique.

[0129] In some embodiments, the ion implantation tool 114 can be used to dope various portions of the optical transceiver 216 to form a PN junction or a PIN junction, wherein an intrinsic / undoped region is included between a p-type doped region and an n-type doped region. The ion implantation tool 114 can be used to implant dopants into the semiconductor layer 302 to dope various portions of the optical transceiver 216.

[0130] like Figure 3CAs shown, multiple metallization layers 214 can be formed in multiple additional portions of the dielectric layer 212 to construct the device region 210. In some embodiments, the multiple metallization layers 214 can be referred to as the back-end of line (BEOL) region of the first semiconductor die 202. In some embodiments, the multiple metallization layers 214 can be constructed in multiple consecutive layers. For example, the deposition tool 102 can deposit a portion of the dielectric layer 212, the exposure tool 104, the development tool 106, the etching tool 108 can be used to form multiple recesses in the portion of the dielectric layer 212, and the deposition tool 102 and / or the electroplating tool 112 can be used to form the first metallization layer 214 (e.g., M1 metallization layer) in the multiple recesses. The deposition tool 102 and / or the electroplating tool 112 can be used to form the first metallization layer 214 (e.g., M1 metallization layer) in the recesses. Similar operations may be performed to form additional metallization layers 214 (eg, M2 metallization layer, M3 metallization layer, etc.).

[0131] like Figure 3D As shown, dielectric layer 234 can be formed over and / or on dielectric layer 212. Deposition tool 102 can be used to deposit dielectric layer 234 using a chemical vapor deposition technique, a physical vapor deposition technique, an oxidation technique (e.g., a thermal oxidation technique), and / or another type of deposition technique. In some embodiments, planarization tool 110 is used to planarize dielectric layer 234 after dielectric layer 234 is deposited.

[0132] like Figure 3E As shown, a plurality of contacts 242 can be formed in and / or on the dielectric layer 234 such that the plurality of contacts 242 are electrically and / or physically coupled to the one or more metallization layers 214. The exposure tool 104, the development tool 106, and the etching tool 108 can be used to form recesses in the dielectric layer 234 to expose the one or more metallization layers 214, and the deposition tool 102 and / or the plating tool 112 are used to form the plurality of contacts 242 in the plurality of recesses.

[0133] like Figure 3F As shown, dielectric layer 236 can be formed over and / or on dielectric layer 234. Dielectric layer 236 can cover a plurality of contacts 242. Deposition tool 102 can be used to deposit dielectric layer 236 using a chemical vapor deposition technique, a physical vapor deposition technique, an oxidation technique (e.g., a thermal oxidation technique), and / or another type of deposition technique. In some embodiments, planarization tool 110 is used to planarize dielectric layer 236 after dielectric layer 236 is deposited.

[0134] like Figure 3GAs shown, a plurality of connection structures 240 are formed through the dielectric layers 234 and 236 such that the plurality of connection structures 240 are electrically and / or physically coupled to one or more of the metallization layers 214. The exposure tool 104, the development tool 106, and the etching tool 108 may be used to form a plurality of recesses through the dielectric layers 234 and 236 to expose one or more of the metallization layers 214, and the deposition tool 102 and / or the plating tool 112 may be used to form the plurality of connection structures 240 in the plurality of recesses.

[0135] like Figure 3H As shown, dielectric layer 238 can be formed over and / or on dielectric layer 236. Dielectric layer 238 can cover a plurality of connection structures 240. Deposition tool 102 can deposit dielectric layer 238 using a chemical vapor deposition technique, a physical vapor deposition technique, an oxidation technique (e.g., a thermal oxidation technique), and / or another type of deposition technique. In some embodiments, planarization tool 110 is used to planarize dielectric layer 238 after dielectric layer 238 is deposited.

[0136] like Figure 3H As further shown, a plurality of bond pads 244 are formed through the dielectric layer 238 such that the plurality of bond pads 244 are electrically and / or physically coupled to the one or more connection structures 240. The exposure tool 104, the development tool 106, and the etching tool 108 can be used to form a plurality of recesses through the dielectric layer 238 to expose the one or more connection structures 240, and the deposition tool 102 and / or the plating tool 112 can be used to form the plurality of bond pads 244 in the plurality of recesses.

[0137] As mentioned above, providing Figures 3A to 3H As an example. Other examples can be found in the Figures 3A-3H Different than described.

[0138] Figures 4A to 4J 4 are diagrams of an example embodiment 400 for forming the second semiconductor die 204 described herein. In some embodiments, one or more of the semiconductor process operations described in connection with the example embodiment 400 may be performed using one or more of the plurality of semiconductor process tools 102 to 114 and / or through a wafer / die transfer tool 116. In some embodiments, one or more of the semiconductor process operations described in connection with the example embodiment 400 may be performed using another semiconductor process tool.

[0139] Please refer to Figure 4A, a substrate may be provided. The substrate may include a semiconductor substrate 246, which may include a silicon (Si) substrate and / or another type of semiconductor substrate. The semiconductor substrate 246 may be provided as a semiconductor wafer (e.g., a silicon chip) and / or another type of semiconductor workpiece.

[0140] like Figure 4B As shown, deposition tool 102 may be used to form layer stack 250 using a chemical vapor deposition technique, a physical vapor deposition technique, an oxidation technique (e.g., a thermal oxidation technique), and / or another type of deposition technique. For example, deposition tool 102 may be used to deposit layer 258 over and / or on semiconductor substrate 246, deposition tool 102 may be used to deposit layer 256 over and / or on layer 258, deposition tool 102 may be used to deposit layer 254 over and / or on layer 256, and / or deposition tool 102 may be used to deposit layer 252 over and / or on layer 254. In some embodiments, planarization tool 110 may be used to planarize one or more of layers 252-258 in layer stack 250.

[0141] like Figure 4C As shown, dielectric layer 264 can be formed over and / or on layer stack 250. Deposition tool 102 can be used to deposit dielectric layer 264 using a chemical vapor deposition technique, a physical vapor deposition technique, an oxidation technique (e.g., a thermal oxidation technique), and / or another type of deposition technique. In some embodiments, planarization tool 110 is used to planarize dielectric layer 264 after dielectric layer 264 is deposited.

[0142] like Figure 4D As shown, multiple metallization layers 266 can be formed in dielectric layer 264. In some embodiments, the pattern in the photoresist layer is used to etch dielectric layer 264 to form multiple recesses in dielectric layer 264. In these embodiments, deposition tool 102 can be used to form a photoresist layer on dielectric layer 264. Exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. Etching tool 108 can be used to etch dielectric layer 264 based on the pattern to form multiple recesses in dielectric layer 264. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove multiple remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to etching dielectric layer 264 based on the pattern.

[0143] The deposition tool 102 and / or the electroplating tool 112 can be operated in a chemical vapor deposition operation, a physical vapor deposition operation, an atomic layer deposition operation, an electroplating operation, a combination thereof, or the like. Figure 1 Another deposition operation is described for depositing metallization layer 266, and / or other suitable deposition operations. In some embodiments, a seed layer is first deposited, and the plurality of metallization layers 266 are deposited on the seed layer. In some embodiments, planarization tool 110 can be used to planarize the plurality of metallization layers 266 after depositing the plurality of metallization layers 266.

[0144] like Figure 4E As shown, dielectric layer 264 can be etched to remove multiple portions of dielectric layer 264. In some embodiments, the pattern in the photoresist layer is used to etch dielectric layer 264 to remove multiple portions of dielectric layer 264. In these embodiments, deposition tool 102 can be used to form a photoresist layer on dielectric layer 264 and / or multiple metallization layers 266. Exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. Etching tool 108 can be used to etch dielectric layer 264 based on the pattern to remove multiple portions of dielectric layer 264. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove multiple remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing and / or another technology). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of dielectric layer 264 .

[0145] like Figure 4F and 4G As shown, a plurality of antireflective coatings 260 may be formed over and / or on a portion of layer 252 that is exposed after removing portions of dielectric layer 264. Figure 4FAs shown, forming the plurality of anti-reflective coating layers 260 may include forming an anti-reflective coating layer 402 on the layer 252 (e.g., using the deposition tool 102), forming a photoresist layer 404 on the anti-reflective coating layer 402 (e.g., using the deposition tool 102), forming a pattern in the photoresist layer 404 (e.g., using the exposure tool 104 and the development tool 106), and removing portions of the anti-reflective coating layer 402 based on the pattern (e.g., using the etching tool 108) to form the anti-reflective coating layer 260d. Forming the plurality of anti-reflective coating layers 260 may include forming a layer 406 of anti-reflective coating on layer 252 and adjacent to anti-reflective coating 260 d (e.g., using deposition tool 102), forming a photoresist layer 408 on the layer 406 of anti-reflective coating and on the anti-reflective coating 260 d, forming a pattern in the photoresist layer 408 (e.g., using exposure tool 104 and development tool 106), and removing portions of the layer 406 of anti-reflective coating based on the photoresist layer 260 d (e.g., using etching tool 108) to form anti-reflective coating 260 c. Similar operations may be performed to form anti-reflective coatings 260 b and 260 a.

[0146] like Figure 4H As shown, oxide-filled regions 262 may be formed over and / or on anti-reflective coating 260, over and / or on dielectric layer 264, and over and / or on plurality of metallization layers 266. Deposition tool 102 may be used to deposit oxide-filled regions 262 using a chemical vapor deposition technique, a physical vapor deposition technique, an oxidation technique (e.g., a thermal oxidation technique), and / or another type of deposition technique. In some embodiments, planarization tool 110 may be used to planarize oxide-filled regions 262 after depositing oxide-filled regions 262.

[0147] like Figure 4IAs shown, a recess 410 can be formed through the oxide-filled region 262 to expose the dielectric layer 264 and the plurality of metallization layers 266. In some embodiments, a pattern in the photoresist layer is used to etch the oxide-filled region 262 to form the recess 410. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on the oxide-filled region 262. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the oxide-filled region 262 based on the pattern to form the recess 410 in the oxide-filled region 262. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of the oxide-filled regions 262 .

[0148] like Figure 4J As shown, dielectric layer 270 can be formed in recess 410 above and / or on dielectric layer 264. Dielectric layer 270 can cover multiple metallization layers 266. Deposition tool 102 can use chemical vapor deposition techniques, physical vapor deposition techniques, oxidation techniques (e.g., thermal oxidation techniques), and / or another type of deposition technique to deposit dielectric layer 270. In some embodiments, planarization tool 110 is used to planarize dielectric layer 270 after deposition so that the top surface of dielectric layer 270 and the top surface of oxide-filled region 262 are coplanar.

[0149] like Figure 4J As further shown, a plurality of bond pads 268 are formed through dielectric layer 270 such that the plurality of bond pads 268 are electrically and / or physically coupled to one or more of the plurality of metallization layers 266. Exposure tool 104, development tool 106, and etch tool 108 may be used to form a plurality of recesses through dielectric layer 270 to expose one or more metallization layers 266, and deposition tool 102 and / or plating tool 112 may be used to form the plurality of bond pads 268 in the plurality of recesses.

[0150] As mentioned above, providing Figures 4A to 4J As an example. Other examples can be found in the Figures 4A to 4J Different than described.

[0151] Figures 5A to 5Fis a diagram of an example embodiment 500 for forming the semiconductor photonic device 200 described herein. In some embodiments, one or more semiconductor process operations described in connection with the example embodiment 500 may be performed using one or more of a variety of semiconductor process tools 102 to 114 and / or through a wafer / die transfer tool 116. In some embodiments, one or more semiconductor process operations described in connection with the example embodiment 500 may be performed using another semiconductor process tool.

[0152] like Figure 5A As shown, a first semiconductor die 202 and a second semiconductor die 204 can be bonded at a bonding interface 206. The bonding interface 206 can include a metal-to-metal bond between a plurality of bonding pads 244 of the first semiconductor die 202 and a plurality of bonding pads 268 of the second semiconductor die 204. The bonding interface 206 can further include a dielectric-to-dielectric bond between a dielectric layer 238 of the first semiconductor die 202 and a dielectric layer 264 of the second semiconductor die 204.

[0153] like Figure 5B As shown, after bonding the first semiconductor die 202 and the second semiconductor die 204, a backside process may be performed on the second semiconductor die 204. The backside process may include forming a plurality of microlenses 248 in the backside surface of the semiconductor substrate 246, and forming a protective layer 272 on the backside surface of the semiconductor substrate 246 after forming the plurality of microlenses 248. Microlenses 248a may be formed over the anti-reflective coating 260a and over the grating coupler 220a; microlenses 248b may be formed over the anti-reflective coating 260b and over the grating coupler 220b, and so on.

[0154] In some embodiments, the pattern in the photoresist layer is used to etch the semiconductor substrate 246 to form the microlenses 248. In these embodiments, the deposition tool 102 can be used to form the photoresist layer on the semiconductor substrate 246. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch the semiconductor substrate 246 based on the pattern to form multiple microlenses 248 in the semiconductor substrate 246. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove multiple remaining portions of the photoresist layer (for example, using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to etching the semiconductor substrate 246 based on the pattern.

[0155] The deposition tool 102 can be used in physical vapor deposition operations, atomic layer deposition operations, chemical vapor deposition operations, epitaxial operations, oxidation operations, bonding operations, etc. Figure 1 The protective layer 272 may be deposited in another type of deposition operation and / or another deposition operation. In some embodiments, the protective layer 272 may conform to the contours of the plurality of microlenses 248 .

[0156] like Figures 5C to 5F As shown, after bonding the first semiconductor die 202 and the second semiconductor die 204, a backside process may be performed on the first semiconductor die 202. Figure 5D As shown, the backside process may include forming a plurality of connection structures 230 from the backside surface of the first semiconductor die 202 through the semiconductor substrate 208 and into the dielectric layer 212 to the one or more metallization layers 214 .

[0157] In some embodiments, the pattern in the photoresist layer is used to etch the semiconductor substrate 208 and the dielectric layer 212 to form a plurality of recesses through the semiconductor substrate 208 and into the dielectric layer 212. Portions of one or more metallization layers 214 may be exposed through the plurality of recesses. In these embodiments, the deposition tool 102 may be used to form a photoresist layer on the backside surface of the semiconductor substrate 208. The exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 may be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 may be used to etch the semiconductor substrate 208 and the dielectric layer 212 based on the pattern to form a plurality of recesses. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of the semiconductor substrate 208 and / or the dielectric layer 212 .

[0158] The deposition tool 102 and / or the electroplating tool 112 can be operated in a chemical vapor deposition mode, a physical vapor deposition mode, an atomic layer deposition mode, an electroplating mode, or a combination thereof. Figure 1 The plurality of connection structures 230 may be deposited by another deposition operation as described above and / or other suitable deposition operations. In some embodiments, a seed layer is first deposited, and the plurality of connection structures 230 are deposited on the seed layer. In some embodiments, the planarization tool 110 may be used to planarize the plurality of connection structures 230 after the plurality of connection structures 230 are deposited.

[0159] like Figure 5E As shown, a plurality of metallization layers 226 may be formed over and / or on the back surface of the semiconductor substrate 208 such that the plurality of metallization layers 226 are electrically and / or physically coupled to one or more connection structures 230. The deposition tool 102 and / or the electroplating tool 112 may be used in a chemical vapor deposition operation, a physical vapor deposition operation, an atomic layer deposition operation, an electroplating operation, or a combination thereof. Figure 1 The plurality of metallization structures 226 are deposited by another deposition operation as described above and / or other suitable deposition operations. In some embodiments, a seed layer is deposited first, and the plurality of metallization layers 226 are deposited on the seed layer. In some embodiments, the planarization tool 110 can be used to planarize the plurality of metallization layers 226 after depositing the plurality of metallization layers 226. In some embodiments, a conductive material layer is deposited on the backside surface of the semiconductor substrate 208, and the etching tool 108 is used to remove portions of the conductive material layer, wherein the plurality of remaining portions of the conductive material layer correspond to the plurality of metallization layers 226.

[0160] like Figure 5E As further shown, electrically insulating layer 224 can be formed over and / or on the back surface of semiconductor substrate 208. Electrically insulating layer 224 can encapsulate multiple metallization layers 226. Deposition tool 102 can be used to deposit a first portion of electrically insulating layer 224 using a chemical vapor deposition technique, a physical vapor deposition technique, an oxidation technique (e.g., a thermal oxidation technique), and / or another type of deposition technique. In some embodiments, deposition tool 102 can deposit the first portion of electrically insulating layer 224 in liquid form, which can be cured to remove solvent from the first portion of electrically insulating layer 224, thereby causing electrically insulating layer 224 to solidify and harden. In some embodiments, planarization tool 110 is used to planarize the first portion of electrically insulating layer 224 after depositing the first portion of electrically insulating layer 224.

[0161] like Figure 5F As shown, a plurality of conductive pads 228 may be attached to the semiconductor photonic device 200. Specifically, the conductive pads 228 may be attached to a plurality of metallization layers 226 on the back side of the second semiconductor die 204.

[0162] As mentioned above, providing Figures 5A to 5F As an example. Other examples can be found in the Figures 5A to 5F Different from what is described.

[0163] Figures 6A to 6C are multiple diagrams of an example semiconductor photonic device 600 described herein. The semiconductor photonic device 600 may include a photonic integrated circuit, such as an optically coupled circuit. Generally speaking, the semiconductor photonic device 600 may be configured to convert between multiple electrical signals and multiple optical signals for high-bandwidth optical communications.

[0164] Figure 6A FIG. 6 shows a cross-sectional view of a semiconductor photonic device 600. Figure 6A As shown, semiconductor photonic device 600 can include a combination and arrangement of multiple layers and / or multiple structures similar to semiconductor photonic device 200 described herein. For example, semiconductor photonic device 600 can include components 202 to 272. However, semiconductor photonic device 600 includes a single microlens 248 and a single anti-reflective coating 260 for multiple grating structures 220a to 220d. In addition, semiconductor photonic device 600 includes multiple color filter layers 602, such as color filter layers 602a to 602d. Figure 6A The number of color filter layers 602 shown is an example, and other numbers of color filter layers 602 are also within the scope of the present invention.

[0165] A plurality of color filter layers 602a to 602d may be included in the oxide-filled region 262. The plurality of color filter layers 602a to 602d may be included below the anti-reflective coating 260. The plurality of grating couplers 220, the microlenses 248, the anti-reflective coating 260, and the plurality of color filter layers 602 may be vertically aligned in the semiconductor photonic device 600. The microlenses 248 span the plurality of color filter layers 602a to 602d.

[0166] The plurality of color filter layers 602 can be configured to filter specific wavelengths or wavelength ranges of the optical signal. Furthermore, each of the plurality of color filter layers 602a through 602d can be configured to filter a respective wavelength or wavelength range of the optical signal. The plurality of materials and / or properties of the plurality of color filter layers 602a through 602d can be selected to transmit specific wavelengths or wavelength ranges of the optical signal and to reflect other wavelengths or wavelength ranges of the optical signal. In this manner, the plurality of materials and / or properties of the plurality of color filter layers 602a through 602d can be selected to separate the optical signal into different wavelengths or wavelength ranges, which are then passed to respective grating couplers 220a through 220d. For example, the materials and / or properties of the color filter layer 602a can be selected to enable transmission of a first wavelength or wavelength range of an optical signal to the grating coupler 220a (and to reflect other wavelengths or wavelength ranges so as to prevent transmission to the grating coupler 220a); the materials and / or properties of the color filter layer 602b can be selected to enable transmission of a second wavelength or wavelength range of an optical signal to the grating coupler 220b (and to reflect other wavelengths or wavelength ranges so as to prevent transmission to the grating coupler 220b), and so on. This enables each of the multiple grating couplers 220a to 220d to process a respective wavelength or wavelength range, allowing the bandwidth of the optical signal to be distributed across the multiple grating couplers 220a to 220d rather than being processed by a single grating coupler. This enables the semiconductor photonic device 200 to process multiple signals with higher bandwidths than a semiconductor photonic device including only a single grating coupler.

[0167] Figure 6B FIG. 6 is a top view of a portion of a semiconductor photonic device 600. Figure 6B As shown, the semiconductor photonic device 600 may include a plurality of microlenses 248 , wherein each microlens 248 is included over an antireflective coating 260 , over a plurality of color filter layers 602 a - 602 d , and over a plurality of grating couplers 220 a - 220 d .

[0168] Figure 6C An example of using multiple color filter layers 602 to divide the wavelength or wavelength range of the light signal 274 is shown. Figure 6CAs shown, the first wavelength (or first wavelength range) 274a can be allowed to pass through the color filter layer 602a, and the color filter layer 602a can be configured to filter or reflect other wavelengths or wavelength ranges of the light signal 274; the second wavelength (or second wavelength range) 274b can be allowed to pass through the color filter layer 602b, and the color filter layer 602b can be configured to filter or reflect other wavelengths or wavelength ranges of the light signal 274; the third wavelength (or third wavelength range) 274c can be allowed to pass through the color filter layer 602c, and the color filter layer 602c can be configured to filter or reflect other wavelengths or wavelength ranges of the light signal 274; the fourth wavelength (or fourth wavelength range) 274d can be allowed to pass through the color filter layer 602d, and the color filter layer 602d can be configured to filter or reflect other wavelengths or wavelength ranges of the light signal 274.

[0169] As mentioned above, providing Figures 6A to 6C As an example. Other examples can be found in the Figures 6A to 6C Described differently.

[0170] Figures 7A to 7E are multiple diagrams of an embodiment 700 for forming the second semiconductor die 204 described herein. Specifically, the example embodiment 700 includes an example of forming the second semiconductor die 204 for use in the semiconductor photonic device 600 described herein. In some embodiments, one or more semiconductor process operations described in connection with the example embodiment 700 may be performed using one or more of the plurality of semiconductor process tools 102 to 114 and / or through a wafer / die transfer tool 116. In some embodiments, one or more semiconductor process operations described in connection with the example embodiment 700 may be performed using another semiconductor process tool.

[0171] Please refer to Figure 7A , you can perform a combination of Figures 4A to 4E One or more semiconductor process operations are described to form a plurality of components 250 - 258 , 264 , and 266 over a semiconductor substrate 246 of a second semiconductor die 204 .

[0172] like Figure 7B As shown, antireflective coating 260 is formed over and / or on layer 252. Deposition tool 102 can be used to perform physical vapor deposition operations, atomic layer deposition operations, chemical vapor deposition operations, epitaxial operations, oxidation operations, combined Figure 1 Another type of deposition operation and / or another suitable deposition operation is described to deposit the antireflective coating 260 .

[0173] like Figure 7C and 7DAs shown, a plurality of color filter layers 602 may be formed above and / or on the anti-reflective coating 260. Figure 7C As shown, forming multiple color filter layers 602 may include forming a color filter material layer 702 on the anti-reflective coating 260 (e.g., using a deposition tool 102), forming a photoresist layer 704 on the color filter material layer 702 (e.g., using a deposition tool 102), forming a pattern in the photoresist layer 704 (e.g., using an exposure tool 104 and a development tool 106), and removing a portion of the color filter material layer 702 based on the pattern (e.g., using an etching tool 108) to form a color filter layer 602d. Forming color filter layer 602 may include forming a color filter material layer 706 on anti-reflective coating 260 and adjacent to color filter layer 602d and on color filter layer 602d (e.g., using deposition tool 102), forming a photoresist layer 708 on color filter material layer 706 (e.g., using deposition tool 102), forming a pattern in photoresist layer 708 (e.g., using exposure tool 104 and development tool 106), and removing portions of color filter layer 706 based on the pattern (e.g., using etching tool 108) to form color filter layer 602c. Similar operations may be performed to form color filter layers 602b and 602a.

[0174] like Figure 7E As shown, the combination can be performed Figures 4H to 4J One or more semiconductor process operations are described to form the plurality of components 262, 268, and 270 of the second semiconductor die 204. In some embodiments, the second semiconductor die 204 can be bonded to the first semiconductor die 202, and a bonding process can be performed. Figures 5A to 5F Similar semiconductor process operations are described to form semiconductor photonic device 600. In some embodiments, a combination of Figures 3A to 3H The semiconductor processing technology is described to form a first semiconductor die 202 .

[0175] As mentioned above, providing Figures 7A to 7E As an example. Other examples can be found in the Figures 7A to 7E Different than described.

[0176] Figures 8A to 8C are multiple diagrams of an example semiconductor photonic device 800 described herein. The semiconductor photonic device 800 may include a photonic integrated circuit, such as an optically coupled circuit. Generally speaking, the semiconductor photonic device 800 may be configured to convert between multiple electrical signals and multiple optical signals for high-bandwidth optical communications.

[0177] Figure 8A FIG. 8 is a cross-sectional view of a semiconductor photonic device 800. Figure 8AAs shown, semiconductor photonic device 800 can include a combination and arrangement of multiple layers and / or multiple structures similar to semiconductor photonic device 600 described herein. For example, semiconductor photonic device 800 can include multiple components 202 to 272 and 602. However, semiconductor photonic device 800 includes a single microlens 248 that is directly located above and / or positioned over a single color filter layer 602d and directly located above and / or over a single grating coupler 220d. In addition, semiconductor photonic device 800 includes a reflector layer 802 that is directly located above color filter layers 602a to 602c. In other words, microlens 248 can be included above color filter layer 802, rather than above the plurality of color filter layers 602a to 602c; however, reflector layer 802 can be included above the plurality of color filter layers 602a to 602c, rather than above color filter layer 602d. A first portion of the anti-reflective coating 260 may be included below the reflector layer 802, and a second portion of the anti-reflective coating 260 may extend laterally outward from the reflective layer 802 and above the color filter layer 602d.

[0178] Reflector layer 802 can include a highly reflective material, such as a metal. Examples include aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), ruthenium (Ru), and / or cobalt (Co). Reflector layer 802 can be included in a recess in layer 252 or in another layer above anti-reflective coating 260. Reflector layer 802 is configured to reflect a portion of the optical signal toward multiple color filter layers 602a to 602c. The optical signal portion corresponds to the portion of the optical signal reflected from color filter layer 602d. The various wavelength components of the optical signal are reflected from reflector layer 802 and multiple color filter layers 602a to 602c until they pass through color filter layer 602 configured to pass each specific wavelength component.

[0179] Figure 8B FIG. 8 is a top view of a portion of a semiconductor photonic device 800. Figure 8B As shown, a semiconductor photonic device 800 may include a plurality of microlenses 248, wherein each microlens 248 is included above a single color filter layer 602. The reflector layer 802 is omitted from the color filter layer 602 positioned above the microlens 248. This enables light signals to pass from the microlens 248 to the color filter layer 602 below the microlens 248. Otherwise, if the reflector layer 802 were included between the microlens 248 and the color filter layer 602 below the microlens 248, the reflector layer 802 would block the light signals from reaching the color filter layer 602 below the microlens 248.

[0180] Figure 8CAn example of using multiple color filter layers 602 and reflector layers 802 to separate multiple wavelengths or multiple wavelength ranges of the light signal 274 is shown. Figure 8C As shown, the optical signal 274 passes through the microlens 248 above the color filter layer 602d and enters the semiconductor photonic device 800. The fourth wavelength (or fourth wavelength range) 274d can be allowed to pass through the color filter layer 602d, and the color filter layer 602d can be configured to filter or reflect other wavelengths or wavelength ranges of the optical signal 274, and the reflected multiple wavelengths (or multiple wavelength ranges) propagate back through the anti-reflection coating 260 and are reflected from the reflector layer 802 toward the color filter layer 602c; the third wavelength (or third wavelength range) 274c can be allowed to pass through the color filter layer 602c, and the color filter layer 602c can be configured to filter or reflect other wavelengths or wavelength ranges of the optical signal 274, and the reflected multiple wavelengths (or multiple wavelength ranges) propagate back through the anti-reflection coating 260. The first wavelength (or first wavelength range) 274a may be allowed to pass through the color filter layer 602a, and the color filter layer 602a may be configured to filter or reflect other wavelengths or wavelength ranges of the light signal 274. The reflected multiple wavelengths (or multiple wavelength ranges) propagate back through the anti-reflective coating 260 and are reflected from the reflector layer 802 toward the color filter layer 602a. The first wavelength (or first wavelength range) 274a may be allowed to pass through the color filter layer 602a, and the color filter layer 602a may be configured to filter or reflect other wavelengths or wavelength ranges of the light signal 274.

[0181] As mentioned above, providing Figures 8A to 8C As an example. Other examples can be found in the Figures 8A to 8C Different than described.

[0182] Figures 9A to 9D 1 are multiple diagrams of an embodiment 900 for forming the second semiconductor die 204 described herein. Specifically, the example embodiment 900 includes an example of forming the second semiconductor die 204 for use in the semiconductor photonic device 800 described herein. In some embodiments, one or more semiconductor process operations described in conjunction with the example embodiment 900 can be performed using one or more of the plurality of semiconductor process tools 102 to 114 and / or through the wafer / die transfer tool 116. In some embodiments, one or more semiconductor process operations described in conjunction with the example embodiment 900 can be performed using another semiconductor process tool.

[0183] Please refer to Figure 9A , you can perform a combination of Figure 4A and 4BOne or more semiconductor process operations are described to form a plurality of components 250 - 258 over a semiconductor substrate 246 of a second semiconductor die 204 .

[0184] like Figure 9B As shown, a recess 902 can be formed in layer 252. In some embodiments, the pattern in the photoresist layer is used to etch layer 252 to form recess 902. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on layer 252. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch layer 252 based on the pattern to form recess 902 in layer 252. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove multiple remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to etching layer 252 based on the pattern.

[0185] like Figure 9C As shown, the reflector layer 802 can be formed in the recess 902 in the layer 252. The deposition tool 102 and / or the electroplating tool 112 can be used to combine chemical vapor deposition operations, physical vapor deposition operations, atomic layer deposition operations, electroplating operations, Figure 1 The reflector layer 802 is deposited in another deposition operation described herein and / or in another suitable deposition operation. In some embodiments, the seed layer is deposited first, and the reflector layer 802 is deposited on the seed layer. In some embodiments, the planarization tool 110 can be used to planarize the reflector layer 802 after the reflector layer 802 is deposited.

[0186] like Figure 9D As shown, the combination can be performed Figures 4C to 4J 7A to 7E to form the plurality of components 262 to 270 and / or 602 of the second semiconductor die 204. In some embodiments, the second semiconductor die 204 can be bonded to the first semiconductor die 202, and a bonding process can be performed. Figures 5A to 5F A plurality of similar semiconductor process operations are described to form the semiconductor photonic device 800. In some embodiments, a combination of Figures 3A to 3H The first semiconductor die 202 is formed using a plurality of semiconductor process technologies described.

[0187] As mentioned above, providing Figures 9A to 9D As an example. Other examples can be found in the Figures 9A to 9D Different than described.

[0188] Figures 10A to 10C are multiple diagrams of an example semiconductor photonic device 1000 described herein. The semiconductor photonic device 1000 may include a photonic integrated circuit, such as an optically coupled circuit. Generally speaking, the semiconductor photonic device 1000 may be configured to convert between multiple electrical signals and multiple optical signals for high-bandwidth optical communications.

[0189] Figure 10A FIG. 1 is a cross-sectional view of a semiconductor photonic device 1000. Figure 10A As shown, the semiconductor photonic device 1000 may include a combination and arrangement of multiple layers and / or multiple structures similar to the semiconductor photonic device 600 described herein. For example, the semiconductor photonic device 1000 may include multiple components 202 to 272. However, the semiconductor photonic device 1000 omits the multiple color filter layers 602. In addition, the semiconductor photonic device 1000 includes a single microlens 248 located in the oxide-filled region 262 and positioned directly above and / or above the grating structure 1002. In some embodiments, the grating structure 1002 may be included in another region of the second semiconductor die 204, such as in the semiconductor substrate 246. Alternatively, the grating structure 1002 may be included in the first semiconductor die 202 above the grating coupler 220d.

[0190] The grating structure 1002 is configured to separate an optical signal into different wavelength components. The grating structure 1002 may include a semiconductor structure, a dielectric structure and / or another type of structure including a plurality of gratings. The plurality of grating pitches of the grating structure 1002 may be included in the range of about 300 nanometers to about 1000 nanometers. However, other values within this range are also within the scope of the present invention. The grating structure 1002 may have a plurality of portions, each portion having a different grating pitch, so that the plurality of portions can each separate an optical signal of a different wavelength (or wavelength range). In some embodiments, the grating structure 1002 may be configured to operate within a range of about 1% duty cycle to about 99% duty cycle. However, other values within this range are also within the scope of the present invention.

[0191] Figure 10B 1 shows a top view of a portion of a semiconductor photonic device 1000. Figure 10B As shown, the semiconductor photonic device 1000 may include a plurality of microlenses 248 , wherein each microlens 248 is included above a single grating coupler 220 and above the grating structure 1002 .

[0192] Figure 10CAn example of using a grating structure 1002 to separate multiple wavelengths or multiple wavelength ranges of the optical signal 274 is shown. Figure 10C As shown, optical signal 274 enters semiconductor photonic device 1000 through microlens 248 above grating structure 1002. Grating structure 1002 separates optical signal 274 into a first wavelength (or first wavelength range) 274a, a second wavelength (or second wavelength range) 274b, a third wavelength (or third wavelength range) 274c, and a fourth wavelength (or fourth wavelength range) 274d. Grating structure 1002 directs first wavelength (or first wavelength range) 274a to grating coupler 220a. Grating structure 1002 directs second wavelength (or second wavelength range) 274b to grating coupler 220b. Grating structure 1002 directs third wavelength (or third wavelength range) 274c to grating coupler 220c. Grating structure 1002 directs fourth wavelength (or fourth wavelength range) 274d to grating coupler 220d.

[0193] As mentioned above, providing Figures 10A to 10C As an example, other examples may differ from those described with respect to Figures 10 to 10C.

[0194] Figures 11A to 11E 100 are diagrams illustrating an example embodiment 1100 for forming the second semiconductor die 204 described herein. Specifically, the example embodiment 1100 includes an example of forming the second semiconductor die 204 for use in the semiconductor photonic device 1000 described herein. In some embodiments, one or more semiconductor process operations described in connection with the example embodiment 1100 may be performed using one or more of the plurality of semiconductor process tools 102 to 114 and / or through a wafer / die transfer tool 116. In some embodiments, one or more semiconductor process operations described in connection with the example embodiment 1100 may be performed using another semiconductor process tool.

[0195] Please refer to Figure 11A , you can perform a combination of Figures 4A to 4E and / or one or more semiconductor process operations described in FIG. 7B to form a plurality of components 250 to 260 , 264 , and 266 over the semiconductor substrate 246 of the second semiconductor die 204 .

[0196] like Figure 11B As shown, a grating material layer 1102 may be formed above and / or on the anti-reflective coating 260. The deposition tool 102 may be used in physical vapor deposition operations, atomic layer deposition operations, chemical vapor deposition operations, epitaxial operations, oxidation operations, bonding operations, etc. Figure 1 The grating material layer 1102 may be deposited in another type of deposition operation as described and / or other suitable deposition operations.

[0197] like Figure 11C As shown, a plurality of gratings 1104 can be formed in the grating material layer 1102. In some embodiments, the pattern in the photoresist layer is used to etch the grating material layer 1102 to form the gratings 1104. In these embodiments, the deposition tool 102 can be used to form a photoresist layer on the grating material layer 1102. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch the grating material layer 1102 based on the pattern to form the plurality of gratings 1104 in the grating material layer 1102. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the plurality of remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of the grating material layer 1102 .

[0198] like Figure 11D As shown, additional portions of the grating material layer 1102 may be removed to form the grating structure 1002 above and / or on the anti-reflective coating 260. In some embodiments, the pattern in the photoresist layer is used to etch the grating material layer 1102 to form the grating structure 1002. In these embodiments, the deposition tool 102 may be used to form a photoresist layer on the grating material layer 1102. The exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 may be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 may be used to etch the grating material layer 1102 based on the pattern to form the grating structure 1002. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of the grating material layer 1102 .

[0199] like Figure 11E As shown, the combination can be performed Figures 4H-4J One or more semiconductor process operations are described to form the plurality of components 262 and 266 to 270 of the second semiconductor die 204. In some embodiments, the second semiconductor die 204 can be bonded to the first semiconductor die 202 and a bonding process can be performed. Figures 5A to 5FSimilar semiconductor process operations are described to form the semiconductor photonic device 1000. In some embodiments, a combination of Figures 3A to 3H The semiconductor processing technology is described to form a first semiconductor die 202 .

[0200] As mentioned above, providing Figures 11A to 11E As an example. Other examples can be found in the Figures 11A to 11E Different than described.

[0201] Figure 12 1 is a diagram of example components of the apparatus 1200 described herein. In some embodiments, one or more of the plurality of semiconductor process tools 102 to 114 and / or the chip / chip transport 116 may include one or more of the plurality of apparatuses 1200 and / or one or more components of the apparatus 1200. Figure 12 As shown, the apparatus 1200 may include a bus 1210 , a processor 1220 , a memory 1230 , an input component 1240 , an output component 1250 and / or a communication component 1260 .

[0202] The bus 1210 may include one or more components that enable wired and / or wireless communication between the various components of the device 1200. ... Figure 12 Two or more components of a computer system are coupled together, for example, via operational coupling, communication coupling, electronic coupling and / or electrical coupling. For example, bus 1210 may include electrical connections (e.g., wires, traces and / or leads) and / or wireless buses. Processor 1220 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application-specific integrated circuit and / or another type of processing component. Processor 1220 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1220 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

[0203] Memory 1230 may include volatile and / or non-volatile memory. For example, memory 1230 may include random access memory (RAM), read-only memory (ROM), a hard disk drive, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 1230 may include internal memory (e.g., RAM, ROM, or hard disk) and / or removable memory (e.g., removable via a universal serial bus connection). Memory 1230 may be a non-transitory computer-readable medium. Memory 1230 may store information related to the operation of device 1200, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, memory 1230 may include, for example, one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 1220) via bus 1210. The communicative coupling between the processor 1220 and the memory 1230 may enable the processor 1220 to read and / or process information stored in the memory 1230 and / or store information in the memory 1230 .

[0204] The input component 1240 can enable the device 1200 to receive input, such as user input and / or sensed input. For example, the input component 1240 can include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, a global navigation satellite system sensor, an accelerometer, a gyroscope, and / or an actuator. The output component 1250 can enable the device 1200 to provide output, such as via a display, a speaker, and / or an LED. The communication component 1260 can enable the device 1200 to communicate with other devices via a wired connection and / or a wireless connection. For example, the communication component 1260 can include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0205] The device 1200 can perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 1230) can store a set of instructions (e.g., one or more instructions or program codes) for execution by the processor 1220. The processor 1220 can execute a set of instructions to perform one or more operations or processes described herein. In some embodiments, execution of the group of instructions by one or more processors 1220 causes the one or more processors 1220 and / or the device 1200 to perform one or more operations or processes described herein. In some embodiments, hard-wired circuits can be used instead of instructions or in combination with instructions to perform one or more operations or processes described herein. Additionally or alternatively, the processor 1220 can be configured to perform one or more operations or processes described herein. Therefore, the implementations described herein are not limited to any particular combination of hardware circuitry and software.

[0206] Figure 12 The number and arrangement of the various components shown are provided as examples. The apparatus 1200 may include Figure 12 Additional components, fewer components, different components, or differently arranged components than those shown. Additionally or alternatively, one set of components (e.g., one or more components) of device 1200 may perform one or more functions described as being performed by another set of components of device 1200.

[0207] Figure 13 is a flow chart of an example process 1300 associated with forming the semiconductor photonic device 1000 described herein. In some embodiments, one or more semiconductor process tools (eg, one or more of the semiconductor process tools 102 to 114) are used to perform Figure 13 Additionally or alternatively, Figure 13 One or more processing blocks of may be performed using one or more components of the apparatus 1200 , such as the processor 1220 , the memory 1230 , the input component 1240 , the output component 1250 , and / or the communication component 1260 .

[0208] like Figure 13 As shown, process 1300 may include forming an optical transceiver, an optical waveguide coupled to the optical transceiver, and a plurality of grating couplers coupled to the optical waveguide in a first semiconductor die (block 1310). For example, one or more of semiconductor process tools 102 to 114 may be used to form optical transceiver 216, optical waveguide 218 coupled to optical transceiver 216, and a plurality of grating couplers 220 (e.g., one or more of the plurality of grating couplers 220a to 220d) coupled to the optical waveguide 218 in a first semiconductor die 202, as described herein.

[0209] like Figure 13 As further shown, the process 1300 may include forming one or more anti-reflective coatings in the second semiconductor die (block 1320). For example, one or more of the plurality of semiconductor process tools 102 to 114 may be used to form one or more anti-reflective coatings 260 (e.g., one or more of the plurality of anti-reflective coatings 260a to 260d) in the second semiconductor die 204, as described herein.

[0210] like Figure 13 As further shown, process 1300 may include bonding a first semiconductor die and a second semiconductor die to form a semiconductor photonic device (block 1330). For example, one or more of the plurality of semiconductor process tools 102 to 114 may be used to bond the first semiconductor die 202 and the second semiconductor die 204 to form the semiconductor photonic device 200, as described herein. In some embodiments, after bonding the first semiconductor die 202 and the second semiconductor die 204, one or more anti-reflective coatings 260 are disposed on at least a subset of the plurality of grating couplers 220.

[0211] like Figure 13 As further shown, process 1300 may include forming one or more microlenses over the one or more anti-reflective coatings after bonding the first semiconductor die (block 1340). For example, one or more of the plurality of semiconductor process tools 102 to 114 may be used to form one or more microlenses 248 (e.g., one or more of the plurality of microlenses 248a to 248d) over the one or more anti-reflective coatings 260 after bonding the first semiconductor die 202 and the second semiconductor die 204, as described herein.

[0212] Process 1300 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in combination with one or more other processes described elsewhere herein.

[0213] In a first embodiment, the process 1300 includes forming a grating structure 1002 over one or more anti-reflective coatings 260 in the second semiconductor die 204 before bonding the first semiconductor die 202 and the second semiconductor die 204 .

[0214] In a second embodiment, either alone or in combination with the first embodiment, forming the one or more microlenses 248 includes forming the one or more microlenses 248 above the grating structure 1002 .

[0215] In a third embodiment, either alone or in combination with one or more of the first and second embodiments, the grating structure 1002 is positioned over one of the plurality of grating couplers 220 after the first semiconductor die 202 and the second semiconductor die 204 are bonded.

[0216] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, process 1300 includes forming a reflector layer 802 in the second semiconductor die 204 before bonding the first semiconductor die 202 and the second semiconductor die 204, wherein one or more anti-reflective coatings 260 are formed, including forming one or more anti-reflective coatings 260 over the reflector layer 802.

[0217] In a fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, a first portion of the one or more anti-reflective coatings 260 is positioned on the reflective layer 802 , and a second portion of the one or more anti-reflective coatings extends laterally outward from the reflective layer 802 .

[0218] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, process 1300 includes forming a plurality of color filter layers 602 (e.g., a plurality of color filter layers 602 a to 602 d ) in the second semiconductor die 204 above the one or more anti-reflective coating layers 260 before bonding the first semiconductor die 202 and the second semiconductor die 204.

[0219] although Figure 13 An example block diagram of process 1300 is shown, but in some embodiments, process 1300 includes Figure 13 1300. In addition or alternatively, two or more blocks of process 1300 can be executed in parallel.

[0220] In this manner, a semiconductor photonic device includes a plurality of grating couplers, each grating coupler being configured to couple a specific wavelength (or wavelength range) of an optical signal to an optical waveguide of the semiconductor photonic device. In some embodiments, various embodiments of the plurality of optical signal splitters or plurality of filters described herein enable a respective wavelength (or respective wavelength range) to be passed to each grating coupler (while filtering out other wavelengths or other wavelength ranges), thereby enabling the grating couplers to process the respective wavelength (or respective wavelength range). This enables multiple wavelengths (or multiple wavelength ranges) to be distributed across the plurality of grating couplers, which can increase the bandwidth of the semiconductor photonic device relative to a semiconductor photonic device that includes only a single grating coupler.

[0221] As detailed above, some embodiments described herein provide a semiconductor photonic device. The semiconductor photonic device includes an optical transceiver. The semiconductor photonic device includes an optical waveguide coupled to the optical transceiver. The semiconductor photonic device includes a plurality of grating couplers coupled to the optical waveguide. The semiconductor photonic device includes a plurality of anti-reflection coatings, wherein each of the plurality of anti-reflection coatings is located above a respective one of the plurality of grating couplers. The semiconductor photonic device includes a plurality of microlenses, wherein each of the plurality of microlenses is located above a respective one of the plurality of anti-reflection coatings.

[0222] As detailed above, some embodiments described herein provide a semiconductor photonic device. The semiconductor photonic device includes an optical transceiver. The semiconductor photonic device includes an optical waveguide coupled to the optical transceiver. The semiconductor photonic device includes a plurality of grating couplers coupled to the optical waveguide. The semiconductor photonic device includes a plurality of color filter layers, wherein each of the plurality of color filter layers is above a respective one of the plurality of grating couplers. The semiconductor photonic device includes an antireflection coating above the plurality of color filter layers. The semiconductor photonic device includes a microlens above one or more of the plurality of color filter layers.

[0223] As detailed above, some embodiments described herein provide a method. The method includes forming an optical transceiver, an optical waveguide coupled to the optical transceiver, and a plurality of grating couplers coupled to the optical waveguide in a first semiconductor die. The method includes forming one or more anti-reflective coatings in a second semiconductor die. The method includes bonding the first semiconductor die to the second semiconductor die to form a semiconductor photonic device, wherein after bonding the first semiconductor die to the second semiconductor die, the one or more anti-reflective coatings are located above at least a subset of the plurality of grating couplers. The method includes forming one or more microlenses above the one or more anti-reflective coatings after bonding the first semiconductor die to the second semiconductor die.

[0224] As used herein, “satisfying a threshold” may mean greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, etc., depending on the context.

[0225] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor photonic device, characterized in that: include: Optical transceivers; an optical waveguide coupled to the optical transceiver; a plurality of grating couplers coupled to the optical waveguide; Multiple anti-reflective coatings, wherein each of the plurality of antireflective coatings is over a respective one of the plurality of grating couplers; as well as Multiple microlenses, wherein each of the plurality of microlenses is over a respective one of the plurality of anti-reflective coatings.

2. The semiconductor photonic device according to claim 1, wherein wherein the optical transceiver, the optical waveguide, and the plurality of grating couplers are included in a first semiconductor die of the semiconductor photonic device; and The plurality of anti-reflective coatings and the plurality of microlenses are included in a second semiconductor die of the semiconductor photonic device, which is bonded to the first semiconductor die at a bonding interface.

3. The semiconductor photonic device according to claim 1, wherein wherein a first microlens of the plurality of microlenses has a first curvature; wherein a second microlens of the plurality of microlenses has a second curvature; and The first bend and the second bend are different bends.

4. The semiconductor photonic device according to claim 1, wherein wherein a first antireflective coating of the plurality of antireflective coatings is configured to allow transmission of a first wavelength range of incident light; wherein a second antireflective coating of the plurality of antireflective coatings is configured to allow transmission of a second wavelength range of incident light; The first wavelength range and the second wavelength range are different wavelength ranges.

5. The semiconductor photonic device according to claim 4, wherein: The first anti-reflective coating comprises: a first multilayer having a first refractive index; and a second multilayer having a second refractive index different from the first refractive index, The first multilayer and the second multilayer are alternated in a direction substantially perpendicular to an extending direction of the first anti-reflective coating.

6. A semiconductor photonic device, characterized in that include: Optical transceivers; an optical waveguide coupled to the optical transceiver; a plurality of grating couplers coupled to the optical waveguide; Multiple color filter layers, wherein each of the plurality of color filter layers is above a respective one of the plurality of grating couplers; an anti-reflective coating over the plurality of color filter layers; as well as A microlens is formed above one or more of the plurality of color filter layers.

7. The semiconductor photonic device according to claim 6, wherein: wherein the optical transceiver, the optical waveguide, and the plurality of grating couplers are included in a first semiconductor die of the semiconductor photonic device; and The plurality of color filter layers, the anti-reflection coating, and the microlens are included in a second semiconductor die of the semiconductor photonic device, which is bonded to the first semiconductor die at a bonding interface.

8. The semiconductor photonic device according to claim 6, wherein: The microlens spans across the multiple color filter layers.

9. The semiconductor photonic device according to claim 6, wherein: wherein the microlens is included only above a first color filter layer of the plurality of color filter layers, and The semiconductor photonic device further includes a reflective layer located above a second color filter layer of the plurality of color filter layers but not above the first color filter layer.

10. The semiconductor photonic device according to claim 9, wherein The anti-reflection coating is between the reflective layer and the second color filter layer.

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