Bidirectional IO circuit and chip

Abstract

The utility model provides a bidirectional IO circuit and a chip, in a slope control circuit of the circuit, a PMOS driving module comprises a plurality of first driving resistors and a plurality of first switch units, an NMOS driving module comprises a plurality of second driving resistors and a plurality of second switch units, and the slope of the slope control circuit is controlled by turning on the first switch units and the second switch units. The combined path resistance of the plurality of first driving resistors and the plurality of second driving resistors in the PMOS driving module and the NMOS driving module is small, the change slope of current output by the PMOS driving module and the NMOS module can be reduced, the influence of ground bounce noise in the circuit is effectively reduced, and then the reliability and the yield of a chip are improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of integrated circuits, and in particular relates to a bidirectional IO circuit. Background Art

[0002] As the application scenarios of integrated circuits become more and more extensive and the scale of chips becomes larger and larger, when a large number of output ports in the chip are flipped at the same time, a large transient current will be generated. The metal parasitic inductance between the circuit ground inside the chip and the chip pin ground will produce large voltage fluctuations, forming ground bounce noise. Excessive ground bounce noise may cause errors in the internal logic circuit of the chip, resulting in poor chip reliability and low chip yield during production. Utility Model Content

[0003] The technical purpose of the utility model is to provide a bidirectional IO circuit, aiming to solve the problem of excessive ground bounce noise inside the chip.

[0004] To solve the above technical problems, the present invention is implemented as follows: a bidirectional IO circuit, comprising:

[0005] Power port, enable port, input port, ground port, first input drive circuit, slope control circuit, second input and output drive circuit, bidirectional input and output port and output port;

[0006] The input end of the first input drive circuit is electrically connected to the output end of the enable port, the output end of the input port, and the power port; the output end of the first input drive circuit is electrically connected to the input end of the slope control circuit and the ground port;

[0007] The input end of the slope control circuit is electrically connected to the output end of the first input drive circuit, and the output end of the slope control circuit is electrically connected to the input end of the second input-output drive circuit;

[0008] The slope control circuit includes a PMOS driving module and an NMOS driving module;

[0009] The PMOS driver module includes a first PMOS transistor, a first NMOS transistor, and a first logic control unit. The gate of the first PMOS transistor and the gate of the first NMOS transistor are electrically connected to the first output terminal of the first input driver circuit. The N-well and source of the first PMOS transistor are electrically connected to the power port. The substrate and source of the first NMOS transistor are electrically connected to the ground port. A plurality of first driving resistors are connected in series between the drain of the first PMOS transistor and the drain of the first NMOS transistor. The drain of the first PMOS transistor is also electrically connected to the first input terminal of the second input-output driver circuit.

[0010] The first logic control unit includes a plurality of first switch units, any two adjacent first drive resistors are electrically connected to a first end of a first switch unit, and the second end of each first switch unit is electrically connected to the drain of the first NMOS transistor;

[0011] The NMOS driver module includes a second PMOS transistor, a second NMOS transistor, and a second logic control unit. The gate of the second PMOS transistor and the gate of the second NMOS transistor are electrically connected to the second output terminal of the first input driver circuit. The N well and source of the second PMOS transistor are electrically connected to the power port. The substrate and source of the second NMOS transistor are electrically connected to the ground port. A second driving resistor is also connected in series between the drain of the second PMOS transistor and the drain of the second NMOS transistor. The drain of the second NMOS transistor is also electrically connected to the second input terminal of the second input-output driver circuit.

[0012] The second logic control unit includes a plurality of second switch units, any two adjacent second drive resistors are electrically connected to the first end of a second switch unit, and the second end of each second switch unit is electrically connected to the drain of the second PMOS transistor;

[0013] The second input / output driving circuit is also electrically connected to the bidirectional input / output port and the output port.

[0014] Furthermore, N-1 groups of first driving resistors are sequentially connected in series between the drains of the first PMOS transistor and the first NMOS transistor, where N is a positive integer and is greater than or equal to 2;

[0015] The first switch unit is an NMOS transistor, and the first logic control unit includes N groups of the NMOS transistors;

[0016] The gates of the N groups of NMOS transistors are all used to be electrically connected to the first signal output terminal of the decoder module, the drains of the N groups of NMOS transistors are all electrically connected to the drain of the first NMOS transistor, and the substrates of the N groups of NMOS transistors are all electrically connected to the ground port;

[0017] The source of the NMOS transistor of the first group is electrically connected between the first end of the first driving resistor of the first group and the drain of the first NMOS transistor, and the source of the NMOS transistor of the second group to the Nth group is electrically connected to the second end of the first driving resistor of the first group to the N-1th group in sequence.

[0018] Furthermore, N groups of second driving resistors are sequentially connected in series between the drains of the second PMOS transistor and the second NMOS transistor, where N is a positive integer and is greater than or equal to 2;

[0019] The second switch unit is a PMOS tube, and the second logic control unit includes N groups of the PMOS tubes;

[0020] The gates of the N groups of PMOS transistors are all used to electrically connect to the second signal output terminal of the decoder module, and the signal output by the second signal output terminal is opposite to the signal output by the first signal output terminal;

[0021] The N wells of the N groups of PMOS transistors are all electrically connected to the power port, and the sources of the N groups of PMOS transistors are all electrically connected to the drain of the second PMOS transistor;

[0022] The drains of the first to Nth groups of PMOS transistors are electrically connected to the first ends of the first to Nth groups of the second driving resistors, respectively.

[0023] Furthermore, N is greater than or equal to 4.

[0024] Furthermore, the first input drive circuit includes an input / output control circuit and a level conversion circuit, and the power supply port includes a low-voltage power supply port and a high-voltage power supply port;

[0025] The input end of the input-output control circuit is electrically connected to the enable port, the input port and the low-voltage power supply port;

[0026] The output end of the input-output control circuit is electrically connected to the input end of the level conversion circuit and the ground port;

[0027] The input-output control circuit is used to output the low-voltage domain input signal to the level conversion circuit;

[0028] The input end of the level conversion circuit is also electrically connected to the output end of the high-voltage power supply port, and the output end of the level conversion circuit is electrically connected to the input end of the slope control circuit and the ground port. The level conversion circuit is used to convert the low-voltage domain input signal into a high-voltage domain input signal, and input the high-voltage domain input signal into the slope control circuit.

[0029] Furthermore, the input and output circuit includes a NOT gate circuit, a NAND gate circuit and a NOR gate circuit;

[0030] The input end of the NOT gate circuit is electrically connected to the enable port and the low-voltage power supply port, and the output end of the NOT gate circuit is electrically connected to the ground port;

[0031] The input end of the NAND gate circuit is electrically connected to the input port and the low-voltage power supply port, the output end of the NAND gate circuit is electrically connected to the input end of the NOT gate circuit and the input end of the level conversion circuit, and the output end of the NOT gate circuit is electrically connected to the ground port;

[0032] The input end of the NOR gate circuit is electrically connected to the input port, the enable port and the low-voltage power supply port, the output end of the NOR gate circuit is electrically connected to the level conversion circuit, and the output end of the NOR gate circuit is also electrically connected to the ground port.

[0033] Furthermore, the level conversion circuit includes a first level conversion circuit and a second level conversion circuit;

[0034] The input end of the first level conversion circuit is electrically connected to the output end of the NAND gate circuit;

[0035] The output end of the first level conversion circuit is electrically connected to the input end of the PMOS driving module;

[0036] The input end of the second level conversion circuit is electrically connected to the output end of the NOR gate circuit;

[0037] The output end of the second level conversion circuit is electrically connected to the input end of the NMOS driving module.

[0038] Furthermore, the second input-output driving circuit includes a driving and ESD protection circuit and a second input driving circuit;

[0039] The input end of the driving and ESD protection circuit is electrically connected to the output end of the PMOS driving module and the output end of the NMOS driving module;

[0040] The output end of the driving and ESD protection circuit is electrically connected to the ground port;

[0041] The input end of the second input drive circuit is electrically connected to the output end of the drive and ESD protection circuit and the power port; the output end of the second input drive circuit is electrically connected to the output port and the ground port;

[0042] The driving and ESD protection circuit and the second input driving circuit are also electrically connected to the bidirectional input and output port.

[0043] Furthermore, the power port includes a high-voltage power port and a low-voltage power port; the driving and ESD protection circuit includes a first driving PMOS transistor, a first driving NMOS transistor, a first switching logic circuit and a second switching logic circuit;

[0044] The source of the first driving PMOS transistor is electrically connected to the high-voltage power supply port, the gate of the first driving PMOS transistor is electrically connected to the output end of the PMOS driving module, and the drain of the first driving PMOS transistor is electrically connected to the bidirectional input and output port;

[0045] The source of the first driving NMOS transistor is electrically connected to the ground port, the gate of the first driving NMOS transistor is electrically connected to the output end of the NMOS driving module, and the drain of the first driving NMOS transistor is electrically connected to the bidirectional input and output port;

[0046] A first end of the first switch logic circuit is connected to the high-voltage power supply port, a second end of the first switch logic circuit is electrically connected to the ground port, and a third end of the first switch logic circuit is electrically connected to the bidirectional input and output port;

[0047] The first end of the second switch logic circuit is connected to the high-voltage power supply port, the second end of the second switch logic circuit is electrically connected to the ground port, and the third end of the second switch logic circuit is electrically connected to the bidirectional input and output port.

[0048] Furthermore, the second input drive circuit includes a high voltage circuit and a low voltage circuit;

[0049] The input end of the high-voltage circuit is electrically connected to the bidirectional input and output port and the high-voltage power supply port, and the output end of the high-voltage circuit is electrically connected to the input end of the low-voltage circuit;

[0050] The low-voltage circuit includes a multi-stage inverter, the input end of the multi-stage inverter is electrically connected to the output end of the high-voltage circuit and the low-voltage power supply port, and the output end of the multi-stage inverter is electrically connected to the output port and the ground port.

[0051] The utility model also provides a chip, comprising the bidirectional IO circuit described above.

[0052] Compared with the prior art, the bidirectional IO circuit and chip in the present invention have the following beneficial effects:

[0053] In the slope control circuit, the PMOS driver module includes multiple first driver resistors and multiple first switch units, and the NMOS driver module includes multiple second driver resistors and multiple second switch units. By turning on the first switch unit and the second switch unit, the combined path resistance of the multiple first driver resistors and the second driver resistors in the PMOS driver module and the NMOS driver module is smaller, which can reduce the current change slope output by the PMOS driver module and the NMOS module, effectively reduce the influence of ground bounce noise in the circuit, and thereby improve the chip yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 It is a circuit block diagram of a bidirectional IO circuit in an embodiment of the present utility model;

[0055] Figure 2This is a circuit diagram of an input and output control circuit in an embodiment of the present utility model;

[0056] Figure 3 1 is a circuit diagram of a level conversion circuit in an embodiment of the present utility model;

[0057] Figure 4 1 is a circuit diagram of a slope control circuit in an embodiment of the present utility model;

[0058] Figure 5 1 is a circuit diagram of a driving and ESD protection circuit in an embodiment of the present invention;

[0059] Figure 6 1 is a circuit diagram of the second input drive circuit in an embodiment of the present utility model;

[0060] Figure 7 This is a waveform diagram of the minimum output delay of the circuit in the embodiment of the present utility model;

[0061] Figure 8 1 is a waveform diagram of the maximum output delay of the circuit in the embodiment of the present utility model.

[0062] In the accompanying drawings, each reference numeral represents:

[0063] 10. First input drive circuit; 11. Input / output control circuit; 12. Level conversion circuit; 121. First level conversion circuit; 122. Second level conversion circuit;

[0064] 20. Slope control circuit; 21. PMOS driver module; 22. NMOS driver module;

[0065] 30. Second input / output drive circuit; 31. Drive and ESD protection circuit; 32. Second input drive circuit; 321. High-voltage circuit; 322. Low-voltage circuit. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention.

[0067] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of this utility model, "plurality" means two or more, unless otherwise specifically defined.

[0068] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0069] Example

[0070] See also Figures 1 to 8 In this embodiment, a bidirectional IO circuit includes:

[0071] Power port, enable port, input port, ground port, first input drive circuit 10, slope control circuit 20, second input / output drive circuit 30, bidirectional input / output port and output port;

[0072] The input end of the first input driving circuit 10 is electrically connected to the output end of the enable port, the output end of the input port, and the power port; the output end of the first input driving circuit 10 is electrically connected to the input end of the slope control circuit 20 and the ground port;

[0073] The input end of the slope control circuit 20 is electrically connected to the output end of the first input driving circuit 10 , and the output end of the slope control circuit 20 is electrically connected to the input end of the second input-output driving circuit 30 ;

[0074] The slope control circuit 20 includes a PMOS driving module 21 and an NMOS driving module 22;

[0075] The PMOS driver module 21 includes a first PMOS transistor, a first NMOS transistor, and a first logic control unit. The gate of the first PMOS transistor and the gate of the first NMOS transistor are electrically connected to the first output terminal of the first input driver circuit 10. The N-well and source of the first PMOS transistor are electrically connected to the power port. The substrate and source of the first NMOS transistor are electrically connected to the ground port. A plurality of first driving resistors are connected in series between the drain of the first PMOS transistor and the drain of the first NMOS transistor. The drain of the first PMOS transistor is also electrically connected to the first input terminal of the second input / output driver circuit 30.

[0076] The first logic control unit includes a plurality of first switch units, any two adjacent first drive resistors are electrically connected to the first end of a first switch unit, and the second end of each first switch unit is electrically connected to the drain of the first NMOS transistor;

[0077] The NMOS driver module 22 includes a second PMOS transistor, a second NMOS transistor, and a second logic control unit. The gate of the second PMOS transistor and the gate of the second NMOS transistor are electrically connected to the second output terminal of the first input driver circuit 10. The N-well and source of the second PMOS transistor are electrically connected to the power port. The substrate and source of the second NMOS transistor are electrically connected to the ground port. A second driving resistor is also connected in series between the drain of the second PMOS transistor and the drain of the second NMOS transistor. The drain of the second NMOS transistor is also electrically connected to the second input terminal of the second input-output driver circuit 30.

[0078] The second logic control unit includes a plurality of second switch units, any two adjacent second driving resistors are electrically connected to the first end of a second switch unit, and the second end of each second switch unit is electrically connected to the drain of the second PMOS transistor;

[0079] The second input / output driving circuit 30 is also electrically connected to the bidirectional input / output port and the output port.

[0080] As an embodiment of the present invention, a bidirectional IO circuit includes: a power port, an enable port OEN, an input port I, a first input drive circuit 10, a slope control circuit 20, a second input / output drive circuit 30, an output port C and a bidirectional input / output port PAD.

[0081] The power supply port includes a high voltage power supply port VDD50 and a low voltage power supply port VDD.

[0082] Among them, the high-voltage power port VDD50 is a 5V high-voltage power domain, the low-voltage power port VDD is a 1.8V low-voltage power domain, and the ground ports include VSSD and VSS. VSSD is the ground port of the main ESD discharge path, and VSS is the low-voltage 1.8V digital control logic circuit ground port.

[0083] The first input driving circuit 10 determines IO input or output through the logic signal input from the enable port OEN. When the enable port OEN=1, the bidirectional input / output port PAD acts as an input port; when the enable port OEN=0, the bidirectional input / output port PAD acts as an output port.

[0084] In the slope control circuit 20, the PMOS driving module 21 includes multiple first driving resistors and multiple first switch units, and the NMOS driving module 22 includes multiple second driving resistors and multiple second switch units. By turning on the first switch unit and the second switch unit, the combined path resistance of the multiple first driving resistors and the second driving resistors in the PMOS driving module 21 and the NMOS driving module 22 is smaller, which can reduce the current change slope output by the PMOS driving module 21 and the NMOS module, effectively reduce the influence of ground bounce noise in the circuit, and thereby improve the chip yield.

[0085] In addition, if the impact of the ground bounce noise on the input port is small, by closing at least part of the first switch unit and the second switch unit, the combined path resistance of the multiple first drive resistors and the second drive resistors in the PMOS driver module 21 and the NMOS driver module 22 is made larger, which can increase the current change slope of the output of the PMOS driver module 21 and the NMOS module, speed up the operating speed of the circuit, and achieve a compromise between the circuit operating speed and the ground bounce noise.

[0086] like Figure 3 As shown, further, N-1 groups of first driving resistors are connected in series between the drains of the first PMOS transistor and the first NMOS transistor, where N is a positive integer and is greater than or equal to 2;

[0087] The first switch unit is an NMOS transistor, and the first logic control unit includes N groups of the NMOS transistors;

[0088] The gates of the N groups of NMOS transistors are all electrically connected to the first signal output terminal of the decoder module, the drains of the N groups of NMOS transistors are all electrically connected to the drain of the first NMOS transistor, and the substrates of the N groups of NMOS transistors are all electrically connected to the ground port;

[0089] The source of the first group of NMOS transistors is electrically connected between the first end of the first group of first driving resistors and the drain of the first NMOS transistor, and the source of the second to Nth groups of NMOS transistors is electrically connected to the second ends of the first to N-1th groups of first driving resistors in sequence.

[0090] like Figure 3 As shown, further, N groups of second driving resistors are sequentially connected in series between the drains of the second PMOS transistor and the second NMOS transistor, where N is a positive integer and is greater than or equal to 2;

[0091] The second switch unit is a PMOS tube, and the second logic control unit includes N groups of the PMOS tubes;

[0092] The gates of the N groups of PMOS transistors are all used to electrically connect to the second signal output terminal of the decoder module, and the signal output by the second signal output terminal is opposite to the signal output by the first signal output terminal;

[0093] The N wells of the N groups of PMOS tubes are all electrically connected to the power port, and the sources of the N groups of PMOS tubes are all electrically connected to the drain of the second PMOS tube;

[0094] The drains of the first to N-th groups of PMOS transistors are electrically connected to the first ends of the first to N-th groups of second driving resistors respectively.

[0095] Furthermore, N is greater than or equal to 4.

[0096] Specifically, in this embodiment, N=4. The decoder module can decode the two-bit control signal to 4 bits and output the trimming signal A. <0> 、A <1> 、A <2> 、A <3> 、A_N <0> 、A_N <1> 、A_N <2> 、A_N <3> Among them, A <0> with A_N <0> 、A <1> with A_N <1> 、A <2> with A_N <2> 、A <3> with A_N <3> Opposite signals.

[0097] like Figure 3 As shown, the PMOS driving module 21 includes a first PMOS transistor PM15, a first NMOS transistor NM15, resistors R2, R3, R4 and a first logic unit. The first logic unit includes NMOS transistors NM17, NM18, NM19 and NM20.

[0098] The N-well and source of PM15 are electrically connected to the high-voltage power supply port VDD50, the gate of PM15 is electrically connected to net684, and the drain of PM15 is electrically connected to the first signal detection terminal B; the substrate and source of NM15 are electrically connected to the ground port VSS, the gate of NM15 is electrically connected to net684, and the drain of NM15 is electrically connected to the second signal detection terminal B_P.

[0099] The substrates of NM17, NM18, NM19 and NM20 are electrically connected to the ground port VSS, the drains of NM17, NM18, NM19 and NM20 are electrically connected to the second signal detection terminal B_P, wherein the gates of NM17, NM18, NM19 and NM20 are electrically connected to A <3> 、A <2> 、A <1> and A <0> The sources of NM17, NM18, NM19 and NM20 are electrically connected to net678, net674, net675 and the first signal detection terminal B respectively.

[0100] The two ends of the resistor R2 are electrically connected to the first signal detection point B and net 675 respectively, the two ends of the resistor R3 are electrically connected to net 675 and net 674 respectively, and the two ends of the resistor R4 are electrically connected to net 674 and net 678 respectively.

[0101] The working principle of the PMOS driver module 21 is:

[0102] When the enable port OEN=1, the first PMOS transistor PM15 and the first NMOS transistor NM15 are both turned off, and the bidirectional input-output port PAD serves as the input port, and C=PAD; when the enable port OEN=0, the first PMOS transistor PM15 and the first NMOS transistor NM15 are turned on, and the bidirectional input-output port PAD serves as the output port, and PAD=I.

[0103] When the input signal I=1, the NM15 transistor is turned on, and the signal B at the first signal detection point reaches the second signal detection point B_P through the path selected by the control signal, and then discharges to VSS through the NM15 transistor. By selecting the combined path resistance controlled by the trim signal, the waveform delay time of the signal B can be adjusted, thereby adjusting the output waveform.

[0104] like Figure 3 As shown, the NMOS driving module 22 includes a second PMOS transistor PM16, a second NMOS transistor NM16, resistors R5, R6, R7, R8 and a second logic unit. The second logic unit includes PMOS transistors PM17, PM18, PM19 and PM20.

[0105] The N-well and source of PM16 are electrically connected to the high-voltage power supply port VDD50, the gate of PM16 is electrically connected to net30, and the drain of PM15 is electrically connected to the fourth signal detection terminal D_P; the substrate and source of NM16 are electrically connected to the ground port VSS, the gate of NM16 is electrically connected to net30, and the drain of NM16 is electrically connected to the third signal detection terminal D.

[0106] The N-wells of PM17, PM18, PM19 and PM20 are electrically connected to the high-voltage power supply port VDD50, and the sources of PM17, PM18, PM19 and PM20 are electrically connected to the fourth signal detection terminal D_P. The gates of PM17, PM18, PM19 and PM20 are electrically connected to A_N <3> 、A_N <2> 、A_N <1> and A_N <0> The drains of PM17, PM18, PM19 and NM20 are electrically connected to net681, net666, net665 and net664 respectively.

[0107] The two ends of resistor R5 are electrically connected to net681 and net666 respectively, the two ends of resistor R6 are electrically connected to net666 and net665 respectively, the two ends of resistor R7 are electrically connected to net665 and net664 respectively, and the two ends of resistor R8 are electrically connected to net664 and the third signal detection point D respectively.

[0108] The working principle of the NMOS driver module 22 is:

[0109] When the enable port OEN=1, the second PMOS transistor PM16 and the second NMOS transistor NM16 are both turned off, and the bidirectional input-output port PAD serves as the input port, and C=PAD; when the enable port OEN=0, the second PMOS transistor PM16 and the second NMOS transistor NM16 are both turned on, and the bidirectional input-output port PAD serves as the output port, and PAD=I.

[0110] When input signal I = 0, PM16 turns on, and current flows through PM16 to the fourth signal detection point D_P, and then through the path selected by the control signal to the third signal detection point D. By selecting the resistance of the combined path controlled by the trim signal, the waveform delay of signal D can be adjusted, thereby adjusting the output waveform.

[0111] Therefore, the bidirectional IO circuit can switch between multiple working modes and select the appropriate output slope according to the circuit working status, effectively solving the contradiction between working speed and ground bounce noise, achieving a compromise between speed and ground bounce noise, and effectively improving the product yield.

[0112] like Figure 2 and 3 As shown, further, the first input drive circuit 10 includes an input-output control circuit 11 and a level conversion circuit 12, and the power supply port includes a low-voltage power supply port and a high-voltage power supply port;

[0113] The input end of the input / output control circuit 11 is electrically connected to the enable port, the input port and the low-voltage power supply port;

[0114] The output end of the input / output control circuit 11 is electrically connected to the input end of the level conversion circuit 12, and the output end of the input / output control circuit 11 is also electrically connected to the ground port;

[0115] The input / output control circuit 11 is used to output the low-voltage domain input signal to the level conversion circuit 12;

[0116] The input end of the level conversion circuit 12 is also electrically connected to the output end of the high-voltage power supply port, and the output end of the level conversion circuit 12 is electrically connected to the input end and the ground port of the slope control circuit 20. The level conversion circuit 12 is used to convert the low-voltage domain input signal into a high-voltage domain input signal, and input the high-voltage domain input signal into the slope control circuit 20.

[0117] In this embodiment, when the enable port OEN=1, the input signal I passing through the input-output circuit is invalid, and the bidirectional input-output port PAD serves as an input port; when the enable port OEN=0, the bidirectional input-output port PAD serves as an output port, and the low-voltage domain input signal I passing through the input-output circuit is input to the level conversion circuit 12 through a logical NOT operation, and the level conversion circuit 12 converts the low-voltage domain input signal into a high-voltage domain input signal.

[0118] like Figure 2 As shown, further, the input and output circuit includes a NOT gate circuit, a NAND gate circuit and a NOR gate circuit;

[0119] The input end of the NOT gate circuit is electrically connected to the enable port and the low-voltage power supply port, and the output end of the NOT gate circuit is electrically connected to the ground port;

[0120] The input end of the NAND gate circuit is electrically connected to the input port and the low-voltage power supply port, the output end of the NAND gate circuit is electrically connected to the input end of the NOT gate circuit and the input end of the level conversion circuit 12, and the output end of the NOT gate circuit is electrically connected to the ground port;

[0121] The input end of the NOR gate circuit is electrically connected to the input port, the enable port and the low voltage power port, the output end of the NOR gate circuit is electrically connected to the level conversion circuit 12, and the output end of the NOR gate circuit is also electrically connected to the ground port.

[0122] like Figure 2 As shown, specifically, the NOT gate circuit includes a PMOS transistor PM2 and an NMOS transistor NM2. The drain of PM2 is electrically connected to net27, the gate of PM2 is electrically connected to the enable port OEN, and the source of PM2 is electrically connected to the low-voltage power supply port VDD. The drain of NM2 is electrically connected to net27, the gate of NM2 is electrically connected to the enable port OEN, and the source of NM2 and the substrate are electrically connected to the ground port VSS.

[0123] The NAND gate circuit includes PMOS transistors PM3 and PM4, and NMOS transistors NM2 and NM3. PM3 and PM4 are connected in parallel, and their drains are both electrically connected to net25. The sources of PM3 and PM4 are electrically connected to the low-voltage power supply port VDD. The gate of PM3 is electrically connected to the input port I, and the gate of PM4 is electrically connected to net27. The drain of NM3 is electrically connected to net25, the gate of NM3 is electrically connected to net27, and the substrate of NM3 is electrically connected to the ground port VSS. The source of NM3 is connected in series to the drain of NM4 via net37. The gate of NM4 is electrically connected to the input port I, and the source of NM4 is electrically connected to the ground port VSS.

[0124] The NOR gate circuit includes PMOS transistors PM0 and PM1, and NMOS transistors NM0 and NM1. PM0's gate is electrically connected to input port I, PM0's source is electrically connected to low-voltage power supply port VDD, PM0's drain is electrically connected to PM1's source via net28, PM1's gate is electrically connected to enable port OEN, PM1's drain is electrically connected to net24, and PM1's source is electrically connected to low-voltage power supply port VDD. NM0 and NM1 are connected in parallel, their drains are electrically connected to net24, their sources and substrates are electrically connected to ground port VSS, NM0's gate is electrically connected to input port I, and NM1's gate is electrically connected to enable port OEN.

[0125] like Figure 3 As shown, further, the level conversion circuit 12 includes a first level conversion circuit 121 and a second level conversion circuit 122;

[0126] The input end of the first level conversion circuit 121 is electrically connected to the output end of the NAND gate circuit;

[0127] The output terminal of the first level conversion circuit 121 is electrically connected to the input terminal of the PMOS driving module 21;

[0128] The input terminal of the second level conversion circuit 122 is electrically connected to the output terminal of the NOR gate circuit;

[0129] An output terminal of the second level conversion circuit 122 is electrically connected to an input terminal of the NMOS driving module 22 .

[0130] like Figure 3 As shown, specifically, the low-voltage devices in the first level conversion circuit 121 include a PMOS transistor PM5 and an NMOS transistor NM5, the source of PM5 is electrically connected to the low-voltage power supply port VDD, the gate of PM5 is electrically connected to net50, and the drain of PM5 is electrically connected to net22; the source of NM5 is electrically connected to the ground port VSS, the gate of NM5 is electrically connected to net25, and the drain of NM5 is electrically connected to net22.

[0131] The high-voltage devices in the first level shifter circuit 121 include PMOS transistors PM6 and PM7, and NMOS transistors NM6, NM7, NM8, and NM9. The source of PM6 is electrically connected to the high-voltage power supply port VDD50, the gate of PM6 is electrically connected to net684, and the drain of PM6 is electrically connected to net21. The source of PM7 is electrically connected to the high-voltage power supply port VDD50, the gate of PM7 is electrically connected to net21, and the drain of PM7 is electrically connected to net684. The source of NM6 is electrically connected to the ground port VSS, the gate of NM6 is electrically connected to net22, and the drain of NM6 is electrically connected to net21. The source and gate of NM7 are electrically connected to net22, and the drain of NM7 is electrically connected to net684. The source and gate of NM8 are electrically connected to net25, and the drain is connected to net21. The source of NM9 is connected to VSS, the gate is connected to net25, and the drain is connected to net684.

[0132] The low-voltage devices in the second level conversion circuit 122 include a PMOS transistor PM10 and an NMOS transistor NM10. The source of PM10 is electrically connected to the low-voltage power supply port VDD, the gate of PM10 is electrically connected to net24, and the drain of PM10 is electrically connected to net29; the source of NM10 is electrically connected to the ground port VSS, the gate of N M10 is electrically connected to net24, and the drain of NM10 is electrically connected to net29.

[0133] The high-voltage devices in the second level conversion circuit 122 include PMOS transistors PM8 and PM9 , and NMOS transistors NM11 , NM12 , NM13 , and NM14 . The source of PM8 is electrically connected to the high-voltage power supply port VDD50, the gate of PM8 is electrically connected to net30, and the drain of PM8 is electrically connected to net26; the source of PM9 is electrically connected to the high-voltage power supply port VDD50, the gate of PM9 is electrically connected to net26, and the drain of PM9 is electrically connected to net30; the source of NM11 is electrically connected to the ground port VSS, the gate of NM11 is electrically connected to net29, and the drain of NM11 is electrically connected to net26; the source and gate of NM12 are electrically connected to net29, and the drain of NM12 is electrically connected to net30; the source and gate of NM13 are electrically connected to net24, and the drain of NM12 is electrically connected to net26; the source of NM14 is electrically connected to the ground port VSS, the gate of NM14 is electrically connected to net24, and the drain of NM12 is electrically connected to net30.

[0134] like Figure 1 As shown, further, the second input-output driving circuit 30 includes a driving and ESD protection circuit 31 and a second input driving circuit 32;

[0135] The input end of the driving and ESD protection circuit 31 is electrically connected to the output end of the PMOS driving module 21 and the output end of the NMOS driving module 22;

[0136] The output terminal of the driving and ESD protection circuit 31 is electrically connected to the ground port;

[0137] The input end of the second input driving circuit 32 is electrically connected to the output end of the driving and ESD protection circuits and the power port; the output end of the second input driving circuit 32 is electrically connected to the output port and the ground port;

[0138] The driving and ESD protection circuit 31 and the second input driving circuit 32 are also electrically connected to the bidirectional input and output port.

[0139] like Figure 5 As shown, further, the power port includes a high-voltage power port and a low-voltage power port; the driving and ESD protection circuit 31 includes a first driving PMOS transistor, a first driving NMOS transistor, a first switching logic circuit and a second switching logic circuit;

[0140] The source of the first driving PMOS transistor is electrically connected to the high-voltage power supply port, the gate of the first driving PMOS transistor is electrically connected to the output end of the PMOS driving module 21, and the drain of the first driving PMOS transistor is electrically connected to the bidirectional input and output port;

[0141] The source of the first driving NMOS transistor is electrically connected to the ground port, the gate of the first driving NMOS transistor is electrically connected to the output end of the NMOS driving module 22, and the drain of the first driving NMOS transistor is electrically connected to the bidirectional input and output port;

[0142] A first end of the first switch logic circuit is connected to the high-voltage power supply port, a second end of the first switch logic circuit is electrically connected to the ground port, and a third end of the first switch logic circuit is electrically connected to the bidirectional input and output port;

[0143] A first end of the second switch logic circuit is connected to the high voltage power supply port, a second end of the second switch logic circuit is electrically connected to the ground port, and a third end of the second switch logic circuit is electrically connected to the bidirectional input and output port.

[0144] In this embodiment, the ESD protection circuit adopts a GCMOS structure. Compared with the traditional method of using MOS parasitic transistor breakdown to conduct discharge, the GCMOS structure greatly reduces the trigger voltage of the MOS parasitic transistor, and the interdigital structure has better discharge consistency.

[0145] like Figure 5 As shown, specifically, the first driving PMOS transistor is PM21, the first driving NMOS transistor is NM21, and the first switching logic circuit and the second switching logic circuit further include high-voltage PMOS transistors PM22, PM23 and high-voltage NMOS transistors NM22, NM23 respectively.

[0146] The source of PM21 is electrically connected to the high-voltage power supply port VDD50 , the gate of PM21 is electrically connected to the ground port VSSD, the drain of PM21 is electrically connected to the gate of PM23 , and the drain of PM23 is electrically connected to the bidirectional input / output port PAD.

[0147] The substrate and source of NM21 are electrically connected to the high-voltage power supply port VDD50, the gate of NM21 is electrically connected to the third signal terminal D, and the drain of NM21 is electrically connected to the bidirectional input / output port PAD. The substrates and sources of NM22 and NM23 are electrically connected to the ground port VSSD, the gate of NM22 is electrically connected to the high-voltage power supply port VDD50, the drain of NM22 is electrically connected to the gate of NM23, and the drain of NM23 is electrically connected to the bidirectional input / output port PAD.

[0148] PM21 and NM21 serve as output driver tubes. The gate of PM21 is connected to signal B, and the gate of NM21 is connected to signal D. By adjusting the gear position of signal B and signal D output by the previous-stage PMOS driver module 21 and NMOS driver module 22, the drain output of PM21 and NM21 can be controlled to achieve the purpose of output slope adjustment.

[0149] PM22, PM23, NM22, and NM23 in the first switching logic circuit and the second switching logic circuit form a GCMOS structure, and together with PM21 and NM21 as output driver transistors, serve as the main discharge path of the ESD protection circuit.

[0150] like Figure 6 As shown, further, the second input drive circuit 32 includes a high voltage circuit 321 and a low voltage circuit 322;

[0151] The input end of the high-voltage circuit 321 is electrically connected to the bidirectional input and output port and the high-voltage power supply port, and the output end of the high-voltage circuit 321 is electrically connected to the input end of the low-voltage circuit 322;

[0152] The low voltage circuit 322 includes a multi-stage inverter, the input end of the multi-stage inverter is electrically connected to the output end of the high voltage circuit 321 and the low voltage power supply port, and the output end of the multi-stage inverter is electrically connected to the output port and the ground port.

[0153] The second input driving circuit 32 realizes the signal level conversion from the signal input from the high voltage power supply port VDD50 to the signal level conversion from the low voltage power supply port VDD.

[0154] like Figure 6 As shown, specifically, the high-voltage circuit 321 includes high-voltage PMOS transistors PM24 and PM25 and a resistor R1 , and the low-voltage circuit 322 includes PMOS transistors PM26 , PM27 , PM28 and NMOS transistors NM26 , NM27 , NM28 .

[0155] The N-wells of PM24 and PM25 are electrically connected to the high-voltage power supply port VDD50. The source of PM24 is electrically connected to the high-voltage power supply port VDD50, the gate of PM24 is electrically connected to the second end of resistor R1, and the drain of PM24 is connected to net680. The source of PM25 is electrically connected to net680, the gate of PM25 is electrically connected to net677, and the drain of PM25 is electrically connected to net686. The substrates of NMOS transistors NM24 and NM25 are electrically connected to the ground port VSS. The source of NM24 is electrically connected to net677, the gate of NM24 is electrically connected to the high-voltage power supply port VDD50, and the drain of NM24 is electrically connected to net685. The source of NM25 is electrically connected to the ground port VSS, the gate of NM25 is electrically connected to net677, and the drain of NM25 is electrically connected to net686. The two ends of resistor R1 are respectively connected to the bidirectional input / output port PAD and net685.

[0156] Among them, resistor R1 serves as a current limiting resistor and as the secondary circuit of the ESD protection structure to protect the gate oxide structure of the PM24 tube, preventing the gate oxide layer from being broken down and causing thermal breakdown due to large current and irreversible damage, which may lead to circuit failure.

[0157] Low-voltage circuit 322 includes a three-stage inverter. The sources of PMOS transistors PM26, PM27, and PM28 are electrically connected to power supply port VDD, while the substrates and sources of NMOS transistors NM26, NM27, and NM28 are electrically connected to ground port VSS. The gates of PM26 and NM26 are electrically connected to net 686, and their drains are connected to net 34. The gates of PM27 and NM27 are electrically connected to net 34, and their drains are electrically connected to net 683. The gates of PM28 and NM28 are electrically connected to net 683, and their drains are connected to output port C.

[0158] This embodiment further provides a chip including the bidirectional IO circuit described above. The chip in this embodiment has similar effects to the bidirectional IO circuit, and will not be described in detail here.

[0159] Test Case

[0160] A simulation environment test is set up on the circuit of Example 1. The simulation environment is described as follows:

[0161] The decoder module outputs two control signals for 4-bit decoding output of the adjustment signal A <0> 、A <1> 、A <2> 、A <3> 、A_N <0> 、A_N <1> 、A_N <2> 、A_N <3> , A <0> with A_N <0> 、A <1> with A_N <1> 、A <2> with A_N <2> 、A <3> with A_N <3> Opposite signals.

[0162] A <3> 、A_N <3> When the controlled MOS tubes NM17 and PM17 are turned on and NM18, NM19, NM20, PM18, PM19, and PM20 are turned off, the gate resistance of PM21 and NM21 in the working state is the largest, and the output delay is the largest; when the PMOS tube or NMOS tube in the slope control circuit is fully turned on, the gate resistance of PM21 and NM21 in the working state is the smallest, and the output delay is the smallest.

[0163] Set the enable port OEN to low, the output port I to output mode, and the input signal I to a square wave signal with a period of 10ns.

[0164] When the PMOS and NMOS tubes in the slope control circuit are fully turned on, the result is as follows Figure 7 As shown:

[0165] A <0> 、A <1> 、A <2> 、A <3> High, NM17, NM18, NM19, and NM20 are turned on;

[0166] A_N <0> 、A_N <1> 、A_N <2> 、A_N <3> For low, PM17, PM18, PM19, and PM20 are turned on;

[0167] When the signal I changes from low to high, the first PMOS transistor is turned on, and the maximum slope of the drain output current change of the first driver PMOS transistor PM21 is 127; when the signal I changes from high to low, the first NMOS transistor is turned on, and the maximum slope of the drain output current change of the first driver NMOS transistor NM21 is -73 ("-" represents the direction).

[0168] When only NM17 and PM17 are turned on in the slope control circuit, the result is as follows: Figure 8 As shown, A <3> High, NM17 is turned on, A <0> 、A <1> 、A <2> is low, NM18, NM19 and NM20 are closed;

[0169] A_N <3> is low, PM17 is turned on; A_N <0> 、A_N <1> 、A_N <2> is high, PM18, PM19, and PM20 are closed;

[0170] When the signal I changes from low to high, the first PMOS transistor PM17 is turned on, and the maximum slope of the drain output current change of the first driver PMOS transistor PM21 is 31; when the signal I changes from high to low, the first NMOS transistor NM17 is turned on, and the maximum slope of the drain output current change of the first driver NMOS transistor NM21 is -27 ("-" represents the direction).

[0171] The results are shown in the following table:

[0172] Table 1

[0173]

[0174] By connecting the decoder module through the first logic control unit and the second logic control unit, the resistance value of the driving resistor between the drain of the first PMOS tube and the first NMOS tube is adjusted, and the current change slope output by the PMOS driving module or the NMOS driving module can be adjusted, thereby adjusting the operating speed of the circuit.

[0175] When the input port operates at a high speed, increasing the drive resistor in the slope control circuit reduces the current slope of the PMOS or NMOS driver module, thereby minimizing the impact of ground bounce noise. When the input port ground bounce noise is less significant, reducing the drive resistor in the slope control circuit increases the current slope. This allows the slope control circuit to adjust the current slope appropriately during chip packaging based on the chip's process corner, achieving a compromise between circuit operating speed and ground bounce noise, thereby improving chip yield.

[0176] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A bidirectional IO circuit, characterized in that: include: Power port, enable port, input port, ground port, first input drive circuit, slope control circuit, second input and output drive circuit, bidirectional input and output port and output port; The input end of the first input drive circuit is electrically connected to the output end of the enable port, the output end of the input port and the power port; The output end of the first input driving circuit is electrically connected to the input end of the slope control circuit and the ground port; The input end of the slope control circuit is electrically connected to the output end of the first input drive circuit, and the output end of the slope control circuit is electrically connected to the input end of the second input-output drive circuit; The slope control circuit includes a PMOS driving module and an NMOS driving module; The PMOS driver module includes a first PMOS transistor, a first NMOS transistor, and a first logic control unit. The gate of the first PMOS transistor and the gate of the first NMOS transistor are electrically connected to the first output terminal of the first input driver circuit. The N-well and source of the first PMOS transistor are electrically connected to the power port. The substrate and source of the first NMOS transistor are electrically connected to the ground port. A plurality of first driving resistors are connected in series between the drain of the first PMOS transistor and the drain of the first NMOS transistor. The drain of the first PMOS transistor is also electrically connected to the first input terminal of the second input-output driver circuit. The first logic control unit includes a plurality of first switch units, any two adjacent first drive resistors are electrically connected to a first end of a first switch unit, and the second end of each first switch unit is electrically connected to the drain of the first NMOS transistor; The NMOS driver module includes a second PMOS transistor, a second NMOS transistor, and a second logic control unit, wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are electrically connected to the second output terminal of the first input driver circuit, the N well and source of the second PMOS transistor are electrically connected to the power port, the substrate and source of the second NMOS transistor are electrically connected to the ground port, a second driving resistor is connected in series between the drain of the second PMOS transistor and the drain of the second NMOS transistor, and the drain of the second NMOS transistor is also electrically connected to the second input terminal of the second input-output driver circuit; The second logic control unit includes a plurality of second switch units, any two adjacent second drive resistors are electrically connected to the first end of a second switch unit, and the second end of each second switch unit is electrically connected to the drain of the second PMOS transistor; The second input / output driving circuit is also electrically connected to the bidirectional input / output port and the output port.

2. The circuit according to claim 1, wherein: N-1 groups of first driving resistors are connected in series between the drains of the first PMOS transistor and the first NMOS transistor, where N is a positive integer and is greater than or equal to 2; The first switch unit is an NMOS transistor, and the first logic control unit includes N groups of the NMOS transistors; The gates of the N groups of NMOS transistors are all used to be electrically connected to the first signal output terminal of the decoder module, the drains of the N groups of NMOS transistors are all electrically connected to the drain of the first NMOS transistor, and the substrates of the N groups of NMOS transistors are all electrically connected to the ground port; The source of the NMOS transistor of the first group is electrically connected between the first end of the first driving resistor of the first group and the drain of the first NMOS transistor, and the source of the NMOS transistor of the second group to the Nth group is electrically connected to the second end of the first driving resistor of the first group to the N-1th group in sequence.

3. The circuit according to claim 2, characterized in that N groups of second driving resistors are connected in series between the drains of the second PMOS transistor and the second NMOS transistor, where N is a positive integer and is greater than or equal to 2; The second switch unit is a PMOS tube, and the second logic control unit includes N groups of the PMOS tubes; The gates of the N groups of PMOS transistors are all used to electrically connect to the second signal output terminal of the decoder module, and the signal output by the second signal output terminal is opposite to the signal output by the first signal output terminal; The N wells of the N groups of PMOS transistors are all electrically connected to the power port, and the sources of the N groups of PMOS transistors are all electrically connected to the drain of the second PMOS transistor; The drains of the first to Nth groups of PMOS transistors are electrically connected to the first ends of the first to Nth groups of the second driving resistors, respectively.

4. The circuit according to claim 2 or 3, characterized in that N is greater than or equal to 4.

5. The circuit according to claim 1, wherein: The first input drive circuit includes an input / output control circuit and a level conversion circuit, and the power supply port includes a low-voltage power supply port and a high-voltage power supply port; The input end of the input-output control circuit is electrically connected to the enable port, the input port and the low-voltage power supply port; The output end of the input-output control circuit is electrically connected to the input end of the level conversion circuit and the ground port; The input-output control circuit is used to output the low-voltage domain input signal to the level conversion circuit; The input end of the level conversion circuit is also electrically connected to the output end of the high-voltage power supply port, and the output end of the level conversion circuit is electrically connected to the input end of the slope control circuit and the ground port. The level conversion circuit is used to convert the low-voltage domain input signal into a high-voltage domain input signal, and input the high-voltage domain input signal into the slope control circuit.

6. The circuit according to claim 5, characterized in that The input and output circuits include a NOT gate circuit, a NAND gate circuit and a NOR gate circuit; The input end of the NOT gate circuit is electrically connected to the enable port and the low-voltage power supply port, and the output end of the NOT gate circuit is electrically connected to the ground port; The input end of the NAND gate circuit is electrically connected to the input port and the low-voltage power supply port, the output end of the NAND gate circuit is electrically connected to the input end of the NOT gate circuit and the input end of the level conversion circuit, and the output end of the NOT gate circuit is electrically connected to the ground port; The input end of the NOR gate circuit is electrically connected to the input port, the enable port and the low-voltage power supply port, the output end of the NOR gate circuit is electrically connected to the level conversion circuit, and the output end of the NOR gate circuit is also electrically connected to the ground port.

7. The circuit according to claim 6, characterized in that The level conversion circuit includes a first level conversion circuit and a second level conversion circuit; The input end of the first level conversion circuit is electrically connected to the output end of the NAND gate circuit; The output end of the first level conversion circuit is electrically connected to the input end of the PMOS driving module; The input end of the second level conversion circuit is electrically connected to the output end of the NOR gate circuit; The output end of the second level conversion circuit is electrically connected to the input end of the NMOS driving module.

8. The circuit according to claim 1, wherein: The second input-output driving circuit includes a driving and ESD protection circuit and a second input driving circuit; The input end of the driving and ESD protection circuit is electrically connected to the output end of the PMOS driving module and the output end of the NMOS driving module; The output end of the driving and ESD protection circuit is electrically connected to the ground port; The input end of the second input drive circuit is electrically connected to the output end of the drive and ESD protection circuit and the power port; The output end of the second input driving circuit is electrically connected to the output port and the ground port; The driving and ESD protection circuit and the second input driving circuit are also electrically connected to the bidirectional input and output port.

9. The circuit according to claim 8, characterized in that The power port includes a high-voltage power port and a low-voltage power port; the driving and ESD protection circuit includes a first driving PMOS transistor, a first driving NMOS transistor, a first switching logic circuit and a second switching logic circuit; The source of the first driving PMOS transistor is electrically connected to the high-voltage power supply port, the gate of the first driving PMOS transistor is electrically connected to the output end of the PMOS driving module, and the drain of the first driving PMOS transistor is electrically connected to the bidirectional input and output port; The source of the first driving NMOS transistor is electrically connected to the ground port, the gate of the first driving NMOS transistor is electrically connected to the output end of the NMOS driving module, and the drain of the first driving NMOS transistor is electrically connected to the bidirectional input and output port; A first end of the first switch logic circuit is connected to the high-voltage power supply port, a second end of the first switch logic circuit is electrically connected to the ground port, and a third end of the first switch logic circuit is electrically connected to the bidirectional input and output port; The first end of the second switch logic circuit is connected to the high-voltage power supply port, the second end of the second switch logic circuit is electrically connected to the ground port, and the third end of the second switch logic circuit is electrically connected to the bidirectional input and output port.

10. The circuit according to claim 9, characterized in that The second input drive circuit includes a high voltage circuit and a low voltage circuit; The input end of the high-voltage circuit is electrically connected to the bidirectional input and output port and the high-voltage power supply port, and the output end of the high-voltage circuit is electrically connected to the input end of the low-voltage circuit; The low-voltage circuit includes a multi-stage inverter, the input end of the multi-stage inverter is electrically connected to the output end of the high-voltage circuit and the low-voltage power supply port, and the output end of the multi-stage inverter is electrically connected to the output port and the ground port.

11. A chip, characterized in that: The method comprises the bidirectional IO circuit according to any one of claims 1 to 9.

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