VDMOS structure and power semiconductor device

Abstract

The utility model provides a VDMOS structure and a power semiconductor device. The VDMOS structure comprises a substrate, an epitaxial layer and a gate structure, wherein the epitaxial layer and the gate structure are arranged at one side of the substrate; the well regions are located in the epitaxial layer and located on the two sides of the gate structure; the source electrode region, the doped region and the metal layer are located in the well region, the source electrode region and the doped region extend into the epitaxial layer from the top surface of the epitaxial layer, the metal layer is located between the doped region and the bottom surface of the well region, and the bottom surface of the metal layer is higher than the bottom surface of the well region; the drain electrode is positioned on the other side of the substrate; the substrate, the epitaxial layer and the source region are of a first doping type, and the well region and the doping region are of a second doping type. Therefore, the resistance of the resistance region below the source region in the well region is reduced due to the existence of the metal layer and the doped region, the generated forward voltage drop is smaller than the positive bias voltage of the parasitic transistor, the parasitic transistor is disconnected, hole current flows out along the path of the well region, the metal layer, the doped region and the source, the risk of device failure caused by avalanche breakdown is avoided, and the reliability of the device is improved. And the reliability of the power semiconductor device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of power semiconductors, in particular to a VDMOS structure and a power semiconductor device. Background Art

[0002] VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor) is a vertical conductive device characterized by high operating frequency, fast switching speed, and low loss. Its most common application is as a power switch to control power conversion, typically controlling and driving inductive loads. Consequently, it frequently experiences high-frequency switching during operation. When the VDMOS is suddenly turned off, the energy accumulated in the inductive load continues to maintain a longitudinal current between the source and drain, causing the drain voltage to rise and triggering avalanche breakdown, releasing the accumulated energy in the load.

[0003] Take N-channel VDMOS as an example, Figure 1 As shown, the VDMOS contains a bipolar NPN parasitic transistor T. This parasitic transistor T is the primary factor affecting the device's avalanche withstand capability. When the device experiences avalanche breakdown and generates a transient high current, the hole current flows along the path of the P-type well region 11, the doped region 12, the source region 13, and the source electrode S. Rb is a resistor located in the resistance region below the source region 13. When the current flowing through this resistor is large enough, the forward voltage drop generated is greater than the positive bias voltage between the base and emitter of the parasitic transistor, turning on the parasitic transistor T. This causes current concentration, secondary breakdown, and ultimately device failure.

[0004] Generally speaking, VDMOS has a certain level of avalanche breakdown resistance. However, when the inductive energy exceeds the VDMOS's tolerance range, the sudden high current can cause device failure or even burnout. Therefore, optimizing the avalanche resistance of the VDMOS structure to improve its reliability has long been a challenge for the industry. Utility Model Content

[0005] In order to overcome the above-mentioned defects, the present invention is proposed to solve or at least partially solve the technical problems of poor avalanche withstand capability and low reliability of the existing VDMOS structure.

[0006] In a first aspect, the present invention provides a VDMOS structure, comprising:

[0007] substrate;

[0008] an epitaxial layer located on one side of the substrate, the epitaxial layer having a bottom surface facing the substrate and a top surface away from the substrate;

[0009] a gate structure located on the top surface of the epitaxial layer, the gate structure comprising a gate dielectric layer and a gate that are stacked;

[0010] a well region in the epitaxial layer, the well region extending from the top surface of the epitaxial layer into the epitaxial layer, the bottom surface of the well region being located in the epitaxial layer, and the well region being located on both sides of the gate structure;

[0011] a source region, a stacked doped region, and a metal layer located in the well region, wherein the source region and the doped region extend from the top surface of the epitaxial layer into the epitaxial layer respectively; along the width direction of the well region, the edge of the source region is tangent to the edge of the doped region; the metal layer is located between the doped region and the bottom surface of the well region, and the bottom surface of the metal layer is higher than the bottom surface of the well region;

[0012] a drain located on the other side of the substrate;

[0013] The substrate, the epitaxial layer and the source region are of a first doping type, the well region and the doping region are of a second doping type, and the first doping type and the second doping type are different.

[0014] Furthermore, in the above-mentioned VDMOS structure, the depth of the source region is smaller than the depth of the doped region.

[0015] Furthermore, in the above-mentioned VDMOS structure, the orthographic projection of the metal layer on the substrate surface coincides with the orthographic projection of the doped region on the substrate surface.

[0016] Furthermore, in the above-mentioned VDMOS structure, along the depth direction of the well region, the highest point of the top surface of the metal layer is lower than the lowest point of the bottom surface of the source region.

[0017] Furthermore, in the above-mentioned VDMOS structure, the well region is a doped silicon region, the doped region is a doped silicon region, and the doping concentration of the doped region is greater than the doping concentration of the well region.

[0018] Furthermore, in the above-mentioned VDMOS structure, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.

[0019] In a second aspect, the present invention provides a power semiconductor device comprising a plurality of cells, each cell comprising the VDMOS structure described in any one of the above items, wherein the source regions in the plurality of cells are electrically connected together, and the drain regions in the plurality of cells are electrically connected together.

[0020] Furthermore, the power semiconductor device described above further comprises a plurality of terminal rings arranged at intervals, wherein the innermost terminal ring defines an active region, and the plurality of cells are located within the active region;

[0021] Furthermore, in the power semiconductor device described above, the depth of the innermost terminal ring is greater than or equal to the depth of the well region.

[0022] The VDMOS structure and power semiconductor device provided by the utility model reduce the resistance of the resistance region below the source region by arranging a metal layer in the well region. At the same time, a doping region with a doping concentration greater than that of the well region is arranged above the metal layer, so that the concentration of the resistance region is increased and the resistance is correspondingly reduced. Therefore, when a hole current is generated, the forward voltage drop generated by the resistance region is less than the positive bias voltage of the base and emitter of the parasitic transistor. When the parasitic transistor is disconnected, the hole current does not flow along the path of the parasitic transistor, but flows along the path of the well region, the metal layer, the doping region, and the source. This avoids the risk of device failure due to avalanche breakdown to the greatest extent, thereby improving the reliability of the VDMOS structure and the power semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The disclosure of the present invention will become more easily understood with reference to the accompanying drawings. Those skilled in the art will readily appreciate that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. Furthermore, similar numbers in the drawings represent similar structures or regions, where:

[0024] Figure 1 is a schematic diagram of an existing VDMOS structure;

[0025] Figure 2 is a schematic diagram of a VDMOS structure according to an embodiment of the present invention;

[0026] Figures 3a to 3i is formed Figure 2 The structural diagram corresponding to some process steps of the VDMOS structure shown. DETAILED DESCRIPTION

[0027] To make the above-mentioned objects, features, and advantages of the present invention more clearly understood, the following detailed description of specific embodiments of the present invention is provided in conjunction with the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0028] In the description of this utility model, the terms "first," "second," etc. are used solely for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the technical features indicated. Furthermore, in this utility model, unless otherwise expressly specified or limited, the terms "connected" and "connected" should be interpreted broadly, meaning, for example, directly connected or indirectly connected through an intermediary, unless otherwise expressly limited. Those skilled in the art will understand the specific meanings of these terms in this utility model based on the specific circumstances.

[0029] Figure 2 FIG. 1 is a schematic structural diagram of a power semiconductor device according to an embodiment of the present invention. Figure 2 As shown, the power semiconductor device includes a substrate of a first doping type (not shown in the figure), an epitaxial layer 18 of a first doping type, a well region 11 of a second doping type, a source region 13 of a first doping type, a doping region 12 of a second doping type, a metal layer 19, a gate dielectric layer 16, a gate G and a drain (not shown in the figure). The first doping type can be N-type or P-type, and the second doping type is opposite to the first doping type, that is, when the first doping type is N-type, the second doping type is P-type, and when the first doping type is P-type, the second doping type is N-type. The following is an example in which the first doping type is N-type and the second doping type is P-type. In addition, for the convenience of explanation, the surface of the epitaxial layer 18, the source region 13, the metal layer 19 and the doping region 12 close to the substrate is called the bottom surface, the surface away from the substrate is called the top surface, the direction from the top surface to the bottom surface or from the bottom surface to the top surface is called the longitudinal direction, and the surface parallel to the substrate is called the lateral direction.

[0030] Specifically, the N-epitaxial layer 18 is located on one side of the N+ substrate, i.e., the front side of the N+ substrate. The gate structure is located on the top surface of the N-epitaxial layer 18. The P-type well region 11 is located within the N-epitaxial layer 18, extending longitudinally from the top surface of the N-epitaxial layer 18 into the N-epitaxial layer 18, and the P-type well region 11 is located on both sides of the gate structure and extends laterally below the gate structure, so that the gate structure partially covers the P-type well regions 11 on both sides below it. The N+ source region 13 is located within the P-type well region 11, extending longitudinally from the top surface of the N-epitaxial layer 18 into the N-epitaxial layer 18, and the N+ source region 13 is located on both sides below the gate structure.

[0031] P+ doped region 12 is located within P-type well region 11 and extends from the top surface of epitaxial layer 18 into epitaxial layer 18. P+ doped region 12 is heavily P-type doped single crystal silicon with a greater doping concentration than P-type well region 11. It replaces the P+ contact region in the existing VDMOS process and continues P-type well region 11. It also maintains a correspondence with the original crystal orientation, reducing defect distribution. Metal layer 19 is located within P-type well region 11 and is stacked with P+ doped region 12. Metal layer 19 is located on the side of P+ doped region 12 closest to the N+ substrate, meaning that metal layer 19 is "suspended" within P-type well region 11.

[0032] The gate structure includes a stacked gate dielectric layer 16 and a gate G. The gate dielectric layer 16 is located on top of the epitaxial layer 18, and the orthographic projection of the gate dielectric layer 16 on the N+ substrate surface partially overlaps with the orthographic projection of the P-type well region 11 on the N+ substrate surface. That is, the gate dielectric layer 16 covers a portion of the P-type well region 11. The gate G is located on the gate dielectric layer 16, and the orthographic projection of the gate G on the N+ substrate surface partially overlaps with the orthographic projection of the P-type well region 11 on the N+ substrate surface. The drain is located on the other side of the N+ substrate, that is, the drain is located on the back side of the N+ substrate. The gate G can be a polysilicon gate; the gate dielectric layer 16 can be made of silicon oxide, a stack of silicon oxide and silicon nitride layers, or other materials that can serve as a gate dielectric; and the drain can be a metal layer formed on the back side of the N+ substrate.

[0033] Compared with existing power semiconductor devices, the power semiconductor device provided in this embodiment is equivalent to replacing part of the P-type well region 11 in the existing VDMOS structure with the metal layer 9, thereby improving the conductivity and reducing the resistance of the resistance region below the N+ source region 13. At the same time, due to the presence of the P+ doped region 12, the doping concentration of the resistance region below the N+ source region 13 is increased, further reducing the resistance of the resistance region. As a result, when the power semiconductor device is suddenly turned off, the energy accumulated in the inductive load will continue to maintain the longitudinal current between the source and the drain. The forward voltage drop generated by the resistance region is less than the positive bias voltage between the base and the emitter of the parasitic transistor. The parasitic transistor is turned off, and the hole current does not flow along the path of the parasitic transistor. Instead, it flows along the path of the P-type well region 11, the metal layer 19, the P+ doped region 12, and the source S. This minimizes the risk of device failure due to avalanche breakdown, thereby improving the reliability of the power semiconductor device. In addition, since the metal layer 19 is “suspended” in the P-type well region 11 , it will not substantially affect the electrical parameters of the power semiconductor device, such as withstand voltage and leakage current.

[0034] On this basis, compared with existing power semiconductor devices, the power semiconductor device provided in this embodiment has the following difference: along the width direction of the well region 11, the edge of the N+ source region 13 is tangent to the edge of the P+ doped region 12. In other words, the N+ source region 13 and the P+ doped region 12 at least partially share the same edge. In this way, during the processing process, the N+ source region 13 can be formed first, then etched to form a groove, and then the metal layer 19 and the P+ doped region 12 can be filled in the groove.

[0035] In a specific implementation process, the depth of the N+ source region 13 is less than the depth of the P+ doping region 12. In addition, for the metal layer 19, this embodiment does not limit the shape of its top surface, which can be horizontal or in other shapes, such as Figure 2 In the structure shown, the top of the metal layer 19 is curved in a longitudinal cross-section; other structures are also possible. Along the depth direction of the well region, the highest point of the top surface of the metal layer 19 is lower than the lowest point of the bottom surface of the N+ source region 13.

[0036] In a specific implementation process, the orthographic projection of the metal layer 19 on the substrate surface coincides with the orthographic projection of the P+ doped region 12 on the substrate surface, that is, the metal layer 19 and the P+ doped region 12 are the same in the width direction of the well region 11.

[0037] Those skilled in the art will appreciate that, in this power semiconductor device, an insulating dielectric layer 14 and a source electrode S are sequentially provided on the side of the gate G away from the N+ substrate, and the source electrode S is electrically connected to the N+ source region 13 via a via penetrating the insulating dielectric layer 14 and the gate dielectric layer 16. The insulating dielectric layer 14 covers the top and side surfaces of the gate structure.

[0038] It should be noted that Figure 2 The power semiconductor device shown in the figure is actually a part of two VDMOS structures. Each VDMOS structure can be regarded as a cell. Figure 2 The dashed line in the figure is the boundary. The left side of the dashed line is half of the first cell, and the right side of the dashed line is half of the second cell, and the two cells are symmetrical with respect to the dashed line. In practice, the power semiconductor device can include more cells, and multiple cells are connected in parallel. Specifically, the power semiconductor device can include multiple terminal rings, which are arranged concentrically, for example, with the innermost terminal ring defining an active area. Multiple cells are arranged in the active area, and multiple cells are connected in parallel.

[0039] Further references Figure 2For two adjacent VDMOS structures, their P-type well regions 11 form a single integrated structure. During actual manufacturing, the P-type well regions 11 of each VDMOS structure are typically formed simultaneously, and the P-type well regions 11 of adjacent VDMOS structures are connected to form a single doped region. Similarly, the same principle applies to metal layer 19 and P+ doped region 12, and will not be further elaborated.

[0040] In a specific implementation process, along the depth direction of the P-type well region 11 , or in other words, along the longitudinal direction, the depth of the source region is less than the depth of the P+ doping region 12 .

[0041] As previously mentioned, the power semiconductor device may further include a plurality of spaced-apart terminal rings (not shown). The innermost terminal ring defines the active region. In a preferred embodiment, the depth of the innermost terminal ring is greater than or equal to the depth of the P-type well region 11. This not only improves avalanche withstand capability, but also ensures that electrical parameters such as withstand voltage and leakage current are substantially unaffected.

[0042] It should be noted that the terminal ring is an annular structure surrounding the active area of ​​the power semiconductor device. It is an annular doped area formed by ion implantation or doping in the epitaxial layer 18. For detailed related content, please refer to the existing technology and will not be repeated here.

[0043] The following describes the process of forming N-type VDMOS in detail. Figures 3a to 3i The process flow for forming a P-type VDMOS is similar to the process flow for forming an N-type VDMOS, and will not be described one by one here.

[0044] S101, different masking layers are formed on the surface of the N- epitaxial layer 18 and ion implantation is performed. After a high temperature thermal process, a P-type well region 11 and an N+ source region 13 are formed accordingly. Figure 3a The N-epitaxial layer 18 can be formed on the substrate surface by an epitaxial process, or an epitaxial wafer with parameters that meet the requirements can be directly purchased commercially, which includes a stacked substrate and epitaxial layer.

[0045] S102, growing a pad oxide layer on the surface of the N- epitaxial layer 18 as a barrier layer, covering part of the N+ source region 13, etching the P-type well region 11 after patterning to form a groove 15, and then removing the pad oxide layer, see Figure 3b The groove 15 has a bilaterally symmetrical structure, and its depth cannot exceed the depth of the well region 11 , and its width cannot completely cover the source region 13 . In other words, through this etching, part of the original N+ source region 13 is also removed.

[0046] S103, depositing metal in the groove 15. The metal does not need to fill the entire groove 15. A deposition process commonly used in the semiconductor field can be used. Finally, the metal thickness at the bottom middle of the groove 15 is greater than the metal thickness on the surface of the N-type epitaxial layer. Figure 3c .

[0047] S104, wet-etching the deposited metal layer to remove the metal on the surface of the N-epitaxial layer 18 and part of the metal in the groove 15. The remaining metal in the groove 15 is used as the metal layer 19. The bottom surface of the metal layer 19 must be higher than the depletion region of the diode (PN junction) between the P-type well region 11 and the N-epitaxial layer 18, that is, the bottom surface of the metal layer 19 must be higher than the bottom surface of the P-type well region 11, and the highest point of the top of the metal layer 19 must be lower than the lowest point of the N+ source region 13. Figure 3d .

[0048] S105. Using vapor phase epitaxial growth, grow heavily doped P-type single crystal silicon in the groove 15. On the one hand, it replaces the P+ contact region formed by injection in the existing VDMOS process and continues the P-type well region. On the other hand, it maintains the correspondence with the original crystal orientation and reduces the distribution of defects. The lowest point of the surface-grown single crystal silicon needs to be higher than or flush with the surface of the N-epitaxial layer 18 so that the remaining single crystal silicon after subsequent chemical mechanical polishing (CMP) can fill the groove 15. Figure 3e .

[0049] S106, using chemical mechanical polishing to completely remove the P-type single crystal silicon on the surface of the N-epitaxial layer 18, thereby obtaining a relatively flat surface. Appropriate over-polishing can be performed to ensure the removal effect. Figure 3f .

[0050] S107, growing a dielectric layer such as a silicon oxide layer on the surface of the N-epitaxial layer 18, and then depositing doped polysilicon, see Figure 3g .

[0051] S108, perform patterning to remove the polysilicon and dielectric layer on the surface of the groove 15 and part of the N+ source region 13, and use the remaining dielectric layer as the gate dielectric layer 16 and the remaining polysilicon layer as the gate G. Figure 3h .

[0052] S109, depositing an insulating dielectric layer 14, patterning it after reflow, and forming contact holes, see Figure 3i .

[0053] S110, metal deposition and etching to form the source S, see Figure 2 .

[0054] Those skilled in the art will appreciate that subsequent processes include thinning the back of the N+ substrate and forming a back metal layer on the back of the N+ substrate to serve as a drain. These processes can refer to existing related technologies and will not be described in detail here.

[0055] When the VDMOS structure is obtained through this process in this embodiment, unlike the existing self-aligned process in which a high-temperature thermal process is performed on the P-type well region 11 and the N+ source region after the gate oxide layer and the heavily doped polycrystalline structure are formed, this structure directly forms the P-type well region 11 and the N+ source region by performing ion implantation and a high-temperature thermal process on the surface of the N-type epitaxial layer using patterned masking layers of different shapes, thereby effectively avoiding the problem of ion diffusion in the heavily doped polycrystalline during the high-temperature thermal process affecting the gate oxide reliability.

[0056] Based on the aforementioned power semiconductor device fabrication process and the description of the existing NMOS fabrication process, it can be seen that the VDMOS structure and power semiconductor device provided in this embodiment can be fabricated by simply improving upon the conventional fabrication process for existing power semiconductor devices. Furthermore, the newly added steps involved are all commonly used in existing semiconductor processes, without increasing the complexity of the process. Therefore, the VDMOS structure and power semiconductor device provided in this embodiment can be manufactured using existing semiconductor fabrication processes, facilitating practical promotion and application.

[0057] Thus far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art may make equivalent changes or substitutions to the relevant technical features, and the technical solutions after such changes or substitutions will fall within the scope of protection of the present invention.

Claims

1. A VDMOS structure, characterized in that: include: substrate; an epitaxial layer located on one side of the substrate, the epitaxial layer having a bottom surface facing the substrate and a top surface away from the substrate; a gate structure located on the top surface of the epitaxial layer, the gate structure comprising a gate dielectric layer and a gate layer stacked together; a well region in the epitaxial layer, the well region extending from the top surface of the epitaxial layer into the epitaxial layer, the bottom surface of the well region being located in the epitaxial layer, and the well region being located on both sides of the gate structure; a source region, a stacked doped region, and a metal layer located in the well region, wherein the source region and the doped region extend from the top surface of the epitaxial layer into the epitaxial layer respectively; along the width direction of the well region, the edge of the source region is tangent to the edge of the doped region; the metal layer is located between the doped region and the bottom surface of the well region, and the bottom surface of the metal layer is higher than the bottom surface of the well region; a drain located on the other side of the substrate; The substrate, the epitaxial layer and the source region are of a first doping type, the well region and the doping region are of a second doping type, and the first doping type and the second doping type are different.

2. The VDMOS structure according to claim 1, wherein: The depth of the source region is less than the depth of the doping region.

3. The VDMOS structure according to claim 1, wherein: The orthographic projection of the metal layer on the substrate surface coincides with the orthographic projection of the doped region on the substrate surface.

4. The VDMOS structure according to any one of claims 1 to 3, wherein: Along the depth direction of the well region, the highest point of the top surface of the metal layer is lower than the lowest point of the bottom surface of the source region.

5. The VDMOS structure according to any one of claims 1 to 3, wherein: The well region is a doped silicon region, the doped region is a doped silicon region, and the doping concentration of the doped region is greater than the doping concentration of the well region.

6. The VDMOS structure according to any one of claims 1 to 3, wherein: The first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.

7. A power semiconductor device, characterized in that: The device comprises a plurality of cells, each cell comprising the VDMOS structure according to any one of claims 1 to 6, wherein the source regions in the plurality of cells are electrically connected together, and the drain regions in the plurality of cells are electrically connected together.

8. The power semiconductor device according to claim 7, characterized in that: It also includes a plurality of terminal rings arranged at intervals, wherein the innermost terminal ring defines an active area, and the plurality of cells are located in the active area.

9. The power semiconductor device according to claim 8, characterized in that: The depth of the innermost terminal ring is greater than or equal to the depth of the well region.

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