Current sampling integrated chip, overcurrent protection circuit thereof, constant current control loop circuit and electronic equipment

Abstract

The utility model provides a current sampling integrated chip, an overcurrent protection circuit, a constant current control loop circuit and an electronic device, a packaging structure comprises N bonding wires, a sampling pin and a grounding pin, a first end of each bonding wire is coupled to the sampling pin, and a second end of each bonding wire is coupled to the grounding pin; the chip structure is arranged in the packaging structure, and the chip structure comprises a current sampling module which is used for obtaining the voltage difference between the sampling pin and the grounding pin when the sampling pin has a current signal, so as to obtain the information of the current flowing through the N bonding wires. Therefore, the impedance generated by the bonding wire connected between the two pins is used as the sampling resistance, the cost is lower, the resistance is smaller, the cost of current sampling in an integrated circuit is reduced, and the efficiency of the circuit is improved.

Description

Technical Field

[0001] The utility model relates to the field of power electronics, in particular to a current sampling integrated chip, an overcurrent protection circuit, a constant current control loop circuit and electronic equipment. Background Art

[0002] With the rapid popularization of high-power fast charging technology, the current charged into the device is getting larger and larger. Since the current flowing through the sampling resistor will generate heat, if the rated power of the sampling resistor is exceeded, the resistor will burn out. Therefore, the current current sampling circuit usually uses smaller sampling resistors, such as 5mΩ resistors or 10mΩ resistors. Although these resistors have higher precision and smaller temperature coefficients, the sampled signals are more accurate, but these resistors are expensive and occupy space outside the chip in the integrated circuit.

[0003] Therefore, how to reduce the cost of current sampling in integrated circuits and improve circuit efficiency has become a technical problem that the industry urgently needs to solve. Utility Model Content

[0004] The utility model provides a current sampling integrated chip, an overcurrent protection circuit, a constant current control loop circuit and electronic equipment, which solves the technical problem of how to reduce the cost of current sampling in an integrated circuit and improve the efficiency of the circuit.

[0005] According to a first aspect of the present invention, an embodiment of the present invention provides a current sampling integrated chip, comprising:

[0006] A packaging structure comprising N bonding wires, a sampling pin, and a ground pin, wherein a first end of each bonding wire is coupled to the sampling pin, and a second end thereof is coupled to the ground pin, and N is a positive integer;

[0007] The chip structure is provided in the package structure and includes:

[0008] The current sampling module is coupled to the sampling pin and the ground pin respectively.

[0009] Optionally, the current sampling module includes a first amplifier, a first resistor, a second resistor, a third resistor and a first transistor;

[0010] The non-inverting input terminal of the first amplifier is coupled to the sampling pin through the first resistor, the inverting input terminal of the first amplifier is coupled to the ground pin through the second resistor, and the output terminal of the first amplifier is coupled to the control terminal of the first transistor. The first terminal of the first transistor is coupled to the non-inverting input terminal of the first amplifier, and the second terminal of the first transistor is grounded through the third resistor. The second terminal of the first transistor is also used to output a sampling voltage, and the sampling voltage includes current information flowing through the N wires.

[0011] Optionally, the first amplifier is a chopper amplifier.

[0012] Optionally, the chip structure further includes a temperature compensation module for outputting a first reference voltage, wherein the temperature coefficient of the first reference voltage is the same as the temperature coefficient of the bonding wire.

[0013] Optionally, the temperature compensation module includes:

[0014] a PTAT voltage generating unit configured to output a PTAT voltage;

[0015] A second reference voltage generating unit is configured to output a second reference voltage based on the PTAT voltage, wherein the second reference voltage is a zero temperature coefficient reference voltage;

[0016] a bias current generating unit configured to output a bias current based on the second reference voltage, wherein the bias current is a current with a zero temperature coefficient;

[0017] The temperature compensation unit is configured to output the first reference voltage based on the PTAT voltage and the bias current.

[0018] According to a second aspect of the present invention, an embodiment of the present invention provides an overcurrent protection circuit for a current sampling integrated chip;

[0019] The device receives an input voltage through a switch, and a ground terminal of the device is coupled to the sampling pin;

[0020] The chip structure also includes an overcurrent detection module, the first input terminal and the second input terminal of the overcurrent detection module respectively receive the first reference voltage and the sampling voltage, and the overcurrent detection module is coupled to the control terminal of the switch through the power supply control pin of the packaging structure.

[0021] Optionally, the overcurrent detection module includes a second amplifier;

[0022] A first input terminal of the second amplifier receives the sampling voltage, a second input terminal thereof receives the first reference voltage, and an output terminal thereof is coupled to the control terminal of the switch.

[0023] According to a third aspect of the present invention, an embodiment of the present invention provides a constant current control loop circuit of a current sampling integrated chip, wherein the chip structure further includes:

[0024] a comparison module, configured to compare the voltage value of the sampled voltage with the voltage value of the first reference voltage, and output a first signal;

[0025] A constant current source circuit, configured to output a first current;

[0026] The loop control module is coupled to the comparison module and the constant current source circuit respectively.

[0027] Optionally, the comparison module includes a third amplifier;

[0028] A first input terminal of the third amplifier receives the sampled voltage, a second input terminal thereof receives the first reference voltage, and an output terminal thereof is coupled to the first terminal of the loop control module.

[0029] Optionally, the chip structure further includes a compensation module, a first end of the compensation module is coupled to the second end of the loop control module, and a second end of the compensation module is coupled to the first input end of the third amplifier.

[0030] According to a third aspect of the present invention, an embodiment of the present invention provides an electronic device, comprising: a current sampling integrated chip as described in any one of the first aspects of the present invention.

[0031] Compared with the prior art, the technical solution of the embodiment of the utility model has the following beneficial effects:

[0032] The current sampling integrated chip, overcurrent protection circuit, constant current control loop circuit, and electronic device of the present invention have a package structure comprising N bonding wires, a sampling pin, and a ground pin. The first end of each bonding wire is coupled to the sampling pin, and the second end thereof is coupled to the ground pin. The chip structure is disposed within the package structure and includes a current sampling module for obtaining the voltage difference between the sampling pin and the ground pin when a current signal is present at the sampling pin, thereby obtaining information on the current flowing through the N bonding wires. Thus, the present invention utilizes the impedance generated by the bonding wire connecting the two pins as a sampling resistor, resulting in lower cost and lower resistance, thereby reducing the cost of current sampling in the integrated circuit and improving circuit efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 This is a schematic diagram of the structure of a high-end current sampling circuit in an embodiment of the prior art;

[0035] Figure 2 This is a schematic diagram of the structure of a low-end current sampling circuit in an embodiment of the prior art;

[0036] Figure 3 This is a schematic diagram of the structure of the current sampling integrated chip in one embodiment of the utility model. Figure 1 ;

[0037] Figure 4 This is a structural diagram of a current sampling module in one embodiment of the present utility model;

[0038] Figure 5 This is a schematic diagram of the structure of the current sampling integrated chip in one embodiment of the utility model. Figure 2 ;

[0039] Figure 6 This is a schematic diagram of the structure of the temperature compensation module in one embodiment of the present invention. Figure 1 ;

[0040] Figure 7 This is a schematic diagram of the structure of the temperature compensation module in one embodiment of the present invention. Figure 2 ;

[0041] Figure 8 1 is a schematic structural diagram of a bias current generating unit in one embodiment of the present utility model;

[0042] Figure 9 is a graph showing the first reference voltage changing with temperature in one embodiment of the present invention;

[0043] Figure 10 This is a schematic structural diagram of an overcurrent protection circuit in one embodiment of the present utility model;

[0044] Figure 11 This is a schematic structural diagram of a second amplifier in one embodiment of the present utility model;

[0045] Figure 12 This is a schematic structural diagram of a constant current control loop circuit in one embodiment of the present utility model;

[0046] Description of reference numerals:

[0047] 1-first power supply terminal;

[0048] 2-First device end;

[0049] 3- Second power supply terminal;

[0050] 4- Second device end;

[0051] RSEN1-first sampling resistor;

[0052] RSEN2-second sampling resistor;

[0053] 10- packaging structure;

[0054] 101-N wires;

[0055] 20- chip structure;

[0056] 201-current sampling module;

[0057] 2011-First Amplifier;

[0058] 202-temperature compensation module;

[0059] 2021-PTAT voltage generation unit;

[0060] 2022-a second reference voltage generating unit;

[0061] 2023- bias current generating unit;

[0062] 20231-4th amplifier;

[0063] 2024-temperature compensation unit;

[0064] 203-overcurrent detection module;

[0065] 2031 - second amplifier;

[0066] 204-Comparison module;

[0067] 2041-third amplifier;

[0068] 205-constant current source circuit;

[0069] 206-loop control module;

[0070] 207-compensation module;

[0071] 30-Equipment;

[0072] ISEN-sampling pin;

[0073] GND-ground pin;

[0074] R1-first resistor;

[0075] R2-second resistor;

[0076] R3-the third resistor;

[0077] R4-fourth resistor;

[0078] R5-fifth resistor;

[0079] R6-sixth resistor;

[0080] R7-seventh resistor;

[0081] R8-eighth resistor;

[0082] Q1 - first transistor;

[0083] Q2 - second transistor;

[0084] Q3-switch;

[0085] C1-first capacitor;

[0086] PM1-first PMOS tube;

[0087] PM2-second PMOS tube;

[0088] PM3-the third PMOS tube;

[0089] PM4-fourth PMOS tube;

[0090] PM5-fifth PMOS tube;

[0091] PM6-sixth PMOS tube;

[0092] NPN1-first NPN transistor;

[0093] NPN2-second NPN transistor;

[0094] NM1-first NMOS tube;

[0095] NM2-second NMOS tube;

[0096] NM3-third NMOS tube;

[0097] VREF_CC-first reference voltage;

[0098] VBG-second reference voltage;

[0099] I0 - bias current. DETAILED DESCRIPTION

[0100] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0101] The terms "first," "second," "third," "fourth," and so on (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0102] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0103] As described in the background art, reducing the cost of current sampling and improving circuit efficiency in integrated circuits has become a technical problem that the industry urgently needs to solve. This will be described in detail below with reference to the accompanying drawings.

[0104] Please refer to Figure 1 , Figure 1 The figure shows a common high-end current sampling circuit in an integrated circuit, comprising a first power supply terminal 1, a first sampling resistor RSEN1 and a first device terminal 2;

[0105] The first power supply terminal 1 is connected to the power supply terminal of the first device terminal 2 through the first sampling resistor RSEN1 , and the current value of the power supply current output by the first power supply terminal 1 can be obtained by detecting the voltage across the first sampling resistor RSEN1 .

[0106] Please refer to Figure 2 , Figure 2 The diagram shows a common low-end current sampling circuit in an integrated circuit, including a second power supply terminal 3, a second sampling resistor RSEN2, and a second device terminal 4;

[0107] The second power supply terminal 3 is connected to the power supply terminal of the second device terminal 4 , and the ground terminal of the second device terminal 43 is coupled to the second sampling resistor RSEN2 .

[0108] exist Figure 2 In the example, the power supply terminal provides a power supply voltage for the power supply terminal of the second device terminal 4, and the current is coupled to the second sampling resistor RSEN2 through the ground terminal of the first device terminal 2. Similarly, Figure 2In the example of , the circuit can obtain the current value of the power supply current output by the power supply end by detecting the voltage across the sampling resistor.

[0109] Since current flowing through a sampling resistor generates heat, exceeding the rated power of the sampling resistor can cause the resistor to burn out. Therefore, current current sampling circuits typically use smaller sampling resistors, such as 5mΩ or 10mΩ resistors. Although these resistors have high precision and a small temperature coefficient, and the sampled signals are more accurate, they still generate heat when the current is high, reducing circuit efficiency. In addition, these resistors are expensive and occupy space outside the chip in the integrated circuit.

[0110] In light of this, the present invention provides a current sampling integrated chip, the package structure of which includes N bonding wires, a sampling pin, and a ground pin. Each bonding wire has a first end coupled to the sampling pin and a second end coupled to the ground pin. The chip structure is disposed within the package structure and includes a current sampling module for obtaining a voltage difference between the sampling pin and the ground pin when a current signal is present at the sampling pin, thereby obtaining information about the current flowing through the N bonding wires. Thus, the present invention utilizes the impedance generated by the bonding wire connecting two pins as a sampling resistor, resulting in lower cost and resistance, thereby reducing the cost of current sampling in integrated circuits and improving circuit efficiency.

[0111] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0112] Please refer to Figure 3 , Figure 3 The current sampling integrated chip of the embodiment of the utility model comprises:

[0113] The package structure 10 includes N bonding wires 101, a sampling pin ISEN, and a ground pin GND. A first end of each bonding wire is coupled to the sampling pin ISEN, and a second end thereof is coupled to the ground pin GND. N is a positive integer.

[0114] The chip structure 20 is disposed in the package structure 10 and includes:

[0115] The current sampling module 201 is coupled to the sampling pin ISEN and the ground pin GND respectively.

[0116] Among them, the N bonding wires 101 can be regarded as an equivalent resistor. The cost of the bonding wires is low. Therefore, the N bonding wires 101 of the present invention can reduce the cost of current sampling in the integrated circuit and improve the efficiency of the circuit. When calculating the equivalent resistance, the impedance of each wire can be evaluated based on the actual wire length and wire diameter of the bonding wire, which is RΩ. Then, the total bonding wire impedance R / NΩ of the N bonding wires 101 is obtained. This impedance is much smaller than the resistance value of conventional precision resistors and is particularly suitable for application in high-power fast charging technology.

[0117] The current sampling module 201 can sample the current flowing through the sampling pin ISEN and the ground pin GND based on the equivalent resistance. Specifically, when a current signal is present at the sampling pin ISEN, the current sampling module 201 is configured to sample the voltage difference between the sampling pin ISEN and the ground pin GND to obtain current information I=ΔV / (R / N) flowing through the N bonding wires.

[0118] exist Figure 3 In the example, the two input terminals of the current sampling module 201 are coupled to the sampling pin ISEN and the ground pin GND respectively through bonding wires. These two bonding wires can be regarded as auxiliary bonding wires. The auxiliary bonding wires are mainly used to provide a signal path. This is because the total bonding impedance of the N bonding wires 101 is much smaller than the impedance of the auxiliary bonding wires. The path where the auxiliary bonding wires are located can be approximately regarded as a break.

[0119] In one embodiment, please refer to Figure 4 , Figure 4 1 shows a structural diagram of the current sampling module 201, which includes a first amplifier 2011, a first resistor R1, a second resistor R2, a third resistor R3 and a first transistor Q1;

[0120] The non-inverting input terminal of the first amplifier 2011 is coupled to the sampling pin ISEN through the first resistor R1, the inverting input terminal thereof is coupled to the ground pin GND through the second resistor R2, and the output terminal thereof is coupled to the control terminal of the first transistor Q1. The first terminal of the first transistor Q1 is coupled to the non-inverting input terminal of the first amplifier 2011, and the second terminal of the first transistor Q1 is grounded through the third resistor R3. The second terminal of the first transistor Q1 is also used to output a sampling voltage, and the sampling voltage includes current information ISENSE flowing through the N wires.

[0121] exist Figure 4 In the example, the first transistor Q1 is a PMOS transistor, but the present invention is not limited thereto and may also be a triode, etc. Those skilled in the art may select a suitable switch type as needed.

[0122] exist Figure 4 In the example, if the resistance of the first resistor R1 is the same as the resistance of the second resistor R2, the current ISENSE flowing through the N bonding wires is equal to ΔV* R3 / R1.

[0123] Since a general amplifier has a large offset voltage, which may cause a high deviation in the sampling output, in a preferred embodiment, the first amplifier 2011 is a chopper amplifier (Chop OP).

[0124] Generally, the bonding wire has a certain temperature coefficient. As the temperature rises, its internal resistance increases. In this case, the sampled current value ISENSE obtained in the current sampling module 201 cannot be directly applied to the subsequent circuit. It is necessary to compensate for the temperature coefficient of the bonding wire. The present invention is further explained by taking the bonding wire made of copper as an example:

[0125] Taking the copper wire as an example, the copper wire has a positive temperature coefficient α=0.00393. As the temperature rises, its internal resistance increases. At high temperatures, the internal resistance of the copper wire

[0126]

[0127] in, is the resistance of the copper wire at a specific ambient temperature, T is the current temperature, and T0 is the specific ambient temperature value.

[0128] For example, the specific ambient temperature is typically 25°C. At a current temperature of 125°C, the internal resistance of the copper wire increases by 39.3%. To compensate for this temperature coefficient, the reference voltage of the subsequent circuit is created to have the same temperature coefficient as the copper wire resistance, thereby compensating for the increase in current sampling values ​​as the temperature rises.

[0129] In one embodiment, please refer to Figure 5 The chip structure 20 further includes a temperature compensation module 202 for outputting a first reference voltage, wherein the temperature coefficient of the first reference voltage is the same as the temperature coefficient of the bonding wire.

[0130] In a specific implementation, please refer to Figure 6 , the temperature compensation module 202 includes:

[0131] The PTAT voltage generating unit 2021 is configured to output a PTAT voltage;

[0132] A second reference voltage VBG generating unit 2022 is configured to output a second reference voltage VBG based on the PTAT voltage, wherein the second reference voltage VBG is a zero temperature coefficient reference voltage;

[0133] The bias current generating unit 2023 is configured to output a bias current I0 based on the second reference voltage VBG, wherein the bias current I0 is a current with a zero temperature coefficient;

[0134] The temperature compensation unit 2024 is configured to output the first reference voltage VREF_CC based on the PTAT voltage and the bias current I0.

[0135] As an example, see Figure 7 The PTAT voltage generating unit 2021 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a first NPN transistor NPN1, a second NPN transistor NPN2, a fourth resistor R4 and a fifth resistor R5;

[0136] The source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are both coupled to the power supply voltage, the gate of the second PMOS transistor PM2 is coupled to the gate of the first PMOS transistor PM1 and the drain of the first PMOS transistor PM1, respectively, the drain of the second PMOS transistor PM2 is coupled to the collector of the second NPN transistor NPN2, the emitter of the second NPN transistor NPN2 is coupled to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is grounded GND through the fifth resistor R5, the drain of the first PMOS transistor PM1 is coupled to the collector of the first NPN transistor NPN1, the emitter of the first NPN transistor NPN1 is coupled to the second end of the fourth resistor R4, and the base of the first NPN transistor NPN1 is coupled to the base of the second NPN transistor NPN2.

[0137] The emitter area of ​​the first NPN transistor NPN1 is different from the emitter area of ​​the second NPN transistor NPN2. Figure 7 In the example, the ratio is 1:8. The V BE With the second NPN transistor NPN2's V BE The difference (ΔV BE ) is the PTAT voltage (i.e. positive temperature coefficient voltage):

[0138] exist Figure 7 In the example, the PTAT voltage is reflected by the voltage drop across the fourth resistor R4, that is, the voltage difference across the fourth resistor R4 is ΔV BE , the current I flowing through the second PMOS transistor PM2 PTAT =ΔV BE / R4.

[0139] On this basis, please continue to refer to Figure 7 In one embodiment, the second reference voltage VBG generating unit 2022 includes a third PMOS transistor PM3, a fourth PMOS transistor PM4, a sixth resistor R6, a seventh resistor R7, a first capacitor C1, a first NMOS transistor NM1, a second NMOS transistor NM2, and a third NMOS transistor NM3;

[0140] The source of the third PMOS transistor PM3 and the source of the fourth PMOS transistor PM4 are both coupled to the power supply voltage, the gate of the third PMOS transistor PM3 is coupled to the gate of the second PMOS transistor PM2, the source of the third PMOS transistor PM3 is coupled to the drain of the first NMOS transistor NM1, the source of the first NMOS transistor NM1 is grounded GND, and the gate of the first NMOS transistor NM1 is coupled to the drain of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2, respectively;

[0141] The gate of the fourth PMOS transistor PM4 is sequentially coupled to the drain of the second PMOS transistor PM2 via the first capacitor C1 and the sixth resistor R6. The drain of the fourth PMOS transistor PM4 is respectively coupled to the drain of the second NMOS transistor NM2 and the gate of the third NMOS transistor NM3. The source of the first NMOS transistor NM1 is grounded GND.

[0142] The drain of the third NMOS transistor NM3 is coupled to the power supply voltage, the source of the third NMOS transistor NM3 is coupled to the base of the second NPN transistor NPN2, the source of the third NMOS transistor NM3 is also connected to the ground GND through the seventh resistor R7, and the source of the third NMOS transistor NM3 is also used to output the second reference voltage VBG.

[0143] Please continue to refer to Figure 8 In one embodiment, the bias current generating unit 2023 includes a fourth amplifier 20231, an eighth resistor R8, a second transistor Q2, a fifth PMOS transistor PM5, and a sixth PMOS transistor PM6;

[0144] The non-inverting input terminal of the fourth amplifier 20231 receives the second reference voltage VBG, the inverting input terminal thereof is coupled to the first terminal of the eighth resistor R8, the output terminal thereof is coupled to the gate of the second transistor Q2, the second terminal of the second transistor Q2 is coupled to the first terminal of the eighth resistor R8, the second terminal of the eighth resistor R8 is grounded GND, the first terminal of the second transistor Q2 is respectively coupled to the drain of the fifth PMOS transistor PM5 and the gate of the fifth PMOS transistor PM5, the source of the fifth PMOS transistor PM5 and the source of the sixth PMOS transistor PM6 are both coupled to the power supply voltage, the gate of the sixth PMOS transistor PM6 is coupled to the gate of the fifth PMOS transistor PM5, and the drain of the sixth PMOS transistor PM6 outputs the bias current I0.

[0145] exist Figure 8 In the example, the second transistor Q2 is a PMOS transistor, but can also be a triode. Those skilled in the art can select a suitable transistor as needed.

[0146] The temperature compensation unit 2024 outputs the first reference voltage VREF_CC based on the PTAT voltage and the bias current I0. In one embodiment, please continue to refer to Figure 7 The temperature compensation unit 2024 includes a seventh PMOS transistor PM7, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5 and a ninth resistor R9;

[0147] The drain and gate of the fourth NMOS transistor NM4 both receive the bias current I0. The gate of the fourth NMOS transistor NM4 is also coupled to the gate of the fifth NMOS transistor NM5. The source of the fourth NMOS transistor NM4 and the source of the fifth NMOS transistor NM5 are both grounded to GND. The drain of the fifth NMOS transistor NM5 is coupled to the drain of the seventh PMOS transistor PM7. The source of the seventh PMOS transistor PM7 is coupled to the power supply voltage, and the gate of the seventh PMOS transistor PM7 is coupled to the gate of the second PMOS transistor PM2. The drain of the seventh PMOS transistor PM7 is also grounded to GND via the ninth resistor R9. The drain of the seventh PMOS transistor PM7 is used to output the first reference voltage VREF_CC.

[0148] The seventh PMOS transistor PM7 mirrors the current I flowing through the second PMOS transistor PM2. PTAT , its mirror ratio is 1:K1, then the current flowing through the seventh PMOS tube PM7 is K1*ΔV BE / R4;

[0149] The ratio of the fourth NMOS transistor NM4 to the fifth NMOS transistor NM5 is 1:K2, and the current I flowing through the ninth resistor R9 is R9 =K1*ΔV BE / R4-I0*K2;

[0150] Since ΔV BE is a positive temperature coefficient voltage. The present invention can obtain currents with different positive temperature coefficients by adjusting the values ​​of K1 and K2. When the current passes through the zero temperature coefficient resistor R9, the first reference voltage VREF_CC with a positive temperature coefficient can be obtained.

[0151] Now combined Figure 9 For further explanation, Figure 9 A curve chart showing the change of the first reference voltage VREF_CC with temperature shows that the voltage value of the first reference voltage VREF_CC increases with increasing temperature. In actual use, it can be used as a reference voltage with the same temperature coefficient as the wire bonding to compensate for the problem of the current sampling value increasing when the temperature rises.

[0152] It should be understood that in the embodiment provided by the present invention, the temperature compensation module 202 is coupled to a subsequent circuit that needs to be applied to the sampled current value, but the present invention is not limited to this. Those skilled in the art can select a suitable temperature compensation method as needed. As long as the impedance generated by the wire connecting the two pins is used as the sampling resistor, it does not deviate from the protection scope of the present invention.

[0153] In addition, please refer to Figure 10 , the embodiment of the present utility model further provides an overcurrent protection circuit of a current sampling integrated chip including the above-mentioned temperature compensation module 202;

[0154] The device 30 receives an input voltage VIN through a switch Q3 , and a ground terminal of the device is coupled to the sampling pin ISEN;

[0155] The chip structure 20 further includes an overcurrent detection module 203, wherein a first input terminal and a second input terminal of the overcurrent detection module receive the first reference voltage VREF_CC and the sampling voltage respectively, and the overcurrent detection module is coupled to the control terminal of the switch Q3 through the power supply control pin CONTROL of the package structure.

[0156] The overcurrent detection module is configured to compare the first reference voltage VREF_CC and the sampling voltage, and output a switch control signal according to the comparison result, so as to disconnect the switch Q3 when an overcurrent occurs in the device 30 .

[0157] In this case, the first reference voltage VREF_CC may also correspond to an overcurrent threshold voltage. For a specific implementation, please refer to Figure 11 , the overcurrent detection module 203 includes a second amplifier 2031;

[0158] A first input terminal of the second amplifier 2031 receives the sampling voltage, a second input terminal thereof receives the first reference voltage VREF_CC, and an output terminal thereof is coupled to the control terminal of the switch.

[0159] In addition, please refer to Figure 12 The present invention also provides a constant current control loop circuit of a current sampling integrated chip including the temperature compensation module 202. The chip structure 20 further includes:

[0160] a comparing module 204 for comparing the voltage value of the sampled voltage with the voltage value of the first reference voltage VREF_CC and outputting a first signal;

[0161] A constant current source circuit 205, configured to output a first current;

[0162] The loop control module 206 is coupled to the comparison module 204 and the constant current source circuit 205 .

[0163] exist Figure 12 In the example, the comparison module 204 includes a third amplifier 2041;

[0164] A first input terminal of the third amplifier 2041 receives the sampled voltage, a second input terminal thereof receives the first reference voltage VREF_CC, and an output terminal thereof is coupled to a first terminal of the loop control module 206 .

[0165] In a preferred embodiment, please refer to Figure 12 The chip structure 20 further includes a compensation module 207 , a first end of the compensation module 207 is coupled to the second end of the loop control module 206 , and a second end thereof is coupled to the first input end of the third amplifier 2041 .

[0166] In addition, an embodiment of the present invention further provides an electronic device including the above-mentioned current sampling integrated chip. For example, the electronic device can be a fast charging plug, a communication device, etc., and the present invention is not limited to this.

[0167] In summary, the package structure of the present invention includes N bonding wires, a sampling pin, and a ground pin. Each bonding wire has a first end coupled to the sampling pin and a second end coupled to the ground pin. A chip structure is disposed within the package structure and includes a current sampling module for obtaining the voltage difference between the sampling pin and the ground pin when a current signal is present at the sampling pin, thereby obtaining information about the current flowing through the N bonding wires. Consequently, the present invention utilizes the impedance generated by the bonding wire connecting two pins as a sampling resistor, resulting in lower cost and resistance, thereby reducing the cost of current sampling in integrated circuits and improving circuit efficiency.

[0168] Although the present invention is disclosed as above, it is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined by the claims.

Claims

1. A current sampling integrated chip, characterized in that: include: A packaging structure comprising N bonding wires, a sampling pin, and a ground pin, wherein a first end of each bonding wire is coupled to the sampling pin, and a second end thereof is coupled to the ground pin, and N is a positive integer; The chip structure is provided in the package structure and includes: The current sampling module is coupled to the sampling pin and the ground pin respectively.

2. The current sampling integrated chip according to claim 1, characterized in that: The current sampling module includes a first amplifier, a first resistor, a second resistor, a third resistor and a first transistor; The non-inverting input terminal of the first amplifier is coupled to the sampling pin through the first resistor, the inverting input terminal of the first amplifier is coupled to the ground pin through the second resistor, and the output terminal of the first amplifier is coupled to the control terminal of the first transistor. The first terminal of the first transistor is coupled to the non-inverting input terminal of the first amplifier, and the second terminal of the first transistor is grounded through the third resistor. The second terminal of the first transistor is also used to output a sampling voltage, and the sampling voltage includes current information flowing through the N wires.

3. The current sampling integrated chip according to claim 2, characterized in that: The first amplifier is a chopper amplifier.

4. The current sampling integrated chip according to claim 2, wherein: The chip structure further includes a temperature compensation module for outputting a first reference voltage, wherein the temperature coefficient of the first reference voltage is the same as the temperature coefficient of the bonding wire.

5. The current sampling integrated chip according to claim 4, characterized in that: The temperature compensation module includes: a PTAT voltage generating unit configured to output a PTAT voltage; A second reference voltage generating unit is configured to output a second reference voltage based on the PTAT voltage, wherein the second reference voltage is a zero temperature coefficient reference voltage; a bias current generating unit configured to output a bias current based on the second reference voltage, wherein the bias current is a current with a zero temperature coefficient; The temperature compensation unit is configured to output the first reference voltage based on the PTAT voltage and the bias current.

6. An overcurrent protection circuit for a current sampling integrated chip according to any one of claims 4 to 5, characterized in that ； The device receives an input voltage through a switch, and a ground terminal of the device is coupled to the sampling pin; The chip structure also includes an overcurrent detection module, the first input terminal and the second input terminal of the overcurrent detection module respectively receive the first reference voltage and the sampling voltage, and the overcurrent detection module is coupled to the control terminal of the switch through the power supply control pin of the packaging structure.

7. The overcurrent protection circuit according to claim 6, wherein: The overcurrent detection module includes a second amplifier; A first input terminal of the second amplifier receives the sampling voltage, a second input terminal thereof receives the first reference voltage, and an output terminal thereof is coupled to the control terminal of the switch.

8. A constant current control loop circuit of a current sampling integrated chip according to any one of claims 4 to 5, characterized in that: The chip structure further includes: a comparison module, configured to compare the voltage value of the sampled voltage with the voltage value of the first reference voltage, and output a first signal; A constant current source circuit, configured to output a first current; The loop control module is coupled to the comparison module and the constant current source circuit respectively.

9. The constant current control loop circuit according to claim 8, wherein: The comparison module includes a third amplifier; A first input terminal of the third amplifier receives the sampled voltage, a second input terminal thereof receives the first reference voltage, and an output terminal thereof is coupled to the first terminal of the loop control module.

10. The constant current control loop circuit according to claim 9, wherein: The chip structure further includes a compensation module, a first end of the compensation module is coupled to the second end of the loop control module, and a second end of the compensation module is coupled to the first input end of the third amplifier.

11. An electronic device, characterized in that: include: The current sampling integrated chip according to any one of claims 1 to 5.

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