Power supply anti-reverse connection protection circuit

Abstract

The utility model discloses a power supply anti-reverse connection protection circuit. The circuit comprises a field effect transistor and a booster circuit, the field effect transistor comprises an NMOS field effect transistor and a PMOS field effect transistor. And the NMOS field effect transistor and the PMOS field effect transistor are in line connection with the booster circuit to form a circuit with a power supply anti-reverse connection protection function. The circuit can be protected when the power supply is reversely connected, the field effect transistor has low conduction loss, and the working efficiency of the circuit can be improved.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic circuits, in particular to a power supply reverse connection protection circuit. Background Art

[0002] In the field of electronic circuit technology, a DC power supply reverse polarity protection circuit is often used. Usually, a diode is connected in series with the positive line of the power supply for reverse polarity protection. The conduction loss and heat generation of the diode are large, which will reduce the conversion efficiency of the power supply. Especially in low-power applications, it is difficult to meet the usage requirements. Utility Model Content

[0003] The purpose of the utility model is to provide a power supply reverse connection protection circuit to achieve reverse connection protection of the power supply and improve the working efficiency of the circuit.

[0004] In order to achieve the above purpose, the technical solution adopted by the utility model is:

[0005] A power supply reverse connection protection circuit comprises a power supply input terminal, a field effect tube, a boost circuit and a power supply output terminal; the field effect tube is divided into an NMOS field effect tube and a PMOS field effect tube.

[0006] Preferably, the power supply input terminal, the source of the NMOS field effect tube and the drain of the PMOS field effect tube are connected together; the gate of the PMOS field effect tube is grounded; the gate of the NMOS field effect tube is connected to the power output terminal of the boost circuit; the drain of the NMOS field effect tube, the source of the PMOS field effect tube and the power input terminal of the boost circuit are connected together.

[0007] Preferably, the voltage at the power output terminal is greater than the voltage at the power supply input terminal, and the difference between the two voltages is greater than the turn-on voltage of the NMOS field effect transistor.

[0008] Preferably, the voltage at the power supply input terminal is greater than the turn-on voltage of the PMOS field effect transistor.

[0009] Preferably, the power supply input terminal, the PMOS field effect transistor, the boost circuit and the power ground to which the power output terminal is connected are connected together.

[0010] Preferably, the boost circuit further includes a boost module and a boost device.

[0011] The beneficial effects of the present invention are as follows: when the power supply is reversely connected, both field-effect transistors are non-conductive, thereby protecting the subsequent boost circuit; when the power supply is positively connected, the voltage reaches the power input terminal of the boost circuit through the parasitic diodes inside the two field-effect transistors, thereby further turning on the PMOS field-effect transistor, and the power supply voltage output by the boost circuit after operation further turns on the NMOS transistor. Since the on-resistance of the two field-effect transistors is low, the on-resistance of the two field-effect transistors after being connected in parallel is further reduced, thereby reducing the power consumption of the circuit and improving the conversion efficiency of the power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is the power supply reverse polarity protection circuit diagram;

[0013] In the figure, Vin is the positive input terminal of the power supply; Q1 is an NMOS field-effect transistor; Q2 is a PMOS field-effect transistor; GND is the power ground; Vcc is the positive input terminal of the boost circuit 1; boost circuit 1 is the boost circuit; Vout is the positive output terminal of the power supply. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0015] A power supply anti-reverse connection protection circuit, such as Figure 1 As shown, it includes a power supply positive input terminal Vin, an NMOS field effect transistor Q1, a PMOS field effect transistor Q2, a boost circuit 1 power supply positive input terminal Vcc, a boost circuit 1 and a power supply positive output terminal Vout.

[0016] In the above-mentioned power supply reverse connection protection circuit, the positive input terminal Vin of the power supply, the source S of the NMOS field-effect transistor Q1, and the drain D of the PMOS field-effect transistor Q2 are connected together; the gate G of the PMOS field-effect transistor Q2 is grounded; the gate G of the NMOS field-effect transistor Q1 is connected to the positive output terminal Vout of the power supply; the drain D of the NMOS field-effect transistor Q1, the source S of the PMOS field-effect transistor Q2, and the positive power input terminal Vcc of the boost circuit 1 are connected together; and the power ground of the entire circuit is commonly connected.

[0017] Working principle of the circuit:

[0018] When the power supply is connected reversely, Vin is connected to the negative pole of the power supply and GND is connected to the positive pole of the power supply. At this time, the parasitic diodes of the NMOS field-effect transistor Q1 and the PMOS field-effect transistor Q2 are not conducting, the gate G voltage of the NMOS field-effect transistor will not be greater than the source S voltage, and the source S voltage of the PMOS field-effect transistor will not be greater than the gate G voltage. Therefore, both the NMOS field-effect transistor and the PMOS field-effect transistor are not conducting, and the boost circuit 1 does not work, thereby realizing the reverse power supply protection function.

[0019] When the power supply is connected to the positive terminal (Vin) and the negative terminal (GND), the parasitic diodes of the NMOS field-effect transistor (Q1) and the PMOS field-effect transistor (Q2) conduct. The positive power input terminal (Vcc) of the boost circuit 1 is then connected to the power supply. The voltage at the source (S) of the PMOS field-effect transistor (FET) is greater than the voltage at the gate (G), causing the PMOS field-effect transistor to conduct and further provide voltage for Vcc. When the boost circuit 1 begins operating, the output voltage (Vout) is greater than the voltage of the power supply (Vin). This means that the voltage at the gate (G) of the NMOS field-effect transistor (FET) is greater than the voltage at the source (S), causing the NMOS field-effect transistor to conduct and also provide voltage for Vcc. Because the on-resistance of a single field-effect transistor is relatively small, when both the NMOS field-effect transistor and the PMOS field-effect transistor are turned on simultaneously, their on-resistances are in parallel, reducing the overall on-resistance. This reduces conduction losses and improves the efficiency of the entire circuit.

[0020] When one of the NMOS field effect transistor and the PMOS field effect transistor fails, the power supply can still supply power to the boost circuit 1 through the other MOS transistor, thereby ensuring the normal operation of the boost circuit 1 and improving the reliability of the circuit.

[0021] The above description is only a preferred embodiment of the present invention. It should be noted that the boost modules and boost devices that may be selected from the boost circuit 1 should also be considered within the scope of protection of the present invention.

Claims

1. A power supply reverse connection protection circuit, characterized in that: It includes a power supply input terminal, a field effect transistor, a boost circuit and a power supply output terminal; The field effect tube is divided into NMOS field effect tube and PMOS field effect tube; The power supply input terminal, the source of the NMOS field-effect transistor and the drain of the PMOS field-effect transistor are connected together; the gate of the PMOS field-effect transistor is grounded; the gate of the NMOS field-effect transistor is connected to the power output terminal; the drain of the NMOS field-effect transistor, the source of the PMOS field-effect transistor and the power input terminal of the boost circuit are connected together.

2. The power supply reverse connection protection circuit according to claim 1, characterized in that: The voltage at the power output terminal is greater than the voltage at the power supply input terminal, and the difference between the two voltages is greater than the turn-on voltage of the NMOS field effect transistor.

3. The power supply reverse connection protection circuit according to claim 1, characterized in that: The voltage at the power supply input terminal is greater than the turn-on voltage of the PMOS field effect transistor.

4. The power supply reverse connection protection circuit according to claim 1, characterized in that: The power supply input terminal, the PMOS field effect transistor, the boost circuit and the power ground connected to the power output terminal are connected together.

5. The power supply reverse connection protection circuit according to claim 1, characterized in that: The boost circuit further includes a boost module and a boost device.

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