Groove type MOSFET device

Abstract

The utility model relates to a power semiconductor device, in particular to a trench-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, and provides a novel shield gate trench-type field effect transistor in order to reduce the cellular size of the device and realize better compromise between breakdown voltage and on resistance. The semiconductor cell trench is composed of a plurality of deep trenches and shallow trenches which are periodically arranged at intervals in the Z direction, the deep trenches are 0.3-4 microns deeper than the shallow trenches, gate electrodes located above the trenches and shield gate electrodes located below the trenches are arranged in the shallow trenches and the deep trenches, and the gate electrodes and the shield gate electrodes are isolated from each other. The gate electrode is isolated from the corresponding side wall of the groove through a gate oxide layer, and the shield gate electrode is isolated from the corresponding side wall of the groove through a groove isolation layer; the gate electrode and the shield gate electrode are connected in the Z direction, and the shield gate electrode changes up and down along with different depths of the groove in the Z direction and is connected to the source electrode metal located on the upper surface at a proper position.

Description

Technical Field

[0001] The utility model relates to a power semiconductor device, in particular to the structure of a trench field effect transistor device and a manufacturing method thereof. Background Art

[0002] A structure of N-type shielded gate trench field effect transistor such as Figure 1 As shown, the device structure includes: an N-type semiconductor region 100; a series of cell trenches 101 located in the N-type semiconductor region 100. The cell trenches are filled with a gate electrode 110 located above and a shielding gate electrode 120 located below. The gate electrode 110 and the corresponding trench sidewall are isolated by a gate oxide layer; the shielding gate electrode 120 and the corresponding trench sidewall are isolated by a trench isolation layer 107; and the gate electrode 110 and the shielding gate electrode 120 are isolated by an inter-electrode isolation layer. The structure also includes a P-doped body region 103 and an N+ doped source region 104 located on the upper surface of the semiconductor between the cell trenches 101; in addition, a series of contact hole trenches 102 and a P+ contact doping region 105 located below the source contact hole trench 102 are included between the cell trenches 101. The source contact hole trench 102 is covered with an upper surface metal layer. A schematic diagram of the electric field strength versus trench depth of an embodiment of the structure is shown in FIG. Figure 3 As shown by the solid line in the middle, the electric field at the bottom of the trench is relatively high, which limits the improvement of the breakdown voltage. Figure 2 As shown, in Figure 1 Based on the device, the device has a trench isolation layer 107 with a thickness varying from thin at the top to thick at the bottom. Figure 1 The schematic diagram of the electric field strength versus trench depth is shown in FIG. Figure 3 As shown by the dotted line, since the trench isolation layer 107 at the bottom of the trench is thicker (d2 in the figure), the electric field strength at the bottom of the trench is reduced and the breakdown voltage is increased. Figure 2 The structure has a more optimized compromise between breakdown voltage and on-resistance. However, a thicker trench isolation layer 107 needs to be provided at the bottom of the trench, thus limiting the further reduction of the cell size. Utility Model Content

[0003] The utility model proposes a novel shielded gate trench field effect transistor with a special trench structure, which is beneficial for reducing the cell size of the device and achieving a better compromise between breakdown voltage and on-resistance.

[0004] A trench MOSFET device is provided. The device comprises a first conductive semiconductor region, wherein the first conductive semiconductor region comprises a series of periodically arranged, mutually parallel semiconductor cell trenches in the X direction. The semiconductor cell trenches are composed of a plurality of deep trenches and shallow trenches periodically arranged at intervals in the Z direction, wherein the deep trenches are 0.3-4 μm deeper than the shallow trenches. The shallow trenches and deep trenches are provided with mutually isolated gate electrodes located above the trenches and shielding gate electrodes located below the trenches. The gate electrodes are isolated from the corresponding trench sidewalls by a gate oxide layer, and the shielding gate electrodes are isolated from the corresponding trench sidewalls by a trench isolation layer. The gate electrode and the shielding gate electrode are connected in the Z direction, and the shielding gate electrode fluctuates in height in the Z direction with different trench depths and is connected to a source metal located on the upper surface at an appropriate position.

[0005] Furthermore, the bottoms of the shallow grooves and the deep grooves are in smooth arc shapes.

[0006] Furthermore, the trench isolation layer below the shallow trench is thicker than the trench isolation layer on its sidewall.

[0007] Furthermore, the deep grooves are circular or equilateral in the XZ section, and the distances between adjacent deep grooves in any direction are equal.

[0008] Furthermore, the deep grooves are circular or equilateral in the XZ section, and the deep grooves in adjacent cell grooves are evenly staggered.

[0009] Furthermore, the deep groove is an ellipse or a long symmetrical polygon in the XZ section.

[0010] Preferably, the bottom of the shallow trench, the bottom of the deep trench and the lower sidewall are provided with a second conductive type semiconductor doping region.

[0011] Furthermore, the junction depth of the second conductive type semiconductor doped region at the bottom of the deep trench is deeper than the junction depth of the second conductive type semiconductor doped region at the lower sidewall of the deep trench.

[0012] Furthermore, the second conductivity type semiconductor doped regions between the lower sidewalls of adjacent deep trenches in the Z direction are connected.

[0013] The utility model proposes a novel shielded gate trench field effect transistor with a special trench structure, which is beneficial for reducing the cell size of the device and achieving a better compromise between breakdown voltage and on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1-3 This is a schematic diagram of an existing shielded gate trench field effect transistor structure, showing how the electric field strength of the structure varies with the trench depth.

[0015] Figure 4 This is a schematic diagram of the trench structure of an embodiment of a shielded gate trench field effect transistor device of the present invention.

[0016] Figure 5 for Figure 4 A schematic cross-sectional view of the groove structure of the embodiment in the figure, along the groove direction.

[0017] Figure 6-8 These are three implementation methods of the top view of the trench structure of the shielded gate trench field effect transistor device of the present invention.

[0018] Figure 9-10 Schematic diagram of the trench cross-section along the Z direction and along the X direction in one embodiment of the shielded gate trench field effect transistor device of the present invention;

[0019] Figure 11-12 This is a schematic diagram of a trench cross section along the Z direction and the X direction in another embodiment of the shielded gate trench field effect transistor device of the present invention. DETAILED DESCRIPTION

[0020] The following describes the relevant technical background of existing shielded gate trench field effect transistors. It should be noted that the corresponding position words described in this document, such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", and "vertical", correspond to the relative positions of the reference diagrams. There is no restriction on fixed directions in the specific implementation. It should be noted that the devices in the drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions and trenches in the drawings, as well as the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0021] The present invention is described in detail below with reference to the accompanying drawings and embodiments. It should be noted that in the following description of the shielded gate trench field effect transistor device and its manufacturing method of the present invention, the semiconductor substrate of the shielded gate trench field effect transistor device is considered to be composed of silicon (Si) material. However, the substrate can also be composed of any other material suitable for the manufacture of shielded gate trench field effect transistors, such as gallium nitride (GaN), silicon carbide (SiC), etc. In the following description, the conductivity type of the semiconductor region is divided into P-type (second conductivity type) and N-type (first conductivity type). A P-type conductive semiconductor region can be formed by doping one or more impurities into the original semiconductor region. These impurities can be, but are not limited to, boron (B), aluminum (Al), gallium (Ga), etc. An N-type conductive semiconductor region can also be formed by doping one or more impurities into the original semiconductor region. These impurities can be, but are not limited to, phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (H +) etc. In the following description, the heavily doped P-type conductive semiconductor region is marked as P + The heavily doped N-type conductive semiconductor region is marked as N + For example, in a silicon substrate, unless otherwise specified, the impurity concentration of a heavily doped region is generally around 1× 10 19 cm -3 to 1 × 10 22 cm -3 Those skilled in the art should know that the P-type (second conductivity type) and the N-type (first conductivity type) described in the present invention can be interchanged.

[0022] A cell trench structure in a trench field effect transistor device of the present invention is as follows Figure 4 As shown, the structure includes an N-type semiconductor region 100, wherein a series of periodically arranged (X direction) and mutually parallel semiconductor cell trenches 201 are provided above the N-type semiconductor region 100, and the series of trenches have a depth variation in the trench extension direction (Z direction), that is, a plurality of periodically arranged deep trenches 211 are formed, and shallow trenches 212 are formed between adjacent deep trenches 211, and the shallow trenches 212 and the deep trenches 211 are arranged at intervals.

[0023] Typically, the intervals between the deep trenches 211 in the Z direction are equal to or slightly larger than the intervals in the X direction (see Figure 6 In some embodiments, the distances between the deep trench 211 and the surrounding deep trenches 211 are the same (refer to Figure 7 In an embodiment of a device with a breakdown voltage of 120 V, the spacing in the X and Z directions is between 1.4 and 2.8 μm. Typically, the spacing of the deep trenches 211 in both the X and Z directions is greater than 0.3 μm.

[0024] Generally speaking, the depth of the deep trench 211 is 0.3-4 μm deeper than the depth of the shallow trench 212. Figure 1 Based on the technical solution, the depth of some cell trenches is reduced by approximately 0.3-4 μm. In a device embodiment with a breakdown voltage of 120 V, the shallow trench 212 is between 2-4 μm deep, and the deep trench 211 is 2-4 μm deeper than the shallow trench 212. In a device embodiment with a breakdown voltage of 165 V, the shallow trench 212 is between 2-4 μm deep, and the deep trench 211 is 4-8 μm deeper than the shallow trench 212.

[0025] The deep groove 211 and the shallow groove 212 are generally cylindrical or elliptical, with a smooth arc bottom, similar to a needle.

[0026] The periodic cell trenches 201 are filled with two electrodes interconnected along the trench direction (Z direction): a gate electrode 110 located above and a shield gate electrode 120 located below. The gate electrode 110 is isolated from the corresponding trench sidewall by a gate oxide layer; the shield gate electrode 120 is isolated from the corresponding trench sidewall by a trench isolation layer 208; and the gate electrode 110 and the shield gate electrode 120 are isolated from each other by an inter-electrode isolation layer.

[0027] Compared with the existing device structure, the utility model adopts periodic needle-shaped deep trenches. The shielded gate electrode in the needle-shaped deep trenches is coupled to the adjacent semiconductor in the XZ plane, and the semiconductor is depleted not only in the X direction but also in the Z direction. Therefore, the equivalent lateral electric field strength in the X direction is greater than that in the Z direction. Figure 1 The device is small, the breakdown voltage is higher, and Figure 2 Compared with the structure in the conventional structure, this structure does not need to increase the thickness of the trench isolation layer in the deep trench, so it will not limit the reduction of the cell size. At the same time, because the trench density in the deep semiconductor of the structure of the utility model is smaller than that of the existing structure, the use of a breakdown voltage of 120V Figure 2 Taking the device with a structure as an example, d1=2000-4000A, d2=5000-8000A, and the cell size is 2.2-2.6um, while the corresponding device of the present invention with a breakdown voltage of 120V has d3=4000-6000A and the cell size is 1.8-2.4um. The cell size is reduced and the semiconductor conduction area (XZ plane) is larger. Therefore, it has a lower on-resistance in forward conduction, achieving a better compromise between breakdown voltage and on-resistance.

[0028] Figure 5 is a schematic cross-sectional view of the trench structure of the above device along the trench direction, and corresponds to Figure 4 The gate electrode 110 is connected to the deep trench 211 and the shallow trench 212 along the trench direction (Z direction) along the tangent line C. The gate electrode 110 is connected to the gate metal 210 on the upper surface through the gate contact hole 221 thereon.

[0029] The shield gate electrode 120 connects the deep trench 211 and the shallow trench 212 along the trench direction (Z direction) and has a varying height. In one trench section, the gate electrode 110 is not located in the upper portion of the trench. The shield gate electrode 120 extends to the upper portion of the trench and connects to the source metal 220 located on the upper surface through the source contact 222.

[0030] In some embodiments, the trench isolation layer 218 at the bottom of the shallow trench 212 is thicker than the trench isolation layer 208 on the sidewall. This structure helps to reduce the electric field strength below the shallow trench 212 and prevent the formation of breakdown weaknesses.

[0031] Preferably, the deep trenches 211 are evenly arranged on the XZ plane, which is beneficial to the charge balance of the device during reverse bias to improve the breakdown voltage; Figure 6-Figure 8 FIG. 1 is a top view of an embodiment of a trench structure in which deep trenches 211 are periodically distributed in the cellular trench 201 .

[0032] An embodiment of the present invention is as follows Figure 6 As shown, the deep trench 211 is circular or equilateral in the XZ section, and the adjacent cellular trenches 201 in the X direction have exactly the same trench structure. The distance w1 between adjacent deep trenches 211 in the X direction and the distance w2 between adjacent deep trenches 211 in the Z direction are, in one embodiment, w1=w2, and in another embodiment, w2 is 80-150% of w1.

[0033] Another embodiment of the present invention is as follows Figure 7 As shown, the deep trenches 211 are circular or equilateral in the XZ section, the deep trenches 211 in adjacent cellular trenches 201 in the X direction have a difference of half a period in the Z direction (uniformly staggered), the distance between the deep trenches 211 on two adjacent cellular trenches 201 is w3, the distance between adjacent deep trenches 211 in the Z direction is w2, in one embodiment w2=w3, in another embodiment, w2 is 80-150% of w3, and Figure 6 Compared with the structure, this structure has better charge balance ability when reverse biased.

[0034] Another embodiment of the present invention is as follows Figure 8 As shown, the deep trench 211 is an ellipse or a symmetrical polygon that is longer in the Z direction in the XZ section, and Figure 6 、 Figure 7 Compared with the structure, this structure is conducive to filling the isolation layer material and the electrode material in the deep trench 211 during the manufacturing process.

[0035] Figure 9-10 Another embodiment of the present invention is shown, wherein Figure 9 is a schematic cross-sectional view of the embodiment along the groove direction (Z direction), Figure 10 FIG2 is a schematic cross-sectional view of the structure along the X direction. The difference from the aforementioned structure is that the bottom of the shallow trench 212 and the bottom and lower sidewalls of the deep trench 211 have P-type semiconductor doped regions 230. The provision of the P-type semiconductor doped regions 230 helps reduce the electric field strength near the bottom of the deep trench 211 and also helps achieve charge balance during reverse bias, thereby improving breakdown resistance.

[0036] In some embodiments, the junction depth of the P-type semiconductor doping region 230 at the bottom of the deep trench 211 is deeper than the junction depth of the P-type semiconductor doping region 230 at the lower sidewall of the deep trench 211. In one practical embodiment, the junction depth of the P-type semiconductor doping region 230 at the bottom of the deep trench 211 is 0.2-2 μm, and the junction depth of the P-type semiconductor doping region 230 at the lower sidewall of the deep trench 211 is 0.1-0.5 μm.

[0037] The method for forming the P-type semiconductor doped region 230 may include multiple ion implantation steps.

[0038] Figure 11-12 Another embodiment of the utility model is shown. Figure 11 is a schematic cross-sectional view of the embodiment along the groove direction (Z direction), Figure 12 is a schematic diagram of the cross section of the structure along the X direction. Figure 9-10 Compared with the embodiment shown, the P-type semiconductor doping regions 230 located on the lower side walls of adjacent deep trenches 211 are connected together in the Z direction. Since the P-type semiconductor doping regions 230 on the lower side walls of the deep trenches 211 in the Z direction are connected to each other, the depth of the P-type semiconductor doping regions 230 below the shallow trench 212 is increased. The increased P-type semiconductor doping regions 230 are beneficial to charge balance during reverse bias, which can further improve the breakdown voltage.

[0039] The method for forming the P-type semiconductor doping region 230 may include at least one directional ion implantation step and at least one annealing step at 1000-1100°C.

[0040] The device structure of the present invention described above only illustrates the key trench structure, and does not specifically describe, for example, the epitaxial structure, semiconductor doping, or contact hole structure. Personnel skilled in the art will be able to appropriately combine and modify existing shielded gate trench field-effect transistor structures to implement more embodiments of the present invention. Personnel skilled in the art will also be able to appropriately combine and modify existing shielded gate trench field-effect transistor manufacturing processes to implement more embodiments of the present invention with process characteristics. For example, a self-aligned contact hole structure may be formed using a self-aligned process.

[0041] In addition, those skilled in the art should know that the structural features and process steps mentioned in the above-mentioned embodiments of the present invention can be combined with each other to form more embodiment device structures and implementation methods.

Claims

1. A trench MOSFET device, wherein a first conductive semiconductor region is provided in the device, characterized in that: The first conductive semiconductor region is provided with a series of periodically arranged and parallel semiconductor cell trenches, each of which is composed of a plurality of deep trenches and shallow trenches periodically arranged at intervals, wherein the deep trench is 0.3-4 μm deeper than the shallow trench, and the shallow trenches and deep trenches are provided with mutually isolated gate electrodes located above the trenches and shielding gate electrodes located below the trenches, the gate electrodes are isolated from the corresponding trench side walls by a gate oxide layer, and the shielding gate electrodes are isolated from the corresponding trench side walls by a trench isolation layer; the gate electrodes and shielding gate electrodes are connected in the Z direction, and the shielding gate electrodes fluctuate in height in the Z direction with different trench depths and are connected to the source metal located on the upper surface at an appropriate position.

2. The trench MOSFET device according to claim 1, wherein The bottoms of the shallow grooves and the deep grooves are in smooth arc shapes.

3. The trench MOSFET device according to claim 1, wherein: The trench isolation layer below the shallow trench is thicker than the trench isolation layer on the sidewall thereof.

4. The trench MOSFET device according to claim 1, wherein: The deep grooves are circular or equilateral in the XZ section, and the distances between adjacent deep grooves in any direction are equal.

5. The trench MOSFET device according to claim 1, wherein: The deep grooves are circular or equilateral in the XZ section, and the deep grooves in adjacent cell grooves are evenly staggered.

6. The trench MOSFET device according to claim 1, wherein: The deep groove is an ellipse or a long symmetrical polygon in the XZ section.

7. The trench MOSFET device according to any one of claims 1 to 6, wherein: The bottom of the shallow trench, the bottom of the deep trench and the lower sidewall are provided with a second conductive type semiconductor doping region.

8. The trench MOSFET device according to claim 7, wherein: The junction depth of the second conductive type semiconductor doping region at the bottom of the deep trench is deeper than the junction depth of the second conductive type semiconductor doping region at the lower sidewall of the deep trench.

9. The trench MOSFET device according to claim 7, wherein: The second conductive type semiconductor doped regions between the lower sidewalls of adjacent deep trenches in the Z direction are connected.

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