Package structure

Abstract

Some embodiments of the present application provide a package structure comprising: an electronic package comprising a first electronic component and a second electronic component, the working temperature of the first electronic component being higher than the working temperature of the second electronic component; the flow channel structure comprises an input port used for inputting liquid and an output port used for discharging the liquid, and a flow channel in the flow channel structure is arranged above the first electronic element and not arranged above the second electronic element. By using the flow channel structure, the heat resistance of the corresponding packaging structure is effectively reduced, and the heat dissipation capability of the packaging structure is improved.

Description

Technical Field

[0001] The present application relates to the technical field of power devices, and more specifically, to a packaging structure. Background Art

[0002] In recent years, due to the increasing demand for AI (artificial intelligence), servers, etc., the demand for advanced packaging has also increased. If encountering larger-sized high-end packages, the warping effect caused by thermal stress during the manufacturing process is more significant. The packaging structure of the fan-out chip on substrate (FoCoS) module will produce corresponding stress warping during the manufacturing process due to the CTE mismatch between the various materials. In order to control the stress warping problem of packaging structures with larger areas such as FOM (fiber optic modem), a dummy silicon layer is attached above the chips such as ASIC (application-specific integrated circuit) and HBM (high-bandwidth memory) to suppress the warping bending amount and reduce the problem of RDL layer (redistribution layer) stress warping causing RDL fracture. However, the additional dummy silicon will increase the thermal resistance of the chip upward, making it difficult for the chip to dissipate heat, resulting in an increase in chip temperature.

[0003] Specifically, see Figure 1A and Figure 1B , Figure 1A and Figure 1B The package structures 10 and 10-1 in the prior art are shown respectively. Figure 1A and Figure 1B As can be seen in FIG, the chips 12 and 13 are bonded to the substrate 11 through the redistribution structure 17 and the bumps 18, and are sealed by the sealant 16. In addition, in order to facilitate heat dissipation, as shown in FIG. Figure 1B As shown, a cooling system 20, such as a heat sink, a cold plate, etc., is provided above the chips 12 and 13, and Figure 1B The heat dissipation direction in is shown as S. Further, as Figure 1C The package structure 10-2 and Figure 1D As shown in the package structure 10-3, in the process of the package structure 10 such as FOM (fiber optic modem), in order to control the warpage to prevent the fracture of the redistribution layer 17 at the region C (such as Figure 1BAs shown in FIG, a silicon layer 15 is bonded above the chips (such as ASICs, HBMs) 12 and 13 through microbumps or thermal interface materials (TIM), or a ring 14 is attached around the chips 12 and 13 with an adhesive layer 19. However, adding a silicon layer 15 above the chips 12 and 13 will reduce the heat dissipation effect of the chips 12 and 13. It can be seen that in the existing package structures 10-2 and 10-3, in order to control the stress warping problem of the package structure 10 with a larger FOM area, a silicon layer 15 is added directly above the chip 12 such as an ASIC and the chip 13 such as an HBM, and then a cooling system 20 is provided to suppress the warping of the package structures 10-2 and 10-3 and prevent the redistribution structure 17 from cracking in area C. However, adding an additional silicon layer 15 (such as a dummy silicon layer) will increase the thermal resistance of the chips 12 and 13 upward, making it difficult for the chips 12 and 13 to dissipate heat, resulting in an increase in the temperature of the chips 12 and 13. Therefore, how to ensure the heat dissipation of the chips 14 and 15 while controlling the stress warping is a key research topic. Utility Model Content

[0004] In order to overcome the above defects, the present application uses a flow channel structure to solve the problem that attaching a silicon layer (reinforcement layer) on the chip to suppress the warping of the package structure increases the thermal resistance of the chip upward and makes it difficult to dissipate heat from the chip.

[0005] Some embodiments of the present application provide a packaging structure, including: an electronic package, the electronic package including a first electronic component and a second electronic component, the operating temperature of the first electronic component being higher than the operating temperature of the second electronic component; a flow channel structure, including an input port for inputting liquid and an output port for discharging liquid, wherein the flow channel in the flow channel structure is arranged above the first electronic component but not above the second electronic component.

[0006] In some embodiments, the flow channel structure includes a body and a cover covering the body, wherein the body has a groove, and the groove and the cover define the flow channel.

[0007] In some embodiments, the body includes a circuit structure disposed above the second electronic component.

[0008] In some embodiments, the circuit structure is disposed on a lower surface of the body.

[0009] In some embodiments, the circuit structure includes a capacitive device.

[0010] In some embodiments, the input port and the output port are both disposed above the second electronic component.

[0011] In some embodiments, the input port is disposed at a position above the second electronic component and closer to the first electronic component, and the output port is disposed at a position above the second electronic component and farther from the first electronic component.

[0012] In some embodiments, the input port and the output port are provided on the cover.

[0013] In some embodiments, the flow channel is serpentine.

[0014] In some embodiments, the packaging structure further includes: an electronic component attached to the lower surface of the body, wherein the electronic component is disposed outside the lateral extent of the electronic package.

[0015] In some embodiments, the packaging structure further includes: a ring structure disposed around the electronic package.

[0016] In some embodiments, the electronic component is disposed laterally between the ring structure and the electronic enclosure.

[0017] In some embodiments, the electronic component is disposed directly above the ring structure and between the flow channel structure and the ring structure.

[0018] In some embodiments, the electronic components are electrically connected via metal wires.

[0019] The metal wire surrounds the flow channel and is arranged outside the lateral range of the flow channel.

[0020] In some embodiments, the flow channel is not disposed above the electronic component.

[0021] In some embodiments, the package structure further includes a substrate, and the ring structure is attached over the substrate by an adhesive layer.

[0022] In some embodiments, the package structure further includes a substrate, and the ring structure is attached above the substrate through the electronic component.

[0023] Some further embodiments of the present application provide a packaging structure, comprising: a substrate; an electronic package arranged above the substrate; and a flow channel structure arranged above the electronic package and comprising a flow channel, wherein the electronic package comprises a first electronic component and a second electronic component, the operating temperature of the first electronic component is higher than the operating temperature of the second electronic component, and wherein the flow channel is arranged directly above the first electronic component, and a circuit structure is arranged directly above the second electronic component, and the flow channel does not overlap with the circuit structure.

[0024] In some embodiments, the flow channel structure includes a body and a cover covering the body, wherein the body has a groove, and the groove and the cover define the flow channel.

[0025] In some embodiments, the circuit structure is disposed on a lower surface of the body.

[0026] In this application, by utilizing the flow channel structure, the thermal resistance of the corresponding packaging structure is effectively reduced, and its heat dissipation capacity is increased, so that the thermal resistance θ of the corresponding packaging structure is reduced to JC Improved by more than 60%. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figures 1A to 1D The figure shows a packaging structure in the prior art.

[0029] Figures 2A to 2E The package structures of some embodiments of the present application are shown.

[0030] Figures 3A to 5B The package structures of some embodiments of the present application are shown.

[0031] Figures 6A to 6C The thermal resistance of the packaging structure in the prior art and the packaging structure of the present application are shown.

[0032] Figures 7 to 10 The process flow of the packaging structure according to some embodiments of the present application is shown. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field fall within the scope of protection of this application. In addition, when "approximately", "about", "substantial", "basic" and the like are used to describe a numerical value or a numerical range, unless otherwise specified, the term is intended to cover a numerical value within ±10% of the described numerical value. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0034] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. Moreover, the present invention may repeatedly refer to numbers and / or letters in various examples. This repetition is merely for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0035] As mentioned above, since the addition of an extra silicon layer increases the thermal resistance of the chip, the present application designs the silicon layer into a flow channel structure, that is, a microchannel form, thereby effectively reducing its thermal resistance and increasing the heat dissipation capacity of the corresponding packaging structure.

[0036] Some embodiments of the present application provide a packaging structure 100, see Figures 2A to 2C , Figure 2A FIG. 1 shows a package structure 100 according to some embodiments of the present application. Figure 2B Shown along Figure 2A A top view of line AA, and Figure 2C Shown Figure 2A The three-dimensional diagram of the package structure 100 is shown. Figures 2A to 2C In the package structure 100 shown, the package structure 100 includes: an electronic package 110, the electronic package 110 includes a first electronic component 102 and a second electronic component 103, the operating temperature of the first electronic component 102 is higher than the operating temperature of the second electronic component 103. Further, the package structure 100 also includes: a flow channel structure 120, such as Figure 2B As shown, the flow channel structure 120 includes an input port 120i for inputting liquid and an output port 120o for discharging liquid, wherein the flow channel 120w in the flow channel structure 120 is arranged above the first electronic component 102, but not above the second electronic component 103. In the present application, the micro-channel design of the flow channel 120w is distributed above the first electronic component 102 and avoids the second electronic component 103, which can more specifically guide the heat generated by the first electronic component 102, and the second electronic component 103 can be used as a functional circuit layout (such as setting a capacitor structure). In some embodiments, the micro-channel design of the flow channel 120w can be designed according to actual conditions, so as to facilitate the heat dissipation of the first electronic component 102 with a higher operating temperature. Figure 2BIn some embodiments, the flow channel 1210w may be filled with a cooling liquid, including but not limited to water, which may be limited according to actual conditions to better dissipate heat for the first electronic component 102. In some other embodiments, such as Figure 2E As shown, the flow channel 120 w in the flow channel structure 120 may be formed over the entire electronic package 110 .

[0037] In some embodiments, see Figure 2A as well as Figure 2D , Figure 2D The specific structure of the flow channel structure 120 is specifically shown. Figure 2D It can be clearly seen that the flow channel structure 120 includes a body 120A and a cover 120B covering the body 120A. Further, the body 120A has a groove R, and the groove R and the cover 120B define a flow channel 120w. Figures 2A to 2D As can be seen from FIG, the body 120A includes a circuit structure 112 disposed above the second electronic component 103, such as Figure 2B As shown. Further, the circuit structure 112 is provided on the lower surface 120Ad of the body 120A. Figure 2B As can be seen in FIG, the circuit structure 112 includes a capacitor device. In some embodiments, the body 120A and the cover 102B are made of silicon. In some embodiments, the circuit structure 112 includes a metal or a metal alloy, such as copper, gold, and the like and their alloys. In this application, Figure 2B In the top view shown, the flow channel 120 w does not overlap with the circuit structure 112 .

[0038] See also Figure 2B ,from Figure 2B As can be seen in FIG, both the input port 120i and the output port 120o are disposed above the second electronic component 103. Specifically, the input port 120i is closer to the first electronic component 102, and the output port 120o is farther from the first electronic component. That is, the input port 120i is disposed above the second electronic component 103 at a position closer to the first electronic component 102, and the output port 120o is disposed above the second electronic component 103 at a position farther from the first electronic component 102. Furthermore, the input port 120i and the output port 120o are disposed on the cover 120B.

[0039] Continue to refer to Figures 2A to 2D The package structure 100 further includes an electronic component 111 attached to the lower surface 120Ad of the body 120A. Figure 2A As can be seen from FIG, the electronic component 111 is arranged outside the lateral extent of the electronic package 110. Figure 2AAs shown, the packaging structure 100 further includes a ring structure 104 disposed around the electronic package 110. Figure 2A In the embodiment shown, the package structure 100 further includes a substrate 101, and a ring structure 104 is attached to the substrate 101 via an adhesive layer 109. In some embodiments, an electronic component 111 is laterally disposed between the ring structure 104 and the electronic package 110. In some embodiments, the electronic component 111 is electrically connected via metal wires 1201. In some embodiments, as shown in FIG. Figure 2B As shown, the metal wire 120l surrounds the flow channel 120w and is arranged outside the lateral extent of the flow channel 120w. In some embodiments, the metal wire 120l is arranged within the body 120A of the flow channel structure 120. Furthermore, the flow channel 120w is not arranged above the electronic component 111. In some embodiments, the electronic component 111 can be a component such as an inductor, a resistor, etc. In some embodiments, the metal wire 120l can include a metal or a metal alloy, such as copper, gold, and the like, and alloys thereof. In some embodiments, the ring structure 104 can be made of a supporting material, or can be made of a metal or a metal alloy, etc.

[0040] Next, see Figure 3A and Figure 3B , Figure 3A shows a package structure 100 ′ according to some embodiments of the present application, and Figure 3B Shown Figure 3A A magnified view of area A. Figure 3A In the illustrated package structure 100 ′, the electronic component 111 is disposed directly above the ring structure 104 and between the flow channel structure 120 and the ring structure 104. In this embodiment, the ring structure 104 is made of silicon and is connected to the flow channel structure 120 via the electronic component 111. Furthermore, the electronic component 111 includes through-silicon vias (TSVs) 111v. In this case, TSV technology is used to connect signals L1 and L2 from the flow channel structure 120. After these signals L1 and L2 are transmitted to the substrate 101, they can communicate with a first electronic component 102, such as an ASIC, and a second electronic component 103, such as an HBM.

[0041] See also Figure 4A and Figure 4B , Figure 4A shows a package structure 100 according to some embodiments of the present application, and Figure 4B Shown Figure 4A A magnified view of area A'. Figure 4AIn the package structure 100″ shown, the electronic component 111 is not only disposed directly above the ring structure 104, but the ring structure 104 is also attached to the substrate 101 via the electronic component 111. In order to reduce the signal transmission distance, the ring structure 104 and the corresponding electronic component 111 below the flow channel structure 120 can be retracted toward the electronic package 110, that is, retracted toward the interior. In this embodiment, the ring structure 104 is also made of silicon. Similarly, the electronic component 111 has a through-hole via (TSV) 111v. By using TSV silicon through-hole via assembly technology, the signals L1' and L2' of the flow channel structure 120 are connected, so that after the signals L1' and L2' are transmitted to the substrate 101, they can communicate with the first electronic component 102 such as an ASIC and the second electronic component 103 such as an HBM.

[0042] Figure 5A FIG. 1 shows a package structure 100 - 1 in which a plurality of package structures 100 are packaged. Figure 5A As can be seen from FIG, the channel structure 120 is not limited to a single package, and the corresponding package structure 100 can be connected to other package structures 100 through the channel structure 120, thereby enabling the signals of more peripheral components to communicate with each other. Figure 5B The package structure 100'-1 is shown, wherein a plurality of package structures 100 and a package structure 100' are packaged together, wherein the package structure 100' is disposed between the package structures 100. Figure 5B As can be seen from the figure, the channel structure 120 is not limited to a single package. The corresponding package structure 100 / 100' can be connected to other package structures 100 through the channel structure 120, thereby enabling signals of more peripheral components to communicate with each other. Figure 5B The diagram shows that after corresponding signals L1″ and L2″ are transmitted to substrate 101, they can communicate with first electronic component 102, such as an ASIC, and second electronic component 103, such as an HBM, in the middle of package structure 100 ′- 1 . It should be understood that any package and combination of the above-mentioned package structures 100 / 100′ / 100″ can be implemented according to practical circumstances.

[0043] Return to reference Figure 2A, the first electronic component 102 and the second electronic component 103 are sealed by a sealant 106. In some embodiments, the sealant 106 may include but is not limited to a molding compound, an underfill, etc. Further, the first electronic component 102 and the second electronic component 103 are connected to the redistribution structure 107 through a connector 113, and the redistribution structure 107 is bonded to the substrate 101 through a bump 108. In some embodiments, the connector 113 may be a conductive column, such as a copper conductive column, etc. In an embodiment, the redistribution structure 107 is a redistribution structure commonly used in the art, and because the microchannel structure 120 is provided, the problem of the redistribution structure 107 being subjected to stress and cracking is avoided. Further, the bump 108 may include but is not limited to a solder bump, and the substrate 101 may include but is not limited to a printed circuit board, etc.

[0044] Continue to refer to Figures 2A to 2B , other embodiments of the present application further provide a packaging structure 100, which includes: a substrate 101; an electronic package 110, arranged above the substrate 101; and a flow channel structure 120, arranged above the electronic package 110 and including a flow channel 120w, wherein the electronic package 110 includes a first electronic component 102 and a second electronic component 103, the operating temperature of the first electronic component 102 is higher than the operating temperature of the second electronic component 103, and wherein the flow channel 120w is arranged directly above the first electronic component 102, and the circuit structure 112 is arranged directly above the second electronic component 103, and in the top view shown in Figure 2B, the flow channel 120w does not overlap with the circuit structure 112. Further, the flow channel structure 120w includes a main body 120A and a cover 120B covering the main body 120A, wherein, as shown in FIG. Figure 2D As shown, the body 120A has a groove R, and the groove R and the cover 120B define a flow channel 120w. In some embodiments, the circuit structure 112 is disposed on the lower surface 120Ad of the body 120A.

[0045] Figures 6A to 6C Shown are the Figure 1C The package structure 10-2 shown in this application Figure 2A The package structure 100 and Figure 1A The thermal resistance θ of the corresponding electronic components of the package structure 10 is shown JC The following table 1 shows the thermal resistance θ of the corresponding package structure. JC value.

[0046] Table 1 Thermal resistance values ​​of package structure 10-2, package structure 100, and package structure 10

[0047]

[0048] It can be seen from Table 1 above that the thermal resistance θ of the package structure 100 with a micro-channel design of the flow channel structure 120 provided by the present application and the package structure 10 in which the chips 12 and 13 are directly exposed to the environment is JC The values ​​are close to or the same, and the thermal resistance θ of the microchannel package structure 100 is JC The value is much smaller than the package structure 10-2 in which a silicon layer 15 is formed on the chips 12 and 13, and compared with the package structure 10-2, the thermal resistance θ of the package structure 100 with microchannel design is JC The value is reduced by about 67%. It can be seen that the packaging structure 100 of the micro-channel design provided by the present application makes the thermal resistance θ JC The value improved by more than 60%.

[0049] Refer to the following Figure 7-10 To introduce this application Figure 2A The process flow of forming the package structure 100 is shown.

[0050] First, refer to Figure 7 and Figure 8 , providing a cover 120B such as silicon and a body 120A such as silicon having a groove R, in which the layout required for peripheral components such as electronic components 111 to communicate with each other (such as metal wires 1201) is made.

[0051] Then, the cover 120B, such as silicon, is bonded to the body 120A, such as silicon, having the groove R, thereby forming a Figure 9 The flow channel structure 120 shown in FIG. 1 has a flow channel 120w therein, and a metal wire 120l is provided on the lower surface 120Ad of the flow channel structure 120 for electrical connection of subsequent electronic components. In addition, the lower surface 120Ad of the flow channel structure 120 is further provided with the above Figure 2B The circuit structure 112 is shown.

[0052] Next, see Figure 10 , attaching the electronic component 111 to the lower surface 120Ad of the flow channel structure 120. In the present application, the electronic component 111 is attached to the lower surface 120Ad of the flow channel structure 120 at a position that does not vertically overlap with the flow channel 120w, that is, the electronic component 111 is attached to the edge of the lower surface 120Ad of the flow channel structure 120.

[0053] Finally, Figure 10 The structure shown is attached to an electronic package 110 (which is bonded to a substrate 101 via a redistribution structure 107 or the like), thereby obtaining the package structure 100 shown in FIG. 2 .

[0054] In the above preparation method, the layout required for the communication between peripheral components such as electronic components 111 (such as metal wires 120l) is made around the flow channel structure 120, and does not overlap with the flow channel 120w; first, the required flow channel 120w is etched above the range of the first electronic element 102, and the upper cover body 120B such as silicon is joined; then, the peripheral components such as electronic components 111 are bonded to the layout side of the flow channel structure 120 (not overlapping with the flow channel 120w); finally, the flow channel structure 120 is bonded to the electronic package 110 such as FOM, thereby obtaining a packaging structure 100 with a microchannel design.

[0055] In the present application, by setting the silicon layer into a flow channel structure 120 in the form of a micro-channel, the thermal resistance of the corresponding packaging structure 100 is effectively reduced, and its heat dissipation capacity is increased, so that the thermal resistance θ of the corresponding packaging structure 100 is JC Improvement of more than 60%. In addition, the flow channel 120w of the flow channel structure 120 made of silicon can be filled with water or cooling liquid. Therefore, the packaging structure provided by the present application has the following advantages:

[0056] 1) Combining the functions of silicon and a cooling system, while controlling the stress warpage of the corresponding package structure 100 / 100' / 100", it can also improve heat dissipation issues, and utilize the silicon flow channel structure 120 to achieve signal transmission between surrounding components;

[0057] 2) The flow channel 120w of the present application can be designed with corresponding micro-channels for high heat source density; and

[0058] 3) The non-channel areas at the edge of the silicon-based microfluidic channel (channel 120w) can be used for layout, allowing surrounding components to communicate signals with each other and making more efficient use of space.

[0059] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A packaging structure, characterized in that: include: An electronic package comprising a first electronic component and a second electronic component, wherein an operating temperature of the first electronic component is higher than an operating temperature of the second electronic component; The flow channel structure includes an input port for inputting liquid and an output port for discharging liquid, Wherein, the flow channel in the flow channel structure is arranged above the first electronic component, but not above the second electronic component.

2. The packaging structure according to claim 1, wherein: The flow channel structure includes a main body and a cover covering the main body. Wherein, the main body has a groove, and the groove and the cover body define the flow channel.

3. The packaging structure according to claim 2, wherein: The body includes a circuit structure disposed above the second electronic component.

4. The packaging structure according to claim 3, wherein: The circuit structure is arranged on the lower surface of the body.

5. The packaging structure according to claim 3, wherein: The circuit structure includes a capacitive device.

6. The packaging structure according to claim 5, wherein: The input port is provided at a position above the second electronic component and closer to the first electronic component, and the output port is provided at a position above the second electronic component and farther from the first electronic component.

7. The packaging structure according to claim 2, wherein: The input port and the output port are arranged on the cover body.

8. The packaging structure according to claim 2, wherein: Also includes: an electronic component attached to the lower surface of the body, Wherein, the electronic component is arranged outside the lateral range of the electronic package.

9. The packaging structure according to claim 8, wherein: Also includes: A ring structure is arranged around the electronic package.

10. The packaging structure according to claim 9, wherein: The electronic component is disposed laterally between the ring structure and the electronic enclosure.

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