Electronic package

Abstract

An electronic package mainly provides a cladding layer embedded with an electronic element, a wiring structure and a circuit structure are sequentially formed on the cladding layer, and a breaking part is formed in the circuit structure to disperse stress in the wiring structure and the circuit structure, so that the problem that the wiring structure or the circuit structure is broken is avoided.

Description

Technical Field

[0001] The present application relates to a semiconductor packaging technology, and more particularly to an electronic package capable of improving reliability. Background Art

[0002] To ensure the continued miniaturization and multifunctionality of electronic products and communications equipment, semiconductor packaging must evolve towards miniaturization to facilitate multi-pin connections. For example, in advanced process packaging, commonly used packaging types include flip-chip packaging, fan-out wiring, and embedded component processes.

[0003] Figures 1A to 1C It is a cross-sectional schematic diagram of a conventional method for manufacturing a semiconductor package 1 .

[0004] like Figure 1A As shown, a plurality of semiconductor chips 12 are disposed on a carrier 9 , and then the semiconductor chips 12 are encapsulated by an encapsulant 13 .

[0005] like Figure 1B As shown, a build-up structure 15 is formed on the encapsulation body 13, and a plurality of solder balls 16 are formed on the build-up structure 15. The build-up structure 15 includes a dielectric layer 150 disposed on the encapsulation body 13, a circuit layer 151 disposed on the dielectric layer 150, and a plurality of conductive blind vias 152 disposed in the dielectric layer 150. The conductive blind vias 152 electrically connect the circuit layer 151 and the semiconductor chip 12.

[0006] like Figure 1C As shown, remove the carrier 9, and then follow Figure 1B The cutting path S shown is used for the singulation process.

[0007] However, in the conventional method of manufacturing the semiconductor package 1, the semiconductor chips 12 are first embedded in the encapsulant 13 and then the build-up structure 15 is fabricated. Therefore, no underfill is used as a stress buffer between the build-up structure 15 and the semiconductor chip 12. Therefore, in the subsequent manufacturing process, the build-up structure 15 is prone to stress concentration, causing the build-up structure 15 to crack. Figure 1C The crack K shown causes damage to the circuit layer 151 .

[0008] Therefore, how to overcome the above-mentioned problems of the prior art has become a difficult problem that needs to be overcome urgently in the industry. Utility Model Content

[0009] In view of the foregoing deficiencies of the prior art, the present application provides an electronic package, comprising: a package layer; an electronic component embedded in the package layer; a wiring structure disposed on the package layer, and the wiring structure comprises an insulating layer disposed on the package layer, a wiring layer disposed on the insulating layer, and a plurality of first conductive blind vias disposed in the insulating layer, so that the first conductive blind vias electrically connect the wiring layer and the electronic component; and a routing structure disposed on the wiring structure, and the routing structure comprises at least one dielectric layer disposed on the insulating layer, a routing layer disposed on the dielectric layer, and a plurality of second conductive blind vias disposed in the dielectric layer, and the plurality of second conductive blind vias electrically connect the routing layer and the wiring layer, wherein the routing layer is formed with a break portion corresponding to the position of the electronic component.

[0010] The present application also provides a method for manufacturing an electronic package, comprising: providing a package layer embedded with an electronic component; forming a wiring structure on the package layer, wherein the wiring structure comprises an insulating layer disposed on the package layer, a wiring layer disposed on the insulating layer, and a plurality of first conductive blind vias disposed in the insulating layer, so that the first conductive blind vias electrically connect the wiring layer and the electronic component; and forming a routing structure on the wiring structure, wherein the routing structure comprises at least one dielectric layer disposed on the insulating layer, a routing layer disposed on the dielectric layer, and a plurality of second conductive blind vias disposed in the dielectric layer, and the plurality of second conductive blind vias electrically connect the routing layer and the wiring layer, wherein the routing layer is formed with a break portion corresponding to the position of the electronic component.

[0011] In the foregoing electronic package and method for manufacturing the same, the wiring structure and the routing structure are in the form of a routing redistribution layer (RDL).

[0012] In the foregoing electronic package and method for manufacturing the same, the first conductive blind vias and the break portion are misaligned with each other.

[0013] In the foregoing electronic package and method for manufacturing the same, the routing structure comprises a plurality of the routing layers. Further, a plurality of the break portions are arranged on different layers of the plurality of the routing layers.

[0014] In the foregoing electronic package and method for manufacturing the same, the break portion is located on the routing layer adjacent to the insulating layer.

[0015] In the foregoing electronic package and method for manufacturing the same, the break portion is located within the vertically projected area of the first conductive blind via.

[0016] In the foregoing electronic package and method for manufacturing the same, the break portion is located within the vertically projected area of the electronic component.

[0017] In the foregoing electronic package and method for manufacturing the same, a single routing layer has a plurality of the break portions.

[0018] As can be seen from the above, the electronic package and its manufacturing method of the present application mainly form a disconnect portion in the circuit layer located on the dielectric layer to disperse the stress in the wiring structure and the circuit structure. Therefore, compared with the existing technology, the electronic package can avoid the problem of stress concentration in the wiring structure and the circuit structure, thereby avoiding the problem of cracking of the wiring structure or the circuit structure, and thus avoiding damage to the wiring layer or the circuit layer, thereby improving product yield and product reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figures 1A to 1C It is a cross-sectional schematic diagram of a conventional method for manufacturing a semiconductor package.

[0020] Figures 2A to 2D It is a cross-sectional schematic diagram of the manufacturing method of the electronic package of this application.

[0021] Figure 2E for Figure 2D A cross-sectional schematic diagram of the subsequent process.

[0022] Figure 3 for Figure 2D A partial cross-sectional schematic diagram of another embodiment of the present invention.

[0023] Figure 4A 、 Figure 4B and Figure 4C for Figure 2D Schematic diagram of a partial cross section of other different embodiments.

[0024] Description of Reference Numerals

[0025] 1 Semiconductor Package

[0026] 12 semiconductor chips

[0027] 13 Encapsulation colloid

[0028] 15 Layered Structure

[0029] 150,250 dielectric layer

[0030] 151,251 circuit layers

[0031] 152 conductive blind vias

[0032] 16,32 solder balls

[0033] 2 Electronic packaging

[0034] 20 Loading plate

[0035] 200 release layer

[0036] 201 bonding layer

[0037] 210,310,410,420,430 disconnection parts

[0038] 22 Electronic components

[0039] 22a Active surface

[0040] 22b Non-active surface

[0041] 220 conductive bumps

[0042] 23 cladding

[0043] 23a First surface

[0044] 23b Second surface

[0045] 24 Wiring Structure

[0046] 240 insulation layer

[0047] 241 wiring layer

[0048] 242 first conductive blind via

[0049] 25 Line structure

[0050] 252 Second conductive blind via

[0051] 26 Conductive elements

[0052] 260 Underbump Metallurgy

[0053] 27 Insulation protective layer

[0054] 3 Electronic devices

[0055] 3a Upper side

[0056] 3b Lower side

[0057] 30 heat sink

[0058] 31 Passive components

[0059] 32 solder balls

[0060] 9 bearing parts

[0061] A, B vertical projection area

[0062] K Crack

[0063] S Cutting path. DETAILED DESCRIPTION

[0064] The following describes the implementation of the present application through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification.

[0065] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of this application. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed in this application without affecting the efficacy and purpose that can be achieved by this application. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of this application. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of this application without substantially changing the technical content.

[0066] Figures 2A to 2D It is a cross-sectional schematic diagram of a method for manufacturing the electronic package 2 of the present application.

[0067] like Figure 2A As shown, at least one electronic component 22 is disposed on a carrier board 20 (two electronic components 22 are shown in the drawings of this embodiment), and then a covering layer 23 having a first surface 23a and a second surface 23b opposite to each other is formed on the carrier board 20 to cover the electronic component 22 so that the electronic component 22 is embedded in the covering layer 23.

[0068] A release layer 200 and a bonding layer 201 may be sequentially formed on the carrier plate 20 , so that the second surface 23 b of the cladding layer 23 and the electronic component 22 are bonded to the bonding layer 201 .

[0069] In this embodiment, the release layer 200 is a thermal release tape, a light-sensitive release film, or a mechanical release structure, and the bonding layer 201 is an adhesive material.

[0070] The coating layer 23 is an insulating material, such as a dry film, an encapsulating colloid such as epoxy resin, or a molding compound.

[0071] In this embodiment, the coating layer 23 can be formed on the carrier board 20 by using liquid compound, injection, lamination, or compression molding.

[0072] The electronic component 22 is an active component, a passive component or a combination thereof, wherein the active component is a semiconductor chip, and the passive component is a resistor, a capacitor and an inductor.

[0073] In this embodiment, the electronic component 22 is a semiconductor chip having an active surface 22a and an inactive surface 22b relative to each other. The active surface 22a has a plurality of electrode pads for combining a plurality of conductive bumps 220, and the inactive surface 22b of the electronic component 22 is combined with the bonding layer 201, and the plurality of conductive bumps 220 are exposed on the first surface 23a of the encapsulation layer 23.

[0074] like Figure 2B As shown, a wiring structure 24 is formed on the first surface 23a of the cladding layer 23, and the wiring structure 24 includes an insulating layer 240 provided on the cladding layer 23, a wiring layer 241 provided on the insulating layer 240, and a plurality of first conductive blind vias 242 provided in the insulating layer 240, so that the plurality of first conductive blind vias 242 electrically connect the wiring layer 241 and the conductive bumps 220 of the electronic component 22.

[0075] In this embodiment, the wiring structure 24 is a redistribution layer (RDL) specification.

[0076] Furthermore, the wiring layer 241 and the first conductive blind via 242 are made of copper, and the insulating layer 240 is made of dielectric materials such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP).

[0077] like Figure 2C As shown, a circuit structure 25 is formed on the wiring structure 24, wherein the circuit structure 25 includes at least one dielectric layer 250 disposed on the insulating layer 240, at least one wiring layer 251 disposed on the dielectric layer 250, and a plurality of second conductive blind vias 252 disposed in the dielectric layer 250, and the plurality of second conductive blind vias 252 electrically connect the wiring layer 251 and the wiring layer 241.

[0078] In this embodiment, the circuit structure 25 is of RDL specification, and the material forming the circuit layer 251 and the second conductive blind vias 252 is copper. In the drawings of this embodiment, the circuit structure 25 includes multiple dielectric layers 250, each formed of a dielectric material such as poly(p-oxadiazole) (PBO), polyimide (PI), or prepreg (PP). Furthermore, the outermost surface of the circuit structure 25 may be coated with a solder mask material such as green paint or graphite to serve as an insulating protective layer 27. Portions of the outermost circuit layer 251 are exposed above the insulating protective layer 27 to allow for bonding of multiple conductive elements 26. For example, the conductive elements 26 may be C4 solder bumps or metal bumps containing solder. Prior to forming the conductive elements 26, an under-bump metallurgy (UBM) 260 may be formed on the circuit layer 251 to facilitate bonding of the conductive elements 26.

[0079] In addition, the dielectric layer 250 may be made of the same material as the insulating layer 240 , and the wiring layer 251 and the second conductive blind via 252 may be made of the same material as the wiring layer 241 and the first conductive blind via 242 .

[0080] Furthermore, the circuit layer 251 has a notch-like disconnection portion 210 formed at a position corresponding to the electronic component 22. In this embodiment, the disconnection portion 210 is located within the vertical projection area B of the electronic component 22, preferably at an edge of the vertical projection area B of the electronic component 22.

[0081] In one embodiment, the number of layers of the circuit layer 251 can be designed according to requirements, such as Figure 2C The second floor shown, Figure 3 A layer as shown or Figure 4A The three layers shown enable the disconnection portions 210, 310, 410 to be positioned in any circuit layer 251 as required, for example Figure 2C 、 Figure 3 or Figure 4A The disconnected portions 210 , 310 , 410 are located near the circuit layer 251 of the insulating layer 240 , ie, adjacent to the circuit layer 251 of the insulating layer 240 , so as to be as close to the electronic component 22 as possible. The closer to the electronic component 22 , the greater the stress on the circuit layer 251 .

[0082] In one embodiment, the disconnect portion 210 , 310 , 410 is not aligned with the first conductive blind via 242 , so the disconnect portion 210 , 310 , 410 is offset from the first conductive blind via 242 . In another embodiment, the disconnect portion 210 , 310 , 410 is located within a vertical projection area A of the first conductive blind via 242 .

[0083] like Figure 2DAs shown, the carrier plate 20, the release layer 200 and the bonding layer 201 are removed, so that the inactive surface 22b of the electronic component 22 is exposed on the second surface 23b of the covering layer 23. Figure 2C The cutting path S shown is used for the singulation process.

[0084] In addition, if Figure 2E As shown, in the subsequent process, the electronic package 2 can be combined with an electronic device 3 such as a circuit board through the conductive elements 26, wherein the upper side 3a of the electronic device 3 can be configured with the electronic package 2, at least one heat sink 30 and at least one passive component 31, and the lower side 3b of the electronic device 3 can be configured with multiple solder balls 32.

[0085] Therefore, the electronic package of the present application forms disconnect portions 210, 310, 410 through the circuit layer 251 located on the dielectric layer 250 to disperse the stress in the wiring structure 24 and the circuit structure 25. Therefore, compared with the prior art, the electronic package 2 can effectively avoid the problem of stress concentration in the wiring structure 24 and the circuit structure 25, thereby avoiding the wiring structure 24 or the circuit structure 25 from cracking, thereby avoiding damage to the wiring layer 241 or the circuit layer 251, thereby improving product yield and product reliability.

[0086] Furthermore, in other embodiments, the circuit layer 251 on a dielectric layer 250 may be cut into multiple segments according to stress requirements to form a structure having multiple cut portions 420, such as Figure 4B The mesh shape shown enables the electronic package 2 to better avoid stress concentration on the wiring structure 24 and the circuit structure 25 , thereby preventing the wiring structure 24 or the circuit structure 25 from cracking.

[0087] It should be understood that the number of disconnected portions on the circuit layer 251 of the circuit structure 25 can be configured as required, such as Figure 4A and Figure 4B As shown, a plurality of disconnected portions 410, 420 may be formed on a single circuit layer 251, or as shown in FIG. Figure 4C As shown, disconnecting portions 410 and 430 may be formed on different circuit layers 251 .

[0088] The present application also provides an electronic package 2, comprising: a covering layer 23, at least one electronic component 22 embedded in the covering layer 23, a wiring structure 24 provided on the covering layer 23, and a circuit structure 25 provided on the wiring structure 24, wherein the circuit structure 25 is formed with a disconnection portion 210, 310, 410, 420, 430.

[0089] The wiring structure 24 includes an insulating layer 240 disposed on the cladding layer 23 , a wiring layer 241 disposed on the insulating layer 240 , and a plurality of first conductive blind vias 242 disposed in the insulating layer 240 , so that the plurality of first conductive blind vias 242 electrically connect the wiring layer 241 and the electronic component 22 .

[0090] The circuit structure 25 includes at least one dielectric layer 250 disposed on the insulating layer 240, at least one circuit layer 251 disposed on the dielectric layer 250, and a plurality of second conductive blind vias 252 disposed in the dielectric layer 250, wherein the plurality of second conductive blind vias 252 electrically connect the circuit layer 251 and the wiring layer 241, wherein the circuit structure 25 is formed with disconnected portions 210, 310, 410, 420, 430.

[0091] In one embodiment, the wiring structure 24 and the circuit structure 25 are of redistribution layer (RDL) specifications.

[0092] In one embodiment, the first conductive blind via 242 and the disconnecting portion 210 , 310 , 410 , 420 , 430 are offset from each other.

[0093] In one embodiment, the circuit structure 25 includes a plurality of circuit layers 251 . For example, the disconnecting portions 210 , 310 , 410 , 420 , and 430 are disposed on different layers of the plurality of circuit layers 251 .

[0094] In one embodiment, the disconnecting portion 210 , 310 , 410 , 420 , 430 is located within a vertical projection area A of the first conductive blind via 242 .

[0095] In one embodiment, the disconnected portions 210 , 310 , 410 , 420 , and 430 are located within a vertical projection area B of the electronic component 22 .

[0096] In one embodiment, the disconnecting portions 210 , 310 , 410 , 420 , and 430 are located in the circuit layer 251 adjacent to the insulating layer 240 .

[0097] In one embodiment, a plurality of disconnecting portions 420 are disposed on a single circuit layer 251 .

[0098] In summary, the electronic package of the present application forms a disconnect portion in the circuit layer located on the dielectric layer to disperse the stress in the wiring structure and the circuit structure. Therefore, the electronic package can effectively avoid the problem of stress concentration in the wiring structure and the circuit structure, thereby avoiding the problem of cracking of the wiring structure or the circuit structure.

[0099] The above examples are intended to illustrate the principles of the application and its best mode and are not intended to limit its scope. Since the application can be practiced with modification and alteration within the spirit and scope of the present disclosure, the applicant hereby gives permission to make, use, and / or sell many embodiments only as examples of the application and as specific examples of embodiments disclosed. The application is not limited to these embodiments, but the scope of the application is to be accorded the broadest interpretation of the principles and features disclosed herein and / or illustrated in the examples.

Claims

1. An electronic package, characterized in that: include: cladding; electronic components embedded in the coating layer; a wiring structure formed on the cladding layer, the wiring structure comprising an insulating layer disposed on the cladding layer, a wiring layer disposed on the insulating layer, and a plurality of first conductive blind vias disposed in the insulating layer, such that the plurality of first conductive blind vias electrically connect the wiring layer and the electronic component; as well as A circuit structure is formed on the wiring structure, and the circuit structure includes at least one dielectric layer provided on the insulating layer, at least one circuit layer provided on the dielectric layer, and a plurality of second conductive blind vias provided in the dielectric layer, and the plurality of second conductive blind vias electrically connect the circuit layer and the wiring layer, wherein the circuit layer is formed with a disconnection portion corresponding to the position of the electronic component.

2. The electronic package according to claim 1, wherein The wiring structure and the line structure are of line redistribution layer specifications.

3. The electronic package according to claim 1, wherein: The first conductive blind hole and the disconnecting portion are offset from each other.

4. The electronic package according to claim 1, wherein: The circuit structure includes a plurality of circuit layers.

5. The electronic package according to claim 4, wherein: The plurality of disconnecting portions are arranged on different layers of the plurality of circuit layers.

6. The electronic package according to claim 1, wherein: The disconnecting portion is located on the circuit layer adjacent to the insulating layer.

7. The electronic package according to claim 1, wherein: The disconnecting portion is located within a vertical projection area of ​​the first conductive blind hole.

8. The electronic package according to claim 1, wherein: The disconnecting portion is located within a vertical projection area of ​​the electronic component.

9. The electronic package according to claim 1, wherein: A single circuit layer has a plurality of disconnected portions.

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