Electronic package
By setting stress buffers on the cutting paths of semiconductor packages and forming a coating layer, the warping problem caused by shrinkage of the packaging layer is solved, the rigidity and stability of the package are improved, and the requirements for light, thin and short electronic products are met.
Patent Information
- Application Number
- CN202422644402.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-10-25
- Filing Date
- 2024-10-31
- Publication Date
- 2025-10-14
- Estimated Expiration
- 2034-10-31
AI Technical Summary
Existing semiconductor packages suffer from warping problems due to shrinkage of the packaging adhesive after the packaging layer is formed. In severe cases, this may damage the chip and make it difficult to meet the demand for thin and compact electronic products.
A stress buffer is set on the cutting path of multiple electronic components, and a coating layer is formed to cover the electronic components and the stress buffer. The stress buffer has a greater thermal expansion coefficient than the coating layer and is formed through an exposure and development process. The stress buffer is removed on the cutting path to reduce stress generation and improve structural rigidity.
It effectively reduces the warping of the package, enhances the rigidity of the overall structure, avoids chip damage caused by excessive warping, and meets the requirements of high-density, high-performance, thin and light electronic products.
Smart Images
Figure CN223436513U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a semiconductor packaging technology, and more particularly to an electronic package capable of reducing package warpage. Background Art
[0002] With the rapid development of portable electronic products in recent years, various related products are gradually moving towards high density, high performance, and light, thin, short and small trends. Various packaging processes are also constantly being innovated to meet the requirements of lightness, thinness, shortness and high density.
[0003] FIG. 1A and FIG. 1B It is a cross-sectional schematic diagram of a conventional method for manufacturing a semiconductor package.
[0004] like FIG. 1A As shown, a wafer 1 is placed on a carrier 13. The wafer 1 includes a plurality of chips 10. Each chip 10 has a first surface 10a and a second surface 10b opposite to each other. A plurality of first metal bumps 11 are formed on the first surface 10a, and a plurality of second metal bumps 12 are formed on the second surface 10b.
[0005] like FIG. 1B As shown, a packaging process is performed to form a packaging layer 14 covering the plurality of chips 10 on the carrier 13 .
[0006] In the aforementioned semiconductor package, in order to meet the trend of light, thin, short and small electronic products, the thickness of the chip 10 has been designed to be thinner and thinner. However, after the packaging layer 14 is formed, due to the shrinkage of the packaging material (such as FIG. 1B The wafer 1 will be warped significantly (as indicated by the arrow), and in severe cases, the chip 10 may be damaged.
[0007] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Utility Model Content
[0008] In view of the various deficiencies of the above-mentioned prior art, the present application provides an electronic packaging assembly, comprising: a plurality of electronic components, each of the electronic components having a first side and a second side relative to each other, wherein the first side is formed with a plurality of first conductive bumps, the second side is formed with a plurality of second conductive bumps, and the electronic components are separated from each other by cutting lines; a stress buffer disposed on the cutting line; and a covering layer for covering the plurality of electronic components and the stress buffer, and allowing the end face of the stress buffer to be exposed outside the covering layer.
[0009] The application also provides a method for manufacturing an electronic package, comprising: providing a whole structure comprising a plurality of electronic elements, wherein each of the electronic elements has opposite first and second sides, the first side is formed with a plurality of first conductive bumps, the second side is formed with a plurality of second conductive bumps, and each of the electronic elements is spaced from each other by a cutting path; disposing a stress buffer on the cutting path; and forming a covering layer covering the plurality of electronic elements and the stress buffer, and making the end surface of the stress buffer exposed outside the covering layer.
[0010] The aforementioned electronic package and the method for manufacturing the same further comprise removing the stress buffer to expose the cutting path.
[0011] The aforementioned electronic package and the method for manufacturing the same further comprise cutting along the cutting path to separate each of the electronic elements.
[0012] The aforementioned electronic package and the method for manufacturing the same further comprise removing the stress buffer from the cutting path by cleaning.
[0013] The aforementioned electronic package and the method for manufacturing the same further comprise that the stress buffer is a water-soluble glue material, and is formed on the cutting path by an exposure and development process.
[0014] The aforementioned electronic package and the method for manufacturing the same further comprise that a plurality of conductive through holes are formed inside the electronic element, so that the plurality of conductive through holes are electrically connected to the plurality of first conductive bumps and the plurality of second conductive bumps.
[0015] The aforementioned electronic package and the method for manufacturing the same further comprise that the width of the stress buffer is greater than the width of the cutting path.
[0016] The aforementioned electronic package and the method for manufacturing the same further comprise that the thermal expansion coefficient of the stress buffer is different from the thermal expansion coefficient of the covering layer.
[0017] The aforementioned electronic package and the method for manufacturing the same further comprise that the thermal expansion coefficient of the stress buffer is greater than the thermal expansion coefficient of the covering layer.
[0018] The aforementioned electronic package and the method for manufacturing the same further comprise that the stress buffer and the plurality of second conductive bumps are located on the same side, and the height of the stress buffer is greater than the height of each of the plurality of second conductive bumps.
[0019] The aforementioned electronic package and the method for manufacturing the same further comprise that the first conductive bumps and the second conductive bumps are metal columns.
[0020] As can be seen from the above, the electronic package and the method for manufacturing the same of the application mainly dispose a stress buffer on the cutting path between the plurality of electronic elements, and then form a covering layer covering the plurality of electronic elements and the stress buffer, so as to reduce the stress by reducing the covering layer, interrupt the stress, and improve the overall structural rigidity, thereby avoiding the problem of excessive warping. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] FIGS. 1A-1B It is a cross-sectional schematic diagram of a conventional method for manufacturing a semiconductor package.
[0022] FIGS. 2A-2C Schematic cross-sectional view of the electronic package and its manufacturing method of the present application.
[0023] Description of Reference Numerals
[0024] 1 wafer
[0025] 10 chips
[0026] 10a First surface
[0027] 10b Second surface
[0028] 11. First metal bump
[0029] 12 Second metal bump
[0030] 13 carrier board
[0031] 14 Encapsulation layer
[0032] 2 Wafer structure
[0033] 2a Electronic packaging
[0034] 20 electronic components
[0035] 20a First side
[0036] 20b Second side
[0037] 200 cutting lanes
[0038] 201 Conductive Perforation
[0039] 21 first conductive bump
[0040] 22 second conductive bump
[0041] 23 bearing parts
[0042] 24 cladding
[0043] 25 Rubber
[0044] 26 Stress buffer
[0045] S,W width. DETAILED DESCRIPTION
[0046] The following describes the implementation of the present application through specific embodiments. Professionals in this field can easily understand other advantages and effects of the present application from the contents disclosed in this specification.
[0047] It is to be understood that the structures, proportions, sizes, etc. shown in the drawings accompanying the present disclosure are merely intended to facilitate the understanding of the present disclosure and are not intended to limit the scope of the present application. Any modification, change in proportion, or adjustment in size that does not affect the function and purpose of the present application should still fall within the scope of the present disclosure. Meanwhile, the terms such as "upper", "first", "second", "one", etc. cited in the present disclosure are merely for the convenience of understanding and are not intended to limit the scope of the present application. Any change in relative relationship or adjustment without substantial change in technical content should also be considered as the scope of the present application.
[0048] FIGS. 2A-2C Cross-sectional view of the method for manufacturing the electronic package of the present application.
[0049] As shown in FIG. 2A , a wafer structure 2 containing a plurality of electronic elements 20 is provided and placed on a carrier 23, wherein each of the electronic elements 20 is spaced apart from each other by a cutting path 200.
[0050] The electronic element 20 is, for example, a semiconductor chip having opposite first and second sides 20a and 20b, and a plurality of first conductive bumps 21 formed on the first side 20a and a plurality of second conductive bumps 22 formed on the second side 20b. The wafer structure 2 is placed on the carrier 23 with the side having the plurality of first conductive bumps 21 through an adhesive 25 so that the plurality of first conductive bumps 21 are embedded in the adhesive 25. The first and second conductive bumps 21 and 22 are, for example, metal pillars of copper pillars, the adhesive 25 is, for example, an adhesive material, and the carrier 23 is, for example, a temporary carrier of non-electrically functional type.
[0051] In addition, a plurality of conductive vias 201 are formed inside the electronic element 20 to electrically connect the plurality of first conductive bumps 21 and the plurality of second conductive bumps 22. The conductive via 201 is, for example, a conductive silicon via (TSV for short).
[0052] Next, a stress buffer 26 is formed on the cutting path 200, wherein the stress buffer 26 is located on the same side as the plurality of second conductive bumps 22. The stress buffer 26 is, for example, a water-soluble adhesive that can be formed on the cutting path 200 through a process such as exposure and development.
[0053] In one embodiment, the width W of the stress buffer 26 is greater than the width S of the scribe line 200 .
[0054] like FIG. 2B As shown, a coating layer 24 is formed on the carrier 23 to cover the plurality of electronic components 20 (including a plurality of second conductive bumps 22 ) and the stress buffer 26 , and the end surface of the stress buffer 26 is exposed outside the coating layer 24 .
[0055] In one embodiment, the thermal expansion coefficient of the stress buffer 26 is different from the thermal expansion coefficient of the coating layer 24 .
[0056] In one embodiment, the thermal expansion coefficient of the stress buffer 26 is greater than the thermal expansion coefficient of the coating layer 24 .
[0057] In one embodiment, the height of the stress buffer 26 is greater than the height of each of the plurality of second conductive bumps 22 to prevent the stress buffer 26 from being covered by the coating layer 24 and causing stress problems.
[0058] like FIG. 2C As shown, the stress buffer 26 located above the scribe line 200 is removed to expose the scribe line 200, wherein the coating layer 24 still covers the plurality of electronic components 20 (including the plurality of second conductive bumps 22). The stress buffer 26 can be removed from the scribe line 200 by cleaning.
[0059] Subsequently, cutting can be performed along the cutting streets 200 to separate the electronic components 20 .
[0060] This application also provides FIG. 2B The electronic package 2a shown includes: a plurality of electronic components 20, each of the electronic components 20 having a first side 20a and a second side 20b relative to each other, wherein the first side 20a is formed with a plurality of first conductive bumps 21, the second side 20b is formed with a plurality of second conductive bumps 22, and each of the electronic components 20 is separated from each other by a cutting line 200; a stress buffer 26, arranged on the cutting line 200; and a covering layer 24, used to cover the plurality of electronic components 20 and the stress buffer 26, and to expose the end surface of the stress buffer 26 to the outside of the covering layer 24.
[0061] The plurality of electronic components 20 constitute a monolithic wafer structure 2. A plurality of conductive through-holes 201 are formed inside the electronic component 20 so as to electrically connect the plurality of first conductive bumps 21 and the plurality of second conductive bumps 22.
[0062] In summary, the electronic package and the manufacturing method thereof of the present application mainly set stress buffer members on the cutting paths among the plurality of electronic elements, and then forms a coating layer covering the plurality of electronic elements and the stress buffer members, so as to reduce the stress generation by reducing the coating layer, interrupt the stress and improve the overall structure rigidity, and avoid the problem of excessive warpage.
[0063] The above embodiments are used to illustrate the principles and effects of the present application, and are not used to limit the present application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the claims.
Claims
1. An electronic package, characterized in that: include: A plurality of electronic components, each of the electronic components having a first side and a second side opposite to each other, wherein a plurality of first conductive bumps are formed on the first side, a plurality of second conductive bumps are formed on the second side, and the electronic components are separated from each other by scribe lines; a stress buffer disposed on the cutting path; and The covering layer is used for covering the plurality of electronic components and the stress buffer, and the end surface of the stress buffer is exposed outside the covering layer.
2. The electronic package according to claim 1, wherein The plurality of electronic components form a whole wafer structure.
3. The electronic package according to claim 1, wherein: A plurality of conductive through-holes are formed inside the electronic component so as to electrically connect the plurality of first conductive bumps and the plurality of second conductive bumps.
4. The electronic package according to claim 1, wherein: The stress buffer is made of water-soluble adhesive.
5. The electronic package according to claim 1, wherein: The width of the stress buffer is greater than the width of the scribe line.
6. The electronic package according to claim 1, wherein: The stress buffer has a thermal expansion coefficient different from that of the coating layer.
7. The electronic package according to claim 1, wherein: The thermal expansion coefficient of the stress buffer is greater than the thermal expansion coefficient of the coating layer.
8. The electronic package according to claim 1, wherein: The stress buffer and the second conductive bumps are located on the same side, and the height of the stress buffer is greater than the height of each of the second conductive bumps.
9. The electronic package according to claim 1, wherein: The first conductive bump and the second conductive bump are metal pillars.