Electronic package

Abstract

An electronic package mainly provides a cladding layer embedded with an electronic element, a wiring structure and a circuit structure are sequentially formed on the cladding layer, and a reinforcing blind hole is formed in the circuit structure to disperse stress in the wiring structure and the circuit structure, so that the problem that the wiring structure or the circuit structure is broken is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor packaging technology, in particular to an electronic package with improved reliability and a manufacturing method thereof. BACKGROUND

[0002] In order to ensure the continuous miniaturization and multifunctionality of electronic products and communication devices, semiconductor packaging needs to be developed towards miniaturization to facilitate the connection of multiple pins. For example, in advanced packaging processes, commonly used packaging types such as flip-chip packaging processes, fan-out wiring processes with embedded components, etc.

[0003] Figures 1A-1C FIG. 1 is a cross-sectional view of a manufacturing method of a conventional semiconductor package 1.

[0004] As shown in FIG. 1, a plurality of semiconductor chips 12 are disposed on a carrier 9, and the semiconductor chips 12 are covered with a packaging gel 13. Figure 1A As shown in FIG. 2, a build-up structure 15 is formed on the packaging gel 13, and a plurality of solder bumps 16 are formed on the build-up structure 15. The build-up structure 15 includes a dielectric layer 150 disposed on the packaging gel 13, a circuit layer 151 disposed on the dielectric layer 150, and a plurality of conductive blind holes 152 disposed in the dielectric layer 150, and the conductive blind holes 152 are electrically connected to the circuit layer 151 and the semiconductor chips 12.

[0005] Figure 1B As shown in FIG. 3, the carrier 9 is removed, and a singulation process is performed along a cutting path S as shown in FIG. 4.

[0006] As shown in FIG. 5, the carrier 9 is removed, and a singulation process is performed along a cutting path S as shown in FIG. 4. Figure 1C Figure 1B As shown in FIG. 6, the carrier 9 is removed, and a singulation process is performed along a cutting path S as shown in FIG. 4.

[0007] However, in the manufacturing method of the conventional semiconductor package 1, the semiconductor chips 12 are first embedded in the packaging gel 13, and then the build-up structure 15 is made, so that no underfill is used as a stress buffer mechanism between the build-up structure 15 and the semiconductor chips 12, and thus the build-up structure 15 is prone to stress concentration problems in subsequent processes, causing the build-up structure 15 to crack, as shown by the crack K in FIG. 7, resulting in damage to the circuit layer 151. Figure 1C

[0008] Therefore, how to overcome the above-mentioned problems of the prior art has become a difficult problem to be solved in the industry at present. INVENTION CONTENTS

[0009] ​​​In view of the foregoing deficiencies of the prior art, the present application provides an electronic package, comprising: a cap layer; an electronic element embedded in the cap layer; a wiring structure formed on the cap layer, and the wiring structure comprises an insulating layer disposed on the cap layer, a wiring layer disposed on the insulating layer, and a plurality of first conductive blind vias disposed in the insulating layer, so as to electrically connect the wiring layer and the electronic element; a routing structure formed on the wiring structure, and the routing structure comprises at least one dielectric layer disposed on the insulating layer, at least one routing layer disposed on the dielectric layer, and a plurality of second conductive blind vias disposed in the dielectric layer, and the plurality of second conductive blind vias electrically connect the routing layer and the wiring layer, wherein the first conductive blind vias and the second conductive blind vias are mutually staggered, so as to form a target region in the dielectric layer between the first conductive blind vias and the second conductive blind vias; and a reinforcement blind via formed in the target region of the dielectric layer.

[0010] The present application also provides a method for manufacturing an electronic package, comprising: forming a cap layer on an electronic element, so as to cover the electronic element; forming a wiring structure on the cap layer, wherein the wiring structure comprises an insulating layer disposed on the cap layer, a wiring layer disposed on the insulating layer, and a plurality of first conductive blind vias disposed in the insulating layer, so as to electrically connect the wiring layer and the electronic element; forming a routing structure on the wiring structure, wherein the routing structure comprises at least one dielectric layer disposed on the insulating layer, at least one routing layer disposed on the dielectric layer, and a plurality of second conductive blind vias disposed in the dielectric layer, and the plurality of second conductive blind vias electrically connect the routing layer and the wiring layer, wherein the first conductive blind vias and the second conductive blind vias are mutually staggered, so as to form a target region in the dielectric layer between the first conductive blind vias and the second conductive blind vias; and forming a reinforcement blind via in the target region of the dielectric layer.

[0011] In the foregoing electronic package and method for manufacturing the same, the wiring structure and the routing structure are in the form of a routing redistribution layer (RDL).

[0012] In the foregoing electronic package and method for manufacturing the same, the routing structure comprises a plurality of the dielectric layers. For example, a plurality of the reinforcement blind vias are disposed in different layers of the plurality of the dielectric layers.

[0013] In the foregoing electronic package and method for manufacturing the same, a plurality of the reinforcement blind vias are disposed in a single dielectric layer.

[0014] In the foregoing electronic package and method for manufacturing the same, the reinforcement blind via is located within a vertical projection area of the electronic element.

[0015] In the foregoing electronic package and method for manufacturing the same, the reinforcement blind via is located in the dielectric layer adjacent to the insulating layer.

[0016] The reinforcing blind via, the first conductive blind via and the second conductive blind via are mutually staggered.

[0017] The reinforcing blind via has a geometric planar shape.

[0018] The width of the reinforcing blind via is equal to or less than the width of the wiring layer.

[0019] Therefore, the electronic package and the manufacturing method thereof can avoid the problem of stress concentration of the wiring structure and the circuit structure, and can avoid the problem of cracking of the wiring structure or the circuit structure, so as to avoid damage of the wiring layer or the circuit layer, and to improve the product yield and the product reliability. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figures 1A-1C FIG. 1 is a cross-sectional view of a manufacturing method of a conventional semiconductor package.

[0021] Figures 2A-2D FIG. 3 is a cross-sectional view of a manufacturing method of an electronic package according to an embodiment of the present application.

[0022] Figure 2E FIG. 4 is a cross-sectional view of a subsequent manufacturing process of the electronic package according to the embodiment of the present application. Figure 2D

[0023] FIG. 6 is a partial cross-sectional view of another embodiment of the electronic package according to the embodiment of the present application. Figure 3A Figure 2D FIG. 7 is a partial top view of the electronic package according to the embodiment of the present application.

[0024] Figure 3B Figure 3A FIG. 8 is a partial top view of another embodiment of the electronic package according to the embodiment of the present application.

[0025] Figure 4A FIG. 9 is a partial cross-sectional view of other different embodiments of the electronic package according to the embodiment of the present application. Figure 4B Figure 4C FIG. 10 is a partial top view of other different embodiments of the electronic package according to the embodiment of the present application. Figure 2D

[0026] FIG. 11 is a partial top view of other different embodiments of the electronic package according to the embodiment of the present application. Figure 5A Figure 5B Figure 5C FIG. 12 is a partial top view of other different embodiments of the electronic package according to the embodiment of the present application. Figure 5D Figure 3B

[0027] REFERENCE NUMERALS

[0028] 1 semiconductor package

[0029] 12 semiconductor chip

[0030] ​​​​​​​13 encapsulation gel

[0031] 15 build-up structure

[0032] 150, 250 dielectric layer

[0033] 151, 251 wiring layer

[0034] 152 conductive blind via

[0035] 16 solder bump

[0036] 2 electronic package

[0037] 20 carrier plate

[0038] 200 spacer layer

[0039] 201 bonding layer

[0040] 21, 31, 41, 42, 43 reinforcing blind via

[0041] 22 electronic component

[0042] 22a active surface

[0043] 22b non-active surface

[0044] 220 conductive bump

[0045] 23 cladding layer

[0046] 23a first surface

[0047] 23b second surface

[0048] 24 wiring structure

[0049] 240 insulating layer

[0050] 241 wiring layer

[0051] 242 first conductive blind via

[0052] 25 wiring structure

[0053] 252 second conductive blind via

[0054] 26 conductive component

[0055] 260 bump under metal layer

[0056] 27 insulating protective layer

[0057] 3 electronic device

[0058] 3a upper side

[0059] 3b lower side

[0060] 30 heat sink

[0061] 31 Passive components

[0062] 32 solder balls

[0063] 9 bearing parts

[0064] A Target Area

[0065] B Vertical projection area

[0066] C Middle area

[0067] D,R width

[0068] P peripheral area

[0069] K Crack

[0070] S Cutting path. DETAILED DESCRIPTION

[0071] The following describes the implementation of the present application through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification.

[0072] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of this application. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed in this application without affecting the efficacy and purpose that can be achieved by this application. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of this application. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of this application without substantially changing the technical content.

[0073] Figures 2A-2D It is a cross-sectional schematic diagram of a method for manufacturing the electronic package 2 of the present application.

[0074] like Figure 2A As shown, at least one electronic component 22 is disposed on a carrier board 20 (two electronic components 22 are shown in the drawings of this embodiment), and then a covering layer 23 having a first surface 23a and a second surface 23b opposite to each other is formed on the carrier board 20 to cover the electronic component 22 so that the electronic component 22 is embedded in the covering layer 23.

[0075] The carrier plate 20 can sequentially form a release layer 200 and a bonding layer 201, so that the second surface 23b of the encapsulation layer 23 is combined with the bonding layer 201.

[0076] In this embodiment, the release layer 200 is a thermal release tape, a light-sensitive release film or a mechanical release structure, and the bonding layer 201 is an adhesive material.

[0077] The encapsulation layer 23 is an insulating material, such as a dry film, a packaging adhesive such as epoxy, or a molding compound.

[0078] In this embodiment, the encapsulation layer 23 can be formed on the carrier plate 20 by liquid encapsulation, injection, lamination or compression molding.

[0079] The electronic element 22 is an active element, a passive element or a combination thereof, wherein the active element is a semiconductor chip, and the passive element is a resistor, a capacitor and an inductor.

[0080] In this embodiment, the electronic element 22 is a semiconductor chip having opposite active surface 22a and non-active surface 22b, the active surface 22a has a plurality of electrode pads to combine a plurality of conductive bumps 220, and the non-active surface 22b of the electronic element 22 is combined with the bonding layer 201, and the plurality of conductive bumps 220 are exposed on the first surface 23a of the encapsulation layer 23.

[0081] As shown in Figure 2B A wiring structure 24 is formed on the first surface 23a of the encapsulation layer 23, and the wiring structure 24 includes an insulating layer 240 disposed on the encapsulation layer 23, a wiring layer 241 disposed on the insulating layer 240, and a plurality of first conductive blind holes 242 disposed in the insulating layer 240, so that a plurality of the first conductive blind holes 242 are electrically connected with the wiring layer 241 and the conductive bumps 220 of the electronic element 22.

[0082] In this embodiment, the wiring structure 24 is a redistribution layer (RDL) specification.

[0083] Furthermore, the material of the wiring layer 241 and the first conductive via 242 is copper, and the material of the insulating layer 240 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP).

[0084] As shown in FIG. 1, a wiring structure 24 is formed on the substrate 20, and at least one reinforcing via 21 is formed in the wiring structure 24, wherein the wiring structure 24 comprises at least one dielectric layer 240 disposed on the substrate 20, at least one wiring layer 241 disposed on the dielectric layer 240, and a plurality of first conductive vias 242 disposed in the dielectric layer 240, and the first conductive vias 242 are electrically connected to the wiring layer 241. Figure 2C As shown in FIG. 1, a wiring structure 24 is formed on the substrate 20, and at least one reinforcing via 21 is formed in the wiring structure 24, wherein the wiring structure 24 comprises at least one dielectric layer 240 disposed on the substrate 20, at least one wiring layer 241 disposed on the dielectric layer 240, and a plurality of first conductive vias 242 disposed in the dielectric layer 240, and the first conductive vias 242 are electrically connected to the wiring layer 241.

[0085] In this embodiment, the wiring structure 25 is RDL specification, and the material of the wiring layer 251 and the second conductive via 252 is copper, and the wiring structure 25 comprises a plurality of the dielectric layer 250, and the material of the dielectric layer 250 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP). In addition, the outermost side of the wiring structure 25 can be provided with an insulating protective layer 27 such as green paint, graphite, or the like, and the surface of the outermost side of the wiring layer 251 is exposed to the insulating protective layer 27 for bonding a plurality of conductive elements 26. For example, the conductive elements 26 are C4 specification solder bumps or metal bumps comprising solder material, and before the conductive elements 26 are formed, an under bump metallurgy (UBM) 260 can be formed on the wiring layer 251 to facilitate bonding of the conductive elements 26.

[0086] In addition, the material of the dielectric layer 250 can be the same as that of the insulating layer 240, and the material of the wiring layer 251 and the second conductive via 252 can be the same as that of the wiring layer 241 and the first conductive via 242.

[0087] Furthermore, the first conductive via 242 and the second conductive via 252 are not aligned and are misaligned with each other, so that a target area A is formed in each of the dielectric layers 250 between the first conductive via 242 and the second conductive via 252. For example, the wiring structure 25 defines a middle region C and a peripheral region P surrounding the middle region C, so that the second conductive via 252 is disposed in the peripheral region P and the middle region C, and the target area A is formed in each of the dielectric layers 250 of the peripheral region P.

[0088] Furthermore, the reinforcement blind via 21 is a conductor such as a metal material and is manufactured together with the second conductive blind via 252 , so that the reinforcement blind via 21 is disposed in at least one dielectric layer 250 in the target area A.

[0089] In one embodiment, the number of dielectric layers 250 can be designed according to requirements, such as Figure 2C The second floor shown, or Figure 3A As shown in FIG. 1 , the position of the enhanced blind hole 21 can be configured in any dielectric layer 250 in the target area A as required, for example Figure 2C or Figure 4A The reinforcement blind holes 21, 41 are located in the dielectric layer 250 close to the insulating layer 240, that is, in the dielectric layer 250 adjacent to the insulating layer 240, so as to be as close to the electronic component 22 as possible. The closer to the electronic component 22, the greater the stress of the circuit layer 251, or as shown in FIG. Figure 4C The reinforcement blind via 43 is shown to be located in the middle dielectric layer 250 .

[0090] In addition, the reinforcement blind hole 21 is not aligned with the first conductive blind hole 242 and the second conductive blind hole 252, so the reinforcement blind hole 21, the first conductive blind hole 242 and the second conductive blind hole 252 are misaligned. For example, the width R of the reinforcement blind hole 31 can be equal to (omitted) or less than (e.g. Figure 3B As shown) the width D of the circuit layer 251 is advantageous for staggered configuration, and the plane shape of the reinforced blind holes 21, 31 can be designed according to staggered requirements, such as an ellipse (such as Figure 3B As shown), circular, polygonal (as Figures 5A-5D There are no special restrictions on various geometric shapes such as those shown in the figure.

[0091] like Figure 2D As shown, the carrier plate 20, the release layer 200 and the bonding layer 201 are removed, so that the inactive surface 22b of the electronic component 22 is exposed on the second surface 23b of the covering layer 23. Figure 2C The cutting path S shown is used for the singulation process.

[0092] In this embodiment, the reinforced blind via 21 is located within the vertical projection area B of the electronic component 22 , and preferably located at the edge of the vertical projection area B of the electronic component 22 .

[0093] In addition, if Figure 2E As shown, in the subsequent process, the electronic package 2 can be combined with an electronic device 3 such as a circuit board through the conductive elements 26, wherein the upper side 3a of the electronic device 3 can be configured with the electronic package 2, at least one heat sink 30 and at least one passive component 31, and the lower side 3b of the electronic device 3 can be configured with multiple solder balls 32.

[0094] Therefore, the manufacturing method of the present application disposes the reinforcement blind via 21 in the target area A, so that the reinforcement blind via 21, the first conductive blind via 242, and the second conductive blind via 252 are offset from each other to disperse the stress in the wiring structure 24 and the circuit structure 25. Therefore, compared with the prior art, the electronic package 2 can effectively avoid the problem of stress concentration in the wiring structure 24 and the circuit structure 25, thereby preventing the wiring structure 24 or the circuit structure 25 from cracking, thereby preventing the wiring layer 241 or the circuit layer 25 from being damaged, thereby improving product yield and product reliability.

[0095] It should be understood that the target area A of the circuit structure 25 can be configured with the number of the reinforced blind holes 21 as required, such as Figure 4A As shown in FIG1 , a reinforced blind hole 41 is provided. Figure 4B As shown in FIG. 1 , a plurality of strengthening blind holes 41 and 42 are arranged in the dielectric layer 250 of the same layer. The strengthening blind holes 41 and 43 can even be arranged in the dielectric layers 250 of different layers. Figure 4C shown.

[0096] The present application also provides an electronic package 2, comprising: a covering layer 23, at least one electronic component 22 embedded in the covering layer 23, a wiring structure 24 provided on the covering layer 23, a circuit structure 25 provided on the wiring structure 24, and at least one reinforced blind hole 21, 31, 41, 42, 43 provided in the circuit structure 25.

[0097] The wiring structure 24 includes an insulating layer 240 disposed on the cladding layer 23 , a wiring layer 241 disposed on the insulating layer 240 , and a plurality of first conductive blind vias 242 disposed in the insulating layer 240 , so that the plurality of first conductive blind vias 242 electrically connect the wiring layer 241 and the electronic component 22 .

[0098] The circuit structure 25 includes at least one dielectric layer 250 disposed on the insulating layer 240, at least one circuit layer 251 disposed on the dielectric layer 250, and a plurality of second conductive blind vias 252 disposed in the dielectric layer 250. The plurality of second conductive blind vias 252 electrically connect the circuit layer 251 and the wiring layer 241. The first conductive blind vias 242 and the second conductive blind vias 252 are offset from each other, so that a target area A is formed in the dielectric layer 250 between the first conductive blind vias 242 and the second conductive blind vias 252.

[0099] The reinforced blind vias 21 , 31 , 41 , 42 , and 43 are disposed in the target area A of the dielectric layer 250 .

[0100] In one embodiment, the wiring structure 24 and the circuit structure 25 are of redistribution layer (RDL) specifications.

[0101] In one embodiment, the circuit structure 25 comprises a plurality of the dielectric layers 250. For example, the plurality of the reinforced blind vias 41, 43 are arranged in different layers of the plurality of the dielectric layers 250.

[0102] In one embodiment, the plurality of the reinforced blind vias 41, 42 are arranged in a single one of the dielectric layers 250.

[0103] In one embodiment, the reinforced blind vias 21, 31, 41, 42, 43 are located within a vertical projection area B of the electronic component 22.

[0104] In one embodiment, the reinforced blind vias 41, 42 are arranged in the dielectric layer 250 adjacent to the insulating layer 240, so as to be as close as possible to the electronic component 22.

[0105] In one embodiment, the reinforced blind vias 21, 31, 41, 42, 43, the first conductive blind via 242 and the second conductive blind via 252 are arranged in a staggered manner.

[0106] In one embodiment, the reinforced blind vias 21, 31, 41, 42, 43 have a planar shape of a geometric figure.

[0107] In one embodiment, the width R of the reinforced blind via 21 is equal to or less than the width D of the circuit layer 251.

[0108] In summary, the electronic package and the method of manufacturing the same of the present application can effectively avoid the stress concentration of the wiring structure and the circuit structure, and thus avoid the cracking of the wiring structure or the circuit structure, by arranging the reinforced blind via in the target area to disperse the stress in the wiring structure and the circuit structure.

[0109] The above embodiments are used to exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the claims.

Claims

1. An electronic package, characterized by Comprising: a cap layer; an electronic element embedded in the cap layer; a wiring structure formed on the cap layer, and the wiring structure includes an insulating layer disposed on the cap layer, a wiring layer disposed on the insulating layer, and a plurality of first conductive blind vias disposed in the insulating layer, so that the plurality of first conductive blind vias electrically connect the wiring layer and the electronic element; a circuit structure formed on the wiring structure, and the circuit structure includes at least one dielectric layer disposed on the insulating layer, at least one circuit layer disposed on the dielectric layer, and a plurality of second conductive blind vias disposed in the dielectric layer, and the plurality of second conductive blind vias electrically connect the circuit layer and the wiring layer, wherein the first conductive blind vias and the second conductive blind vias are mutually staggered, so that a target area is formed in the dielectric layer between the first conductive blind vias and the second conductive blind vias; and a reinforcement blind via formed in the target area of the dielectric layer.

2. The electronic package according to claim 1, wherein The wiring structure and the circuit structure are in the specification of a re-distribution layer (RDL).

3. The electronic package of claim 1, wherein, The circuit structure includes a plurality of the dielectric layers.

4. The electronic package of claim 3, wherein, The plurality of reinforcement blind vias are arranged in different layers of the plurality of dielectric layers.

5. The electronic package of claim 1, wherein, A plurality of reinforcement blind vias are arranged in a single dielectric layer.

6. The electronic package of claim 1, wherein, The reinforcement blind via is located in the vertical projection area of the electronic element.

7. The electronic package of claim 1, wherein, The reinforcement blind via is located in the dielectric layer adjacent to the insulating layer.

8. The electronic package of claim 1, wherein, The reinforcement blind via, the first conductive blind via, and the second conductive blind via are mutually staggered.

9. The electronic package of claim 1, wherein, The planar shape of the reinforcement blind via is a geometric shape.

10. The electronic package according to claim 1, wherein The width of the reinforcement blind via is equal to or less than the width of the circuit layer.

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