Chip packaging structure
By electrically connecting the internal chipset to the redistribution layer and encapsulating the entire chip in plastic, the problems of cumbersome chip packaging structure and high production cost in the prior art are solved, and efficient chip packaging production is achieved.
Patent Information
- Application Number
- CN202422921505.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-11-04
- Estimated Expiration
- 2034-11-28
AI Technical Summary
Existing chip packaging structures require the separate fabrication of upper and lower chip layers, resulting in cumbersome processing steps and high production costs.
The internal chipset is electrically connected to the redistribution layer, and the external chips are connected to the redistribution layer through metal pillars. The whole structure is molded into a single structure, simplifying the molding process to a single step.
It enables the simultaneous packaging of different chips, simplifying production steps, reducing production costs, and improving production efficiency.
Smart Images
Figure CN223513952U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to chip packaging technical field especially relates to a chip packaging structure. BACKGROUND
[0002] Chip packaging structure in prior art needs to package different chips into the same structure, because the structure is composed of two layers, the chip in the lower layer and the chip in the upper layer need to be molded respectively, leading to complicated processing steps, relatively low production efficiency, and high production cost.
[0003] Therefore, the applicant develops a chip packaging structure to solve the above problems. UTILITY MODEL CONTENTS
[0004] The utility model provides a chip packaging structure to solve the problem of complicated processing steps and high production cost of prior art chip packaging structure.
[0005] The utility model achieves the above-mentioned purposes through the following technical solutions:
[0006] The utility model discloses a chip packaging structure, which comprises:
[0007] Inner chip group, the inner chip group includes at least one bare chip;
[0008] Rerouting layer, the inner chip group is electrically connected with the top surface of the rerouting layer;
[0009] Outer chip, the bottom surface of the outer chip is connected with the rerouting layer through a metal column, the outer chip, the rerouting layer and the metal column form an installation space, and the inner chip group is arranged in the installation space;
[0010] Plastic packaging structure, the plastic packaging structure integrates the inner chip group, the outer chip, the metal column and the top surface of the rerouting layer.
[0011] Further, the height of the metal column is not less than 150 microns.
[0012] Preferably, the metal column is a copper column.
[0013] Specifically, the outer chip is a logic chip or a storage chip.
[0014] Specifically, the outer chip is a packaged chip or a bare chip.
[0015] Further, the bottom surface of the rerouting layer is connected with a ball grid array.
[0016] Further, the inner chip group is bonded and connected with the rerouting layer through a flip chip method.
[0017] Further, the bare chips in the inner chip group are spaced and laid flat on the redistribution layer.
[0018] Further, the outer chip is connected with the metal column through a reflow welding structure, and the metal column is connected with the redistribution layer through a bonding structure.
[0019] The chip packaging structure has the advantages that:
[0020] The chip packaging structure allows different chips to be simultaneously packaged according to the structure of the lower layer and the upper layer in the production process, and the lower layer chip and the upper layer chip only need to be molded once, so that the structure is simple, the production cost is saved, the production efficiency is improved, and the problems of complicated steps and high production cost of the chip packaging structure in the prior art are solved. BRIEF DESCRIPTION OF DRAWINGS
[0021] Figure 1 The chip packaging structure is a structural schematic diagram.
[0022] In the figure, 1 is an inner chip group, 2 is a redistribution layer, 3 is an outer chip, 4 is a molding structure, 5 is a metal column, and 6 is a ball grid array. DETAILED DESCRIPTION
[0023] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be described clearly and completely in combination with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, rather than all the embodiments. The components of the embodiments of the utility model described and shown in the drawings can be arranged and designed in various different configurations.
[0024] Therefore, the following detailed description of the embodiments of the utility model provided in the drawings is not intended to limit the scope of the claimed utility model, but only represents selected embodiments of the utility model. Based on the embodiments in the utility model, all other embodiments obtained by those of ordinary skill in the art without creative labor belong to the scope of protection of the utility model.
[0025] It should be noted that: similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.
[0026] In the description of the utility model, it needs to be understood that the orientation or position relationship indicated by the terms "upper", "lower", "inner", "outer", "left", "right" and the like is based on the orientation or position relationship shown in the drawings, or is the orientation or position relationship commonly placed when the utility model product is used, or is the orientation or position relationship commonly understood by the person skilled in the art, and is only for the convenience of describing the utility model and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the utility model.
[0027] In addition, the terms "first", "second" and the like are only used for differentiation in description and cannot be understood as indicating or implying relative importance.
[0028] In the description of the utility model, it also needs to be explained that, unless otherwise explicitly specified and limited, the terms "arrange", "connect" and the like should be understood in a broad sense, for example, "connect" can be fixedly connected, or can be detachably connected, or integrally connected; can be mechanically connected, or electrically connected; can be directly connected, or indirectly connected through an intermediate medium, or can be the communication inside two elements. For the person skilled in the art, the specific meaning of the above terms in the utility model can be understood according to the specific circumstances.
[0029] The specific embodiments of the utility model will be described in detail below in combination with the drawings.
[0030] As shown in the figure, a chip packaging structure comprises: Figure 1 An inner chip set 1, the inner chip set 1 comprising at least one bare chip;
[0031] A rewiring layer 2, the inner chip set 1 being electrically connected to the top surface of the rewiring layer 2;
[0032] An outer chip 3, both ends of the bottom surface of the outer chip 3 being connected to the rewiring layer 2 through metal columns 5, the outer chip 3, the rewiring layer 2 and the metal columns 5 forming a mounting space, and the inner chip set 1 being arranged in the mounting space;
[0033] A plastic encapsulation structure 4, the plastic encapsulation structure 4 encapsulating the inner chip set 1, the outer chip 3, the metal columns 5 and the top surface of the rewiring layer 2 into an integrated structure.
[0034] In some embodiments, the height of the metal column 5 is preferably not less than 150 μm.
[0035] In some embodiments, the metal column 5 is preferably a copper column.
[0036]
[0037] In some embodiments, the external chip 3 is preferably a logic chip or a memory chip.
[0038] In some embodiments, the external chip 3 is preferably a packaged chip or a bare chip.
[0039] like Figure 1 As shown, in some embodiments, the bottom surface of the redistribution layer 2 is preferably connected to a ball grid array 6.
[0040] In some embodiments, the internal chipset 1 is preferably bonded to the redistribution layer 2 via a flip-chip method.
[0041] like Figure 1 As shown, in some embodiments, the bare chips in the inner chipset 1 are preferably laid flat on the redistribution layer 2.
[0042] In some embodiments, the external chip 3 is connected to the metal pillar 5 via a reflow soldering structure, and the metal pillar 5 is connected to the redistribution layer 2 via a bonding structure.
[0043] The manufacturing process of this utility model is as follows:
[0044] First, the redistribution layer 2 is fabricated on the substrate using a redistribution layer process. The inner chip assembly 1 is then bonded to the redistribution layer 2 using a flip-chip method. Next, several metal pillars with one end connected to the redistribution layer 2 are fabricated on the upper surface of the redistribution layer 2 using through-hole molding technology. Then, the outer chip 3 is reflow soldered to the metal pillars 5, and the flux is removed. After that, the inner chip assembly 1, the outer chip 3, the metal pillars 5, and the top surface of the redistribution layer 2 are encapsulated into a single structure using a molding compound 4. Then, the upper surface of the molding compound is ground once. Finally, a ball grid array 6 is connected below the redistribution layer 2, thus completing the fabrication process of this utility model.
[0045] The chip packaging structure proposed in this utility model allows for only one molding process during production. It is simple in structure, saves production costs, improves production efficiency, and solves the problems of cumbersome steps and high production costs in the existing chip packaging structure.
[0046] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.
Claims
1. A chip packaging structure, characterized in that, include: An internal chipset, wherein the internal chipset includes at least one bare chip; A redistribution layer, wherein the inner chipset is electrically connected to the top surface of the redistribution layer; An outer chip, the bottom two ends of which are connected to the redistribution layer via metal pillars, the outer chip, the redistribution layer and the metal pillars enclose an installation space, and the inner chip group is disposed within the installation space; A molding compound structure that integrates the inner chipset, the outer chip, the metal pillars, and the top surface of the redistribution layer into a single structure.
2. The chip packaging structure according to claim 1, characterized in that, The height of the metal column is not less than 150 μm.
3. The chip packaging structure according to claim 1, characterized in that, The metal column is a copper column.
4. The chip packaging structure according to claim 1, characterized in that, The external chip is either a logic chip or a memory chip.
5. A chip packaging structure according to claim 1, characterized in that, The external chip is either a packaged chip or a bare chip.
6. A chip packaging structure according to claim 1, characterized in that, The bottom surface of the rewiring layer is connected to a ball grid array.
7. A chip packaging structure according to claim 1, characterized in that, The internal chipset is bonded to the redistribution layer via a flip-chip method.
8. A chip packaging structure according to claim 1, characterized in that, The bare chips in the internal chipset are laid out in a flat, spaced manner on the redistribution layer.
9. A chip packaging structure according to claim 1, characterized in that, The external chip is connected to the metal pillar via a reflow soldering structure, and the metal pillar is connected to the redistribution layer via a bonding structure.