Autonomous controllable standardized distributed station DTU interval unit

Abstract

The utility model discloses an autonomous controllable standardized distributed station DTU interval unit which comprises a main control chip MCU, an FPGA chip and an analog quantity acquisition module. The main control chip MCU and the FPGA chip are connected through a bus to carry out data interaction; the FPGA chip is connected with the analog quantity acquisition module through a bus to access data acquired by the analog quantity acquisition module; the analog quantity acquisition module comprises a mutual inductor module, an operational amplifier module, an ADC sampling module and an electric energy metering module; the output end of the mutual inductor module is connected with the input end of the operational amplifier module and the input end of the electric energy metering module, the output end of the operational amplifier module is connected with the input end of the ADC sampling module, and the output end of the ADC sampling module is connected with the FPGA chip. According to the autonomous controllable standardized distributed station DTU interval unit disclosed by the utility model, the sampling precision is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to power system technical field, concretely is a kind of self-controllable standardization decentralized station DTU interval unit. BACKGROUND

[0002] The standardization design scheme of primary-secondary fusion looped network cabinet and data transmission device (Data Transfer Unit, DTU) proposed by State Grid Operation Inspection Department points out that the terminal standardization scheme of decentralized station, considering the fusion needs of terminal and primary equipment, installs terminal in primary equipment internally, carries out standardization design to decentralized station terminal, and standardizes each group function, performance, interface, structure, supporting equipment of terminal.

[0003] And, switch quantity acquisition circuit includes electric energy metering module and ADC sampling module, currently, the input range of domestic electric energy metering module is between-0.7~0.7V, the input range of ADC sampling module is between-0.5~0.5V.In voltage current is input to mutual inductor, the output range of mutual inductor is between-0.7~0.7V, if the output of mutual inductor is directly connected to electric energy metering module and ADC sampling module, then the sampling precision of ADC sampling module will be reduced, simultaneously, the load of mutual inductor output end increases, and voltage reduction is caused, further reduces the sampling precision of ADC sampling module. SUMMARY

[0004] The technical problem to be solved by the utility model lies in: improve the sampling precision of ADC sampling module of switch quantity acquisition circuit in DTU interval unit.

[0005] To solve the above technical problem, the utility model provides the following technical scheme:

[0006] A self-controllable standardization decentralized station DTU interval unit, including main control chip MCU, FPGA chip and analog quantity acquisition module;Main control chip MCU and FPGA chip are connected through bus to carry out data interaction;

[0007] FPGA chip and analog quantity acquisition module are connected through bus to access the data collected by analog quantity acquisition module;

[0008] Among them, analog quantity acquisition module includes mutual inductor module, operational amplifier module, ADC sampling module, electric energy metering module;The output end of mutual inductor module is connected with the input end of operational amplifier module and electric energy metering module respectively, and the output end of operational amplifier module is connected with the input end of ADC sampling module, and the output end of ADC sampling module is connected with FPGA chip;

[0009] The operational amplifier module comprises an amplifier, resistors R15, R13, R19 and R16; two ends of the resistor R15 are connected with the output end of the mutual inductor module and the inverting input end of the amplifier respectively; the resistor R19 is connected with the non-inverting input end of the amplifier and grounded; two ends of the resistor R13 are connected with the inverting input end and the output end of the amplifier respectively; two ends of the resistor R16 are connected with the output end of the amplifier and the input end of the ADC sampling module.

[0010] In an embodiment of the utility model, mutual inductor module includes mutual inductor T1, resistance R43, R59, R44, common mode inductance TF1 and bidirectional diode D21;

[0011] One end of resistance R43 is connected with three-phase alternating current, and the other end is connected with input end 4 pin of mutual inductor T1;

[0012] One end of resistance R59 is connected with neutral line, and the other end is connected with input end 3 pin of mutual inductor T1;

[0013] Resistance R44 is connected in parallel with the output end of mutual inductor T1;

[0014] 2,4 pins of common mode inductance TF1 input end are connected with 1,2 pins of mutual inductor T1 output end respectively;And, 3 pin of common mode inductance TF1 output end is grounded, and 1 pin is connected with bidirectional diode D21 and then grounded.

[0015] In an embodiment of the utility model, mutual inductor module is provided with 8, and three-phase voltage, three-phase current, zero sequence voltage and zero sequence current are collected respectively.

[0016] In an embodiment of the utility model, corresponding operational amplifier module is provided with 8, and ADC sampling module is provided with 1.

[0017] In an embodiment of the utility model, the front-stage input of ADC sampling module is provided with a first filter module;Wherein, the first filter module comprises a first filter resistor, a second filter resistor and a first filter capacitor;

[0018] One end of the first filter resistor is connected with the output end of the operational amplifier module, and the other end is connected with the first filter capacitor;The first filter capacitor is also connected with the second filter resistor, and the other end of the second filter resistor is grounded.

[0019] In an embodiment of the utility model, the ADC sampling module comprises a sampling chip;

[0020] The connection end of the first filter resistor and the first filter capacitor is connected with the sampling port of the sampling chip, and the connection end of the second filter resistor and the first filter capacitor is connected with the sampling ground port of the sampling chip;

[0021] The analog conversion data port of the sampling chip is connected with the FPGA chip.

[0022] In an embodiment of the utility model, the electric energy metering module includes electric energy metering chip U7, second filter module, and the second filter module is designed with 7; the input end of 7 second filter modules is connected with the output end of the mutual inductor module that gathers three -phase voltage, three -phase current and zero sequence voltage respectively, and the output end of 7 second filter modules is connected with the analog quantity input port of electric energy metering chip U7.

[0023] In an embodiment of the utility model, the second filter module includes third filter resistance, fourth filter resistance, second filter capacitor and third filter capacitor;

[0024] The third filter resistance and second filter capacitor are connected in series, and the third filter resistance end of the series is also connected with the output end of the mutual inductor module, and the third filter resistance and second filter capacitor connection point are connected with the analog quantity input port of electric energy metering chip U7;

[0025] The fourth filter resistance and third filter capacitor are connected in series, and the fourth filter resistance end of the series is also grounded, and the fourth filter resistance and third filter capacitor connection are connected with the analog quantity input port of electric energy metering chip U7;

[0026] Second filter capacitor and third filter capacitor are connected, and grounded at the connection.

[0027] In an embodiment of the utility model, the data port of electric energy metering chip U7 is connected with the data port of main control chip MCU.

[0028] In an embodiment of the utility model, the hardware used in DTU interval unit is all domestic.

[0029] Compared with the prior art, the utility model has the advantages that the output end of the mutual inductor module is divided into two paths, one path is connected with the operational amplifier, so that the output signal is matched with the output range of the ADC sampling module, and a filter circuit is added in the front stage of the ADC sampling module to filter, further improving the signal quality. The other path is connected with the electric energy metering module, and a filter circuit is also added before the electric energy metering module to filter.

[0030] In the embodiment, the inductance value of the common mode inductor in the mutual inductor module is 22uH, the frequency is 50Hz during normal operation, the inductive reactance is small, and there is no influence on the input waveform of the front stage. When there is high-frequency interference in the front stage, the impedance is large at this time, the high-frequency interference cannot be input to the measurement circuit, and the surge fast transient test can be effectively prevented. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 It is a self-controllable standardized decentralized station DTU interval unit schematic diagram of the embodiment of the utility model.

[0032] Figure 2 The schematic diagram of the main control chip MCU of the embodiment of the utility model.

[0033] Figure 3 The schematic diagram of the Ethernet PHY chip of the embodiment of the utility model.

[0034] Fig. 4 (A)~Fig. 4 (F) are the schematic diagram of the FPGA chip of the embodiment of the utility model.

[0035] Figure 5 The schematic diagram of the ESD static protection diode assembly of the embodiment of the utility model.

[0036] Figure 6 The schematic diagram of the network isolation transformer of the embodiment of the utility model.

[0037] Figure 7 The schematic diagram of the switch quantity acquisition module of the embodiment of the utility model.

[0038] Figure 8 The schematic diagram of the terminal row of the embodiment of the utility model.

[0039] Fig. 9 (A) is the schematic diagram of the relay J1A of the embodiment of the utility model.

[0040] Fig. 9 (B) is the schematic diagram of the switch J1B of the embodiment of the utility model.

[0041] Figure 10 The schematic diagram of the analog quantity acquisition module of the embodiment of the utility model.

[0042] Figure 11 The schematic diagram of the mutual inductor module of the embodiment of the utility model.

[0043] Figure 12 The schematic diagram of the operational amplifier module of the embodiment of the utility model.

[0044] Figure 13 The schematic diagram of the first filter module of the embodiment of the utility model.

[0045] Figure 14 The schematic diagram of the sampling chip of the embodiment of the utility model.

[0046] Figure 15 The schematic diagram of the second filter module of the embodiment of the utility model.

[0047] Figure 16 The schematic diagram of the electric energy metering chip of the embodiment of the utility model.

[0048] Figure 17 The schematic diagram of the time synchronization module of the embodiment of the utility model. DETAILED DESCRIPTION

[0049] In order to make the technical scheme of the utility model understood by those skilled in the art, the technical scheme of the utility model will be further described in conjunction with the drawings of the specification.

[0050] The terms "first", "second", "third", etc. are used only for descriptive purposes and should not be construed as implying or suggesting relative importance or an indicated number of the technical features. Therefore, the features with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0051] Referring to Figure 1 As shown in the figure, the utility model provides a kind of autonomous controllable standardization dispersed station DTU spacing unit, including main control chip MCU, FPGA chip, communication module, switch quantity acquisition module, switch quantity output module and analog quantity acquisition module.Communication module, analog quantity acquisition module, switch quantity acquisition module, switch quantity output module and analog quantity acquisition module are connected with main control chip MCU by FPGA chip, and the hardware used in DTU spacing unit is all domestic.

[0052] Referring to Figure 1 And Figure 2 As shown in the figure, in an embodiment of the utility model, main control chip MCU, FPGA chip are as the main hardware architecture of main control module, main control chip MCU selects GD32H759IMK6, and FPGA chip selects PGL22G_FBG256.Main control chip MCU is mainly responsible for operation, control, FPGA chip is mainly responsible for gathering incoming, control outgoing, etc., and main control chip MCU and FPGA chip are connected by bus to carry out data interaction.

[0053] Referring to Figures 1 to 6 As shown in the figure, in the embodiment, communication module includes Ethernet PHY chip U14, network transformer and RJ45 connector. Among them, Ethernet PHY chip U14 uses JLIIII-N032I, and Ethernet PHY chip U14 is connected with RJ45 connector by network transformer.

[0054] In the embodiment, FPGA chip uses multiple, such as Figures 4(A) to 4(F)In the embodiment, the chip labels are U11A~U11F. Among them, the FPGA chip U11D and the FPGA chip U11E are mainly connected with the master control chip MCU. For example, the interfaces defined as FMC-A[0-13] and FMC-D[0-15] in the FPGA chip U11D and U11E are connected with the master control chip MCU, which is a bus interface. Other FPGA chips are mainly connected with, for example, a communication module, an analog quantity acquisition module, a switching quantity acquisition module, a switching quantity output module and an analog quantity acquisition module. For example, the interfaces defined with "PHY0" in the Ethernet PHY chip U14 are connected with the FPGA chip U11C.

[0055] In the embodiment of the utility model, network transformer is the differential signal of preceding stage input is coupled filter with the coil of difference mode coupling to enhance signal, and is coupled to RJ45 connector through electromagnetic field conversion. This makes the Ethernet PHY chip U14 and RJ45 connector have no physical connection, and the direct signal transmission between the two is cut off, so as to achieve the protection purpose. Among them, the network transformer includes ESD static protection diode assembly and network isolation transformer HU2. Among them, the Ethernet PHY chip adopts JLIIII-N032I, and the network isolation transformer HU2 adopts HR641680E.

[0056] In the embodiment, the ESD static protection diode assembly includes ESD static protection diode D18, bidirectional diode D19, D20, capacitor C94, C95, C96 and inductance L6.

[0057] In the embodiment, the 5th pin and the 6th pin of the Ethernet PHY chip U14 are connected with the 1st pin of the input end and the 6th pin of the output end of the ESD static protection diode D18 respectively, and are also connected with the 7th pin and the 8th pin of the network isolation transformer HU2 respectively.

[0058] In the embodiment, the 3rd pin and the 4th pin of the Ethernet PHY chip U14 are connected with the 4th pin of the input end and the 4th pin of the output end of the ESD static protection diode D18 respectively, and are also connected with the 1st pin and the 3rd pin of the network isolation transformer HU2 respectively.

[0059] In the embodiment, the capacitor C94, C95, C96 are connected with the inductance L6 in parallel, and the other end of the inductance L6 is connected with the power supply. The capacitor C94, C95, C96 are also connected with the power supply end of the ESD static protection diode D18 in parallel. The two ends of the bidirectional diode D19 are connected with the 16th pin and the 14th pin of the network isolation transformer HU2 respectively. The two ends of the bidirectional diode D20 are connected with the 11th pin and the 9th pin of the network isolation transformer HU2 respectively.

[0060] Please refer toFigure 7 、 8 As shown in FIGS. 1, 2, 3, 4, 5, 6, 7, 8, and 9, in the embodiment, the switch quantity acquisition module comprises a photocoupler U1, resistors R1, R2, R3, R5, a capacitor C1, a bidirectional diode D1, voltage stabilizing tubes D11 and D12.

[0061] One end of the resistor R2 is connected with the output end of the photocoupler U1, and the other end is connected with the DIFFIO-L0-18 N / D13 port in the FPGA chip U11A; one end of the resistor R1 is connected with the resistor R2 and the input / output end of the photocoupler U1, and the other end is connected with the power supply; one end of the capacitor C1 is connected with the resistor R2, and the other end is connected with the output end of the photocoupler U1 and grounded; the input end of the photocoupler U1 is connected with the bidirectional diode D1 and the resistor R5 in parallel, and the voltage stabilizing tube D11 and the resistor R3 are connected in series, one end of which is connected with the input end of the photocoupler U1, and the other end is connected with the terminal row P1; the positive electrode of the voltage stabilizing tube D12 is connected with the input end of the photocoupler U1, and the negative electrode is connected with the terminal row P1.

[0062] In the embodiment, the front stage of the switch quantity acquisition module mainly comprises the current-limiting resistor R3, the voltage stabilizing tube DI1 and the photocoupler U1; the resistor R5 functions as voltage division; the bidirectional diode D1 prevents the front stage of the photocoupler from being damaged; the voltage stabilizing tube prevents the switch from shaking; and the photocoupler U1 mainly functions as isolation. After the resistor R1 is pulled up in the rear stage, the DI1 signal is high level when it is not conducted; the capacitor C1 can effectively remove the noise, preventing the noise from being introduced into the control chip. The photocoupler U1 adopts the model TLP785GB-S.

[0063] As shown in FIGS. 1, 2, 3, 4, 5, 6, 7, 8, and 9, in the embodiment, the switch quantity acquisition module comprises a photocoupler U1, resistors R1, R2, R3, R5, a capacitor C1, a bidirectional diode D1, voltage stabilizing tubes D11 and D12. Figure 8 In the embodiment, the positive electrode of the diode D10 is connected with the DIFFIO-L0-19 N / D15 port in the FPGA chip U11A, and the negative electrode is connected with the first pin of the relay J1A. The positive electrode of the diode D9 is connected with the 16th pin of the relay J1A, the negative electrode is connected with the first pin of the relay J1A, and the capacitor C8 is connected with the diode D9 in parallel. The two ends of the switch J1B are both connected with the terminal row P1.

[0064] In the embodiment, the relay J1A adopts HFE60 / 24-1HDSTG, and the output current can reach 8A. The diode D9 functions as providing a reactance release loop when the relay J1A returns from action to return. The capacitor C8 functions as providing an energy release loop when the surge fast transient experiment is performed.

[0065] As shown in FIGS. 1, 2, 3, 4, 5, 6, 7, 8, and 9, in the embodiment, the switch quantity acquisition module comprises a photocoupler U1, resistors R1, R2, R3, R5, a capacitor C1, a bidirectional diode D1, voltage stabilizing tubes D11 and D12.

[0066] As shown in FIGS. 1, 2, 3, 4, 5, 6, 7, 8, and 9, in the embodiment, the switch quantity acquisition module comprises a photocoupler U1, resistors R1, R2, R3, R5, a capacitor C1, a bidirectional diode D1, voltage stabilizing tubes D11 and D12.Figures 10 to 16 As shown in the embodiment of the utility model, the analog quantity acquisition module comprises a mutual inductor module, an operational amplifier module, an ADC sampling module and an electric energy metering module. The output end of the mutual inductor module is connected with the input end of the operational amplifier module and the electric energy metering module respectively, and the output end of the operational amplifier module is connected with the input end of the ADC sampling module, and the output end of the ADC sampling module is connected with the FPGA chip.

[0067] In the embodiment, the mutual inductor module comprises a mutual inductor T1, resistors R43, R59, R44, a common mode inductor TF1 and a bidirectional diode D21. One end of the resistor R43 is connected with three-phase alternating current, and the other end is connected with the input end 4 pin of the mutual inductor T1. One end of the resistor R59 is connected with the neutral line, and the other end is connected with the input end 3 pin of the mutual inductor T1; the resistor R44 is connected in parallel with the output end of the mutual inductor T1. The 2 and 4 pins of the input end of the common mode inductor TF1 are connected with the 1 and 2 pins of the output end of the mutual inductor T1 respectively. The 3 pin of the output end of the common mode inductor TF1 is grounded, and the 1 pin is connected with the bidirectional diode D21 and then grounded. In the embodiment, eight mutual inductor modules are arranged to acquire three-phase voltage, three-phase current, zero sequence voltage and zero sequence current respectively. Figure 11 Taking the UA phase voltage in the three-phase voltage as an example.

[0068] In the embodiment, the mutual inductor T1 adopts ZMPT107, the front-stage resistors R43 and R59 are voltage dividing resistors, and the input voltage is converted into small current through the voltage dividing resistors. The rear-stage circuit mutual inductor T1 and the resistor R44 form a loop to convert the current into voltage. The inductance value of the common mode inductor TF1 is 22uH, the normal working frequency is 50Hz, the inductive reactance is small, and the front-stage input waveform is not affected. When high-frequency interference exists in the rear stage, the impedance is large, the high-frequency interference cannot be input to the measurement circuit, and the surge fast transient test can be effectively prevented.

[0069] In the embodiment, the operational amplifier module comprises an amplifier, resistors R15, R13, R19 and R16. The two ends of the resistor R15 are respectively connected with the output end of the mutual inductor module and the reverse input end of the amplifier. The resistor R19 is connected with the same-phase input end of the amplifier and then grounded. The two ends of the resistor R13 are respectively connected with the reverse input end and the output end of the amplifier. The two ends of the resistor R16 are respectively connected with the output end of the amplifier and the input end of the ADC sampling module. In the embodiment, eight corresponding operational amplifier modules are arranged with the eight mutual inductor modules.

[0070] In the embodiment, the front-stage input of the ADC sampling module is provided with a first filter module. The first filter module comprises a first filter resistor, a second filter resistor and a first filter capacitor.

[0071] One end of the first filter resistor is connected to the output terminal of the operational amplifier module, and the other end is connected to the first filter capacitor; the first filter capacitor is also connected to the second filter resistor, and the other end of the second filter resistor is grounded.

[0072] Referring to Figure 13 As shown in the figure, the first filter resistor has RR1, RR3, RR5, RR7, RR9, RR11, RR13, and RR15, the second filter resistor has RR2, RR4, RR6, RR8, RR10, RR12, RR14, and RR16, and the first filter capacitor has CC1, CC2, CC3, CC4, CC5, CC6, CC7, and CC8.

[0073] In this embodiment, the first filter module is also provided with 8.

[0074] In this embodiment, the ADC sampling module includes a sampling chip, and the connection ends of the first filter resistor and the first filter capacitor are connected to the sampling port of the sampling chip, and the connection ends of the second filter resistor and the first filter capacitor are connected to the sampling ground port of the sampling chip, as Figure 14 In this embodiment, the 49th to 64th pins of the sampling chip are connected to the analog conversion data port of the FPGA chip, wherein the analog conversion data port of the sampling chip is as Figure 14 In this embodiment, the 16th to 33rd pins of the sampling chip are connected to the FPGA chip U11F. In this embodiment, the ADC sampling module is provided with 1, the sampling chip uses BL1082, and the sampling rate is as high as 200ksps. The analog quantity input by the front stage is filtered by the first filter module and then input to the sampling chip, and the FPGA chip accesses the data of the sampling chip in a bus mode.

[0075] In this embodiment, the electric energy metering module includes an electric energy metering chip U7 and a second filter module. The second filter module is designed to have 7, the input ends of the 7 second filter modules are respectively connected to the output ends of the 7 mutual inductor modules, the 7 mutual inductor modules are respectively mutual inductor modules for collecting three-phase voltage, three-phase current, and zero sequence voltage, and the output ends of the 7 second filter modules are connected to the analog quantity input port of the electric energy metering chip U7.

[0076] In this embodiment, the second filter module includes a third filter resistor, a fourth filter resistor, a second filter capacitor, and a third filter capacitor.

[0077] In this embodiment, the third filter resistor is connected in series with the second filter capacitor. The third filter resistor is also connected to the output terminal of the current transformer module. The connection point between the third filter resistor and the second filter capacitor is connected to the analog input port of the energy metering chip U7. A fourth filter resistor is connected in series with the third filter capacitor. The fourth filter resistor is also grounded, and the connection point between the fourth filter resistor and the third filter capacitor is connected to the analog input port of the energy metering chip U7. The second and third filter capacitors are connected and grounded at their connection point. Figure 15 As shown, in the second filter module, the third filter resistors are such as RR17, RR21, RR25, RR29R, R18R, R22, RR26, and the second filter capacitors are such as CC9, CC13, CC21, CC10, CC14, CC18. Figure 15 In the diagram, the remaining resistor is the fourth filter resistor, and the remaining capacitor is the third filter capacitor. Undoubtedly, the third and fourth filter resistors use the same specifications, as do the second and third filter capacitors.

[0078] In this embodiment, the energy metering chip U7 uses an ATT7022EU-N. It calculates active and reactive energy based on the input three-phase current, voltage, zero-sequence voltage, and zero-sequence current. The analog input port of the energy metering chip U7 is as follows: Figure 16 In the diagram, pins 3, 4, 6, 7, 9, 10, 13, 14, 16, 17, 19, 20, 21, and 22 of the power metering chip U7 are used. The data ports of the power metering chip U7 are connected to the data ports of the main control chip MCU, specifically pins 35 to 38. Correspondingly, the data ports of the main control chip MCU are PE14, PE12, PE16, and PE15.

[0079] Please see Figure 17 As shown, in one embodiment of this utility model, the autonomous and controllable standardized distributed station DTU bay unit further includes a time synchronization module. The time synchronization module includes isolator US1, resistors RS1, RS2, RS3, RS4, capacitors CS1, CS2, TVS diodes DS1, DS2, DS3, and resettable fuses FS1, FS2.

[0080] In the embodiment, one end of the resistor RS2 is connected with the 5th pin of the isolator US1, and the other end is connected with the power supply. One end of the resistor RS3 is connected with the 3rd pin of the isolator US1, and the other end is connected with the power supply. In addition, the 3rd pin of the isolator US1 is also connected with the DIFFIO-I2-15-N / L-DQSL-N port in the FPGA chip U11C. One end of the resistor RS1 is connected with the 13th pin of the isolator US1, and the other end is connected with the ground. One end of the resistor RS4 is connected with the 12th pin of the isolator US1, and the other end is connected with the ground. One end of the capacitor CS1 is connected with the 1st pin of the isolator US1, and the other end is connected with the ground. One end of the capacitor CS2 is connected with the 16th pin of the isolator US1, and the other end is connected with the ground. The 1st port of the TVS diode DS1 is connected with the 13th pin of the isolator US1, and the 2nd port is connected with the 12th pin of the isolator US1. The TVS diode DS2 is connected with the TVS diode DS1 in parallel. One end of the TVS diode DS3 is connected with the 12th pin of the isolator US1, and the 2nd port is connected with the ground. One end of the self-resetting fuse FS1 is connected with the 13th pin of the isolator US1, and the other end is connected with the terminal row P1. One end of the self-resetting fuse FS2 is connected with the 12th pin of the isolator US1, and the other end is connected with the terminal row P1.

[0081] In the embodiment, the isolator US1 adopts CA-IS3088WX to convert the differential signal into a TTL level, the TVS diode adopts SMBJ6.0CA, and the TVS diodes DS1 and DS3 prevent the single-end input voltage from being too large.

[0082] In the embodiment, the self-controllable standardized distributed station DTU spacing unit further comprises a man-machine interaction module mainly composed of a key, a liquid crystal display module and an LED lamp, which is used to realize the operation of reading device information and the like. In the embodiment, no limitation is made.

[0083] It is obvious for those skilled in the art that the utility model is not limited to the details of the above-mentioned exemplary embodiments, and can be realized in other specific forms without departing from the spirit or basic characteristics of the utility model. Therefore, the embodiments should be regarded as exemplary and non-limiting from any point of view, and the scope of the utility model is defined by the appended claims rather than the above description, and therefore all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the utility model, and any reference signs in the claims should not be regarded as limiting the claims.

[0084] The above-described embodiments only represent the implementation manners of the utility model, and the protection scope of the utility model is not limited to the above-described embodiments, and for those skilled in the art, under the premise of not departing from the concept of the utility model, a plurality of modifications and improvements can be made, and these all belong to the protection scope of the utility model.

Claims

1. An autonomously controllable standardized distributed station (DTU) spacing unit, characterized by The device comprises a master chip MCU, an FPGA chip and an analog quantity acquisition module; the master chip MCU and the FPGA chip are connected through a bus for data interaction; the FPGA chip and the analog quantity acquisition module are connected through a bus to access data collected by the analog quantity acquisition module; The analog quantity acquisition module comprises a mutual inductor module, an operational amplifier module, an ADC sampling module and an electric energy metering module; the output end of the mutual inductor module is connected with the input end of the operational amplifier module and the electric energy metering module respectively, and the output end of the operational amplifier module is connected with the input end of the ADC sampling module, and the output end of the ADC sampling module is connected with the FPGA chip; The operational amplifier module comprises an amplifier, resistors R15, R13, R19 and R16; the two ends of the resistor R15 are connected with the output end of the mutual inductor module and the inverting input end of the amplifier respectively; the resistor R19 is connected with the non-inverting input end of the amplifier and grounded; the two ends of the resistor R13 are connected with the inverting input end and the output end of the amplifier respectively; the two ends of the resistor R16 are connected with the output end of the amplifier and the input end of the ADC sampling module.

2. The autonomously controllable standardized distributed station (DTU) spacing unit according to claim 1, characterized in that The mutual inductor module comprises a mutual inductor T1, resistors R43, R59, R44, a common-mode inductor TF1 and a bidirectional diode D21; One end of the resistor R43 is connected with three-phase alternating current, and the other end is connected with the input end 4 of the mutual inductor T1; One end of the resistor R59 is connected with a neutral line, and the other end is connected with the input end 3 of the mutual inductor T1; The resistor R44 is connected in parallel with the output end of the mutual inductor T1; The 2 and 4 pins of the input end of the common-mode inductor TF1 are connected with the 1 and 2 pins of the output end of the mutual inductor T1 respectively, and the 3 pin of the output end of the common-mode inductor TF1 is grounded, and the 1 pin is connected with the bidirectional diode D21 and grounded.

3. The autonomously controllable standardized distributed station (DTU) spacing unit according to claim 2, characterized in that There are eight mutual inductor modules, which are used to collect three-phase voltage, three-phase current, zero sequence voltage and zero sequence current respectively.

4. The autonomously controllable standardized distributed station (DTU) spacing unit according to claim 3, characterized in that There are eight corresponding operational amplifier modules, and one ADC sampling module.

5. The autonomously controllable standardized distributed station (DTU) spacing unit according to claim 1, characterized in that The front-stage input of the ADC sampling module is provided with a first filter module; the first filter module comprises a first filter resistor, a second filter resistor and a first filter capacitor; One end of the first filter resistor is connected with the output end of the operational amplifier module, and the other end is connected with the first filter capacitor; the first filter capacitor is further connected with the second filter resistor, and the other end of the second filter resistor is grounded.

6. The autonomously controllable standardized distributed station (DTU) spacing unit according to claim 5, characterized in that The ADC sampling module comprises a sampling chip; The connection ends of the first filter resistor and the first filter capacitor are connected with the sampling port of the sampling chip, and the connection ends of the second filter resistor and the first filter capacitor are connected with the sampling grounding port of the sampling chip; The analog conversion data port of the sampling chip is connected with the FPGA chip.

7. The autonomously controllable standardized distributed station (DTU) spacing unit according to claim 3, characterized in that The electric energy metering module comprises an electric energy metering chip U7 and a second filter module; and the second filter module is designed with seven; the input ends of the seven second filter modules are connected with the output ends of the mutual inductor modules for collecting three-phase voltage, three-phase current and zero sequence voltage respectively; and the output ends of the seven second filter modules are connected with the analog quantity input port of the electric energy metering chip U7.

8. The autonomously controllable standardized distributed station (DTU) spacing unit according to claim 7, characterized in that The second filter module comprises a third filter resistor, a fourth filter resistor, a second filter capacitor and a third filter capacitor; The third filter resistor is connected with the second filter capacitor in series, and the end of the third filter resistor in series is also connected with the output end of the mutual inductor module; the connection point of the third filter resistor and the second filter capacitor is connected with the analog quantity input port of the electric energy metering chip U7; The fourth filter resistor is connected with the third filter capacitor in series, and the end of the fourth filter resistor in series is also connected with the ground; the connection point of the fourth filter resistor and the third filter capacitor is connected with the analog quantity input port of the electric energy metering chip U7; The second filter capacitor and the third filter capacitor are connected, and the connection point is connected with the ground.

9. The autonomously controllable standardized distributed station (DTU) spacing unit according to claim 7, characterized in that The data port of the electric energy metering chip U7 is connected with the data port of the main control chip MCU.

10. The autonomously controllable standardized distributed station (DTU) spacing unit according to claim 1, characterized in that The hardware used in the DTU interval unit is all domestic.

Images