LED chip

Abstract

The utility model provides an LED chip which is provided with an epitaxial lamination unit, and the epitaxial lamination unit at least comprises a first type semiconductor layer, an active region and a second type semiconductor layer which are sequentially laminated on a substrate from bottom to top. Wherein the edge area of the upper surface of the second type semiconductor layer is provided with a concave-convex microstructure, and the microstructure can be used as a nucleation point in the forming process of the insulating protection layer, so that the compactness and the adhesion of the insulating protection layer are improved, stress concentration of the edge area of the upper surface of the LED chip is relieved, and the moisture-proof capability of the LED chip is improved; and the reliability of the LED chip is further improved.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the technical field of semiconductor device manufacturing, more specifically, it relates to a LED chip. BACKGROUND

[0002] In the current LED chip product, the commonly used passivation layer is single-layer silicon oxide. Because of its low cost, simple manufacturing method and ideal refractive index, it is widely used. With the smaller and smaller size of LED chips and the wider and wider application field, the water vapor resistance of various products to LED chips is required higher and higher, especially like vehicle-mounted LED chips.

[0003] In order to improve the water vapor resistance of LED chip, the current conventional method is to deposit a layer of silicon oxide as passivation layer by PECVD (chemical vapor deposition method) technology to prevent water vapor from entering, but the inventor found that there is still stress concentration in the edge area of the upper surface of the LED chip, which is easy to be eroded by water vapor, resulting in low reliability of the LED chip. UTILITY MODEL CONTENT

[0004] Therefore, the utility model provides a LED chip to solve the problem of stress concentration in the edge area of the upper surface of the LED chip in the prior art, which is easy to be eroded by water vapor, resulting in low reliability of the LED chip.

[0005] To achieve the above-mentioned purpose, the utility model adopts the following technical scheme:

[0006] A LED chip, comprising a substrate and a plurality of LED light emitting units arranged on the surface of the substrate and spaced apart by a cutting channel, characterized in that the LED light emitting unit comprises:

[0007] An epitaxial layer unit is arranged on the surface of the substrate, and the epitaxial layer unit comprises at least a first type semiconductor layer, an active region and a second type semiconductor layer stacked on the substrate in turn from bottom to top; the epitaxial layer unit has a groove exposing part of the first type semiconductor layer on the side away from the substrate; wherein a concave-convex microstructure is arranged on the edge area of the upper surface of the second type semiconductor layer;

[0008] A first electrode and a second electrode are arranged on the epitaxial layer unit: the first electrode is arranged at the bottom of the groove and forms an electrical connection with the first type semiconductor layer, and is insulated from the sidewall of the groove; the second electrode is arranged on the side of the second type semiconductor layer away from the active region and forms an electrical connection with the second type semiconductor layer, and the first electrode and the second electrode are arranged away from each other;

[0009] An insulating protective layer covers the microstructure and the exposed surface of the epitaxial stack unit, and exposes the first electrode and the second electrode.

[0010] Preferably, the roughness of the microstructure is not greater than 0.5 μm.

[0011] Preferably, the microstructure occupies 0-3% of the area of the upper surface of the second-type semiconductor layer, excluding the end point.

[0012] Preferably, the microstructure extends at least to the sidewall of the second-type semiconductor layer.

[0013] Preferably, the sidewall of the epitaxial stack unit forms a mesa structure through the exposed portion of the first-type semiconductor layer; and a concave-convex microstructure is provided in the edge region of the mesa structure.

[0014] Preferably, the microstructure occupies 0-3% of the area of the surface of the mesa structure, excluding the end point.

[0015] Preferably, the microstructure extends from the surface of the mesa structure to the sidewall of the mesa structure.

[0016] Preferably, the starting layer of the insulating protective layer comprises an aluminum oxide layer, and the aluminum oxide layer forms an island structure on the microstructure in an atomic layer deposition manner.

[0017] Preferably, the insulating protective layer further comprises a first passivation layer, a reflective layer and a second passivation layer which are sequentially stacked on the aluminum oxide layer.

[0018] Preferably, the epitaxial stack further comprises a transparent conductive layer, a first pad and a second pad; wherein the transparent conductive layer is provided on the side surface of the second-type semiconductor layer away from the active region, and the second electrode is deposited on the surface of the transparent conductive layer or embedded in the transparent conductive layer in a first via hole to form a connection with the second-type semiconductor layer.

[0019] and the insulating protective layer has a second via hole exposing the first electrode and a third via hole exposing the second electrode;

[0020] The first pad forms an electrical connection with the first electrode through the second via hole, the second pad forms an electrical connection with the second electrode through the third via hole, and the first pad and the second pad are arranged in a spaced manner.

[0021] The above technical solution achieves the following effects:

[0022] 1. The LED chip is provided by the utility model, through setting up epitaxial laminated unit, epitaxial laminated unit at least includes: first type semiconductor layer, active region and second type semiconductor layer are sequentially laminated on the substrate from below to above;Wherein, the edge area on the upper surface of second type semiconductor layer is provided with the concave-convex microstructure, the microstructure can be as the nucleation point of insulating protective layer formation process, to improve the compactness and adhesion of insulating protective layer, it is favorable to alleviate the stress concentration of the edge area on the upper surface of LED chip to improve the waterproof capacity of LED chip, and then improve the reliability of LED chip.

[0023] 2, further, by setting the roughness of microstructure is not more than 0.5 μm, to make the compactness and adhesion of insulating protective layer formed on microstructure higher, further improve the waterproof capacity of LED chip.

[0024] 3, further, by setting microstructure at least extends to the sidewall of second type semiconductor layer, the microstructure of the edge area on the upper surface of second type semiconductor layer coincides with the microstructure of the sidewall of second type semiconductor layer, it is favorable to alleviate the stress concentration at the corner of LED chip, further improve the waterproof capacity of LED chip.

[0025] 4, further, by setting the sidewall of epitaxial laminated unit forms mesa structure through exposed part first type semiconductor layer;The edge area of mesa structure is provided with the concave-convex microstructure, the microstructure can be as the nucleation point of insulating protective layer formation process, to improve the compactness and adhesion of insulating protective layer at the sidewall of epitaxial laminated unit, and then improve the waterproof capacity of LED chip.

[0026] 5, further, by setting microstructure extends from the surface of mesa structure to the sidewall of mesa structure, the microstructure of the edge area of mesa structure coincides with the microstructure of the sidewall of mesa structure, it is favorable to alleviate the stress concentration at the corner of the sidewall of epitaxial laminated unit, further improve the compactness and adhesion of insulating protective layer at the sidewall of epitaxial laminated unit, and then improve the waterproof capacity of LED chip.

[0027] 6, further, by setting the starting layer of insulating protective layer includes aluminum oxide layer, microstructure is more conducive to the island-like structure of aluminum oxide layer to be formed on microstructure in atomic layer deposition mode, to make the compactness of aluminum oxide layer formation, can alleviate the stress of aluminum oxide layer on epitaxial laminated unit, further improve the compactness and adhesion of insulating protective layer. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical scheme in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only constitute the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained on the premise of not paying creative labor according to the provided drawings.

[0029] Figure 1 A structure schematic diagram of an LED chip provided by the embodiment of the present application is shown in the figure.

[0030] Figure 2 A structure schematic diagram of another LED chip provided by the embodiment of the present application is shown in the figure.

[0031] Figure 3 A structure schematic diagram of another LED chip provided by the embodiment of the present application is shown in the figure.

[0032] Figure 4 A structure schematic diagram of another LED chip provided by the embodiment of the present application is shown in the figure.

[0033] Figure 5 A structure schematic diagram of another LED chip provided by the embodiment of the present application is shown in the figure.

[0034] Figure 6 A flow chart of a manufacturing method of an LED chip provided by the embodiment of the present application is shown in the figure.

[0035] Figures 7 to 10 A process sectional view corresponding to each step of the manufacturing method shown in the figure. Figure 6

[0036] A process sectional view corresponding to each step of the manufacturing method of the first photoetching is shown in the figure. Figures 11 to 14

[0037] A process sectional view corresponding to each step of the manufacturing method of the second photoetching is shown in the figure. Figures 15 to 19 Explanation of symbols in the figure:

[0038]

[0039] ​1, substrate; 2, epitaxial layer unit; 21, first type semiconductor layer; 22, active region; 23, second type semiconductor layer; 24, groove; 3, first electrode; 4, second electrode; 5, insulating protective layer; 51, aluminum oxide layer; 52, first passivation layer; 53, reflective layer; 54, second passivation layer; 6, transparent conductive layer; 7, first pad; 8, second pad; 9, first photoresist; 10, first photoetching pattern; 11, second photoresist; 12, second photoetching pattern; A, cutting path preset area; B, cutting path; C, sawtooth; D, microstructure; T, table structure; S1, area of microstructure on sidewall of groove; S2, area of sidewall of groove; S3, area of microstructure on sidewall of epitaxial layer unit; S4, area of sidewall of epitaxial layer unit. DETAILED DESCRIPTION

[0040] To make the content of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work belong to the scope of protection of the present application.

[0041] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced without the specific details that are set forth in the following description, in other manners different from those described herein, and it can be apparent to those skilled in the art that the present application is not limited to the embodiments disclosed in the following description.

[0042] Secondly, the present application is described in detail in combination with the schematic diagram. In the detailed description of the embodiments of the present application, the cross-sectional view of the device structure is locally enlarged without the general proportion for the convenience of description, and the schematic diagram is only an example, which should not limit the scope of protection of the present application herein. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual manufacture.

[0043] The embodiments of the present application provide an LED chip, as shown in the drawings, which comprises a substrate 1 and a plurality of LED light emitting units (only one is shown in the drawings) arranged on the surface of the substrate 1 and spaced from each other by cutting paths B. Figure 1 The LED light emitting unit comprises: Figure 1

[0044] ​An epitaxial stack unit 2 is arranged on the surface of the substrate 1, and the epitaxial stack unit 2 at least comprises: a first-type semiconductor layer 21, an active region 22 and a second-type semiconductor layer 23 which are sequentially stacked on the substrate 1 from bottom to top; a groove 24 with a part of the first-type semiconductor layer 21 exposed is arranged on the side of the epitaxial stack unit 2 away from the substrate 1; and a microstructure D in relief is arranged on the edge region of the upper surface of the second-type semiconductor layer 23.

[0045] A first electrode 3 and a second electrode 4 are arranged on the epitaxial stack unit 2: the first electrode 3 is arranged at the bottom of the groove 24 and forms an electrical connection with the first-type semiconductor layer 21, and is arranged in insulation with the sidewall of the groove 24; the second electrode 4 is arranged on the side of the second-type semiconductor layer 23 away from the active region 22 and forms an electrical connection with the second-type semiconductor layer 23, and the first electrode 3 and the second electrode 4 are arranged away from each other.

[0046] An insulating protective layer 5 covers the microstructure D and the exposed surface of the epitaxial stack unit 2, and exposes the first electrode 3 and the second electrode 4.

[0047] The specific type of the substrate 1 is not limited in the embodiment, and the substrate 1 can be a semiconductor substrate such as a sapphire substrate, a silicon substrate or a silicon carbide substrate, and the specific material of the substrate 1 can be selected according to requirements.

[0048] It should be noted that the specific doping type of the first-type semiconductor layer 21 and the second-type semiconductor layer 23 is not limited in the embodiment, the doping type of the first-type semiconductor layer 21 is opposite to that of the second-type semiconductor layer 23, the first-type semiconductor layer 21 can be a P-type semiconductor layer or an N-type semiconductor layer, and the N-type semiconductor layer and the P-type semiconductor layer can be GaN or Al GaN.

[0049] Optionally, in the embodiment, the groove 24 has a structure of wide at the top and narrow at the bottom, and the sidewall of the groove 24 is an inclined sidewall.

[0050] Optionally, in the embodiment, the epitaxial stack unit 2 has a structure of narrow at the top and wide at the bottom, and the sidewall of the epitaxial stack unit 2 is an inclined sidewall.

[0051] On the basis of the above embodiment, in an embodiment of the present application, the roughness of the microstructure D is not greater than 0.5 μm.

[0052] On the basis of the above embodiment, in an embodiment of the present application, as shown in Figure 2 the microstructure D at least extends to the sidewall of the second-type semiconductor layer 23.

[0053] On the basis of the above embodiment, in an embodiment of the present application, the microstructure D accounts for 0%-3% of the area of the upper surface of the second-type semiconductor layer 23, and the end point value is not included.

[0054] On the basis of the above-mentioned embodiments, in an embodiment of the present application, the microstructure accounts for an area S1 of the side wall of the groove, and the area of the side wall of the groove is S2, then, 0 < S1≤ S2.

[0055] On the basis of the above-mentioned embodiments, in an embodiment of the present application, the microstructure accounts for an area S3 of the side wall of the epitaxial stack unit, and the area of the side wall of the epitaxial stack unit is S4, then, 0 < S3≤ S4.

[0056] On the basis of the above-mentioned embodiments, in an embodiment of the present application, as shown in Figure 3 , the side wall of the epitaxial stack unit 2 forms a table-shaped structure T through the exposed first-type semiconductor layer 21; and the microstructure D in relief is arranged at the edge region of the table-shaped structure T.

[0057] On the basis of the above-mentioned embodiments, in an embodiment of the present application, the microstructure D accounts for 0%-3% of the area of the surface of the table-shaped structure T, and the end point value is not included.

[0058] On the basis of the above-mentioned embodiments, in an embodiment of the present application, as shown in Figure 4 , the microstructure D extends from the surface of the table-shaped structure T to the side wall of the table-shaped structure T.

[0059] On the basis of the above-mentioned embodiments, in an embodiment of the present application, referring to Figure 4 , the starting layer of the insulating protective layer 5 includes an aluminum oxide layer 51, and the aluminum oxide layer 51 forms an island-shaped structure on the microstructure D in the form of atomic layer deposition.

[0060] On the basis of the above-mentioned embodiments, in an embodiment of the present application, continuing to refer to Figure 4 , the insulating protective layer 5 further includes a first passivation layer 52, a reflective layer 53 and a second passivation layer 54 which are sequentially stacked on the aluminum oxide layer 51.

[0061] Optionally, in the embodiment, the materials of the first passivation layer 52 and the second passivation layer 54 include but are not limited to one or more of silicon oxide and silicon nitride.

[0062] Optionally, in the embodiment, the reflective layer 53 includes a DBR structure.

[0063] It should be noted that, in the embodiment, the DBR structure is a periodic structure formed by alternately stacking two materials with different refractive indexes in the form of ABAB, wherein the high-refractive-index layer can adopt a Ti3O5 layer, and the low-refractive-index layer can adopt a SiO2 layer; and the number of periods of the DBR structure is not specifically limited and can be set according to actual needs.

[0064] On the basis of the above-mentioned embodiments, in an embodiment of the present application, as shown in Figure 5As shown, the epitaxial stack further comprises a transparent conductive layer 6, a first pad 7 and a second pad 8; wherein the transparent conductive layer 6 is arranged on the side surface of the second-type semiconductor layer 23 away from the active region 22, and the second electrode 4 is deposited on the surface of the transparent conductive layer 6 or embedded in the transparent conductive layer 6 through the first through hole to form a connection with the second-type semiconductor layer 23;

[0065] The insulating protective layer 5 has a second through hole exposing the first electrode 3 and a third through hole exposing the second electrode 4;

[0066] The first pad 7 forms an electrical connection with the first electrode 3 through the second through hole, the second pad 8 forms an electrical connection with the second electrode 4 through the third through hole, and the first pad 7 and the second pad 8 are arranged at intervals.

[0067] The embodiment of the present application further provides a manufacturing method of an LED chip, as shown in the accompanying drawings, Figure 6 The manufacturing method of the LED chip comprises the following steps:

[0068] As shown in the accompanying drawings, Figure 7 A substrate 1 is provided, and an epitaxial stack is stacked on the substrate 1, wherein the epitaxial stack at least comprises: a first-type semiconductor layer 21, an active region 22 and a second-type semiconductor layer 23 which are sequentially stacked in the direction away from the substrate 1;

[0069] In the embodiment, the specific type of the substrate 1 is not limited, and the substrate 1 can be a semiconductor substrate such as a sapphire substrate, a silicon substrate or a silicon carbide substrate, and the specific material of the substrate 1 can be selected and used according to requirements.

[0070] It should be noted that the specific doping type of the first-type semiconductor layer 21 and the second-type semiconductor layer 23 is not limited in the embodiment, the doping type of the first-type semiconductor layer 21 is opposite to that of the second-type semiconductor layer 23, the first-type semiconductor layer 21 can be a P-type semiconductor layer or an N-type semiconductor layer, and the N-type semiconductor layer and the P-type semiconductor layer can be GaN or Al GaN.

[0071] As shown in the accompanying drawings, Figure 8 The epitaxial stack is etched by a first photoetching to form a cutting path preset area A and a groove 24, the cutting path preset area A and the groove 24 respectively expose the corresponding first-type semiconductor layer 21; at the same time, a concave-convex microstructure D is formed on the edge area of the upper surface of the second-type semiconductor layer 23;

[0072] As shown in the accompanying drawings, Figure 9 The epitaxial stack is etched by a second photoetching to form a plurality of epitaxial stack units 2 arranged at intervals through a cutting path B, and the cutting path B exposes the surface of the substrate 1;

[0073] It should be noted that the embodimentFigure 9 Only one epitaxial stack unit 2 is shown in the figure, which corresponds to one LED light emitting unit. It can be understood that there are many epitaxial stack units in one epitaxial stack, as shown in the figure. Figure 9 The epitaxial stack unit 2 is shown in the figure.

[0074] Step S400, as shown in the figure, a first electrode 3 and a second electrode 4 are made on each epitaxial stack unit 2 to form several LED light emitting units (only one is shown in the figure); the first electrode 3 is arranged at the bottom of the groove 24 and forms an electrical connection with the first-type semiconductor layer 21, and is arranged to be insulated from the side wall of the groove 24; the second electrode 4 is arranged on the side of the second-type semiconductor layer 23 away from the active region 22 and forms an electrical connection with the second-type semiconductor layer 23, and the first electrode 3 and the second electrode 4 are arranged to be far away from each other. Figure 10 Figure 10 Step S500, as shown in the figure, an insulating protective layer 5 is made, which covers the microstructure D and the exposed surface of each epitaxial stack unit 2, and exposes the first electrode 3 and the second electrode 4.

[0075] Step S500, as shown in the figure, an insulating protective layer 5 is made, which covers the microstructure D and the exposed surface of each epitaxial stack unit 2, and exposes the first electrode 3 and the second electrode 4. Figure 1 Optionally, in the embodiment, the groove 24 has a structure of wide at the top and narrow at the bottom, and the side wall of the groove 24 is an inclined side wall.

[0076] Optionally, in the embodiment, the epitaxial stack unit 2 has a structure of narrow at the top and wide at the bottom, and the side wall of the epitaxial stack unit 2 is an inclined side wall.

[0077] On the basis of the above embodiment, in an embodiment of the present application, the roughness of the microstructure D is not greater than 0.5 μm.

[0078] On the basis of the above embodiment, in an embodiment of the present application, in step S200, the first photoetching specifically includes the following steps:

[0079] Step S201, as shown in the figure, a first photoresist 9 is deposited on the epitaxial stack;

[0080] Figure 11 Step S202, as shown in the figure, the first photoresist 9 is patterned to expose part of the surface of the epitaxial stack, and then a hardening process is performed to form a first photoetching pattern 10, and at the same time, a sawtooth-shaped C is formed on the edge area of the upper surface of the first photoetching pattern 10.

[0081] Step S203, as shown in the figure, the first photoetching pattern 10 is used as a mask, and an etching process is performed to form a cutting path preset area A, a groove 24 and a microstructure D on the second-type semiconductor layer 23 at the same time. Figure 12

[0082] Step S203, as shown in the figure, the first photoetching pattern 10 is used as a mask, and an etching process is performed to form a cutting path preset area A, a groove 24 and a microstructure D on the second-type semiconductor layer 23 at the same time. Figure 8

[0083] ​​​​Based on the above embodiments, in one embodiment of this application, the first photolithography further extends the microstructure D to at least the sidewall of the second type semiconductor layer 23.

[0084] Specifically, the following procedures are included:

[0085] Step A101, Reference Figure 11 As shown, a full layer of first photoresist 9 is deposited on the epitaxial stack;

[0086] Step A102, as follows Figure 13 As shown, the first photoresist 9 is patterned through exposure and development processes, exposing part of the epitaxial stack surface, and the first photoresist 9 has a structure that is narrow at the top and wide at the bottom, and the sidewalls of the first photoresist 9 are inclined sidewalls. Then, the first photolithographic pattern 10 is formed through hard film process, and a serrated C is formed in the edge region of the upper surface of the first photolithographic pattern 10, and the serrated C extends to the sidewalls of the first photolithographic pattern 10.

[0087] Step A103, as follows Figure 14 As shown, using the first photolithographic pattern 10 as a mask, a microstructure D on the epitaxial stack, including the pre-defined dicing area A, the groove 24, and the second type semiconductor layer 23, is simultaneously formed through an etching process, and the microstructure D extends at least to the sidewall of the second type semiconductor layer 23.

[0088] Based on the above embodiments, in one embodiment of this application, the first photoresist 9 can be hardened on a baking plate using a first hardening temperature and a first hardening time.

[0089] Based on the above embodiments, in one embodiment of this application, the microstructure D occupies 0%-3% of the area of ​​the upper surface of the second type semiconductor layer 23, excluding the endpoint values.

[0090] Based on the above embodiments, in one embodiment of this application, the area of ​​the sidewall of the groove occupied by the microstructure is S1, and the area of ​​the sidewall of the groove is S2, then 0 < S1 ≤ S2.

[0091] Based on the above embodiments, in one embodiment of this application, the area of ​​the microstructure occupying the sidewall of the epitaxial stacked unit is S3, and the area of ​​the sidewall of the epitaxial stacked unit is S4, then 0 < S3 ≤ S4.

[0092] Based on the above embodiments, in one embodiment of this application, step S300 further includes etching the epitaxial stack through a second photolithography process, so that the sidewalls of the epitaxial stack unit form a mesa-shaped structure T through the exposed portion of the first type semiconductor layer 21; simultaneously, forming a concave-convex microstructure D in the edge region of the mesa-shaped structure T, specifically including the following steps:

[0093] Step S301, as follows Figure 15As shown, a whole layer of second photoresist 11 is deposited on the chip structure formed after the first photoetching, so that the second photoresist 11 covers the epitaxial stack, the preset area A of the cutting groove and the groove 24;

[0094] In step S302, as shown in Figure 16 The second photoresist 11 is patterned to expose part of the preset area A of the cutting groove, and then a second photoetching pattern 12 is formed by a hard film process, and a sawtooth-shaped C is formed on the edge area of the upper surface of the second photoetching pattern 12.

[0095] In step S303, as shown in Figure 17 The second photoetching pattern 12 is used as a mask to form the cutting groove B, the table-shaped structure T and the microstructure D on the table-shaped structure T by an etching process.

[0096] It should be noted that in the embodiment, the device structure shown in Figure 14 may be used for preparation, and in other embodiments, the device structure shown in Figure 8 may be used for preparation, which will not be described here.

[0097] It should be further noted that in the embodiment, the epitaxial stack is deeply etched by the second photoetching, so that the epitaxial stack unit forms a table-shaped structure T through the exposed part of the first type semiconductor layer 21, and a concave-convex microstructure D is formed on the edge area of the table-shaped structure T. The microstructure can be used as a nucleation point in the formation process of the insulating protective layer to improve the compactness and adhesion of the insulating protective layer 5 on the side wall of the epitaxial stack unit 2, thereby improving the water vapor resistance of the LED chip. The microstructure D on the table-shaped structure T is formed in the second photoetching process, without the need to increase the roughening process step, which can simplify the process, save costs and improve production.

[0098] On the basis of the above embodiment, in an embodiment of the present application, the second photoetching also makes the microstructure D extend from the surface of the table-shaped structure T to the side wall of the table-shaped structure T.

[0099] Specifically, the following processes are included:

[0100] In step A201, as shown in Figure 15 A whole layer of second photoresist 11 is deposited on the chip structure formed after the first photoetching, so that the second photoresist 11 covers the epitaxial stack, the preset area A of the cutting groove and the groove 24;

[0101] In step A202, as shown in Figure 18As shown, the second photoresist 11 is patterned by an exposure and development process to expose the preset area A of the cutting groove, and the second photoresist 11 has a narrow top and wide bottom structure, and the sidewall of the second photoresist 11 is an inclined sidewall. Then, a second photoresist pattern 12 is formed by a hardening process, and a sawtooth structure C is formed on the edge area of the upper surface of the second photoresist pattern 12, and the sawtooth structure C extends to the sidewall of the second photoresist pattern 12.

[0102] As shown in step A203, the second photoresist pattern 12 is used as a mask to form the cutting groove B, the table structure T and the microstructure D on the table structure T by an etching process, and the microstructure D extends from the surface of the table structure T to the sidewall of the table structure T. Figure 19

[0103] In an embodiment of the present application, the second photoresist 11 is hardened in the oven by using a second hardening temperature and a second hardening time based on the above embodiments.

[0104] In an embodiment of the present application, the microstructure D accounts for 0%-3% of the area of the surface of the table structure T, not including the end point value, based on the above embodiments.

[0105] In an embodiment of the present application, as shown in Figure 4 As shown, the starting layer of the insulating protective layer 5 includes an aluminum oxide layer 51, and the aluminum oxide layer 51 is grown in an island-like structure on the microstructure D by atomic layer deposition.

[0106] Optionally, in the present embodiment, the ALD (atomic layer deposition) technology is used to deposit the aluminum oxide layer 51. ALD is a thin film preparation technology of atomic level growth layer by layer. The precursor is adsorbed on the surface of the substrate to form a thin film by reaction, and has good density.

[0107] In an embodiment of the present application, as shown in Figure 4 As shown, the insulating protective layer 5 further includes a first passivation layer 52, a reflective layer 53 and a second passivation layer 54 which are sequentially stacked on the aluminum oxide layer 51.

[0108] Optionally, in the present embodiment, the materials of the first passivation layer 52 and the second passivation layer 54 include but are not limited to one or more of silicon oxide and silicon nitride.

[0109] Optionally, in the present embodiment, the reflective layer 53 includes a DBR structure.

[0110] ​It should be noted that in the embodiment, the DBR structure is a periodic structure in which two materials with different refractive indexes are alternately stacked in an ABAB manner, wherein the high-refractive-index layer can be a Ti3O5 layer, and the low-refractive-index layer can be a SiO2 layer; and the number of periods of the DBR structure is not specifically limited, and can be set according to actual needs.

[0111] On the basis of the above embodiment, in an embodiment of the present application, as shown in FIG. 1, the epitaxial stack further includes a transparent conductive layer 6, a first pad 7, and a second pad 8; wherein the transparent conductive layer 6 is arranged on a side surface of the second-type semiconductor layer 23 away from the active region 22, and the second electrode 4 is deposited on a surface of the transparent conductive layer 6 or embedded in the transparent conductive layer 6 through a first via to form a connection with the second-type semiconductor layer 23. Figure 5

[0112] The insulating protective layer 5 has a second via exposing the first electrode 3 and a third via exposing the second electrode 4.

[0113] The first pad 7 forms an electrical connection with the first electrode 3 through the second via, the second pad 8 forms an electrical connection with the second electrode 4 through the third via, and the first pad 7 and the second pad 8 are arranged at intervals.

[0114] In summary, the above technical solutions achieve the following effects:

[0115] 1. The LED chip provided by the embodiment, by arranging an epitaxial stack unit, the epitaxial stack unit at least includes: a first-type semiconductor layer, an active region, and a second-type semiconductor layer stacked on a substrate in turn from bottom to top; wherein a concave-convex microstructure is arranged on an edge region of an upper surface of the second-type semiconductor layer, the microstructure can be used as a nucleation point in the process of forming the insulating protective layer to improve the compactness and adhesion of the insulating protective layer, which is conducive to relieving stress concentration on the edge region of the upper surface of the LED chip to improve the water vapor resistance of the LED chip, and further improve the reliability of the LED chip.

[0116] 2. Further, by setting the roughness of the microstructure to be not greater than 0.5 μm, the compactness and adhesion of the insulating protective layer formed on the microstructure are higher, and the water vapor resistance of the LED chip is further improved.

[0117] 3. Further, by setting the microstructure to extend at least to the sidewall of the second-type semiconductor layer, the microstructure on the edge region of the upper surface of the second-type semiconductor layer coincides with the microstructure on the sidewall of the second-type semiconductor layer, which is conducive to relieving stress concentration at the corner of the LED chip, and further improves the water vapor resistance of the LED chip.

[0118] ​4、Further, by setting the side wall of the epitaxial stack unit to form a table-shaped structure through the exposed part of the first type semiconductor layer; the edge area of the table-shaped structure is provided with a concave-convex microstructure, which can be used as a nucleation point in the formation process of the insulating protective layer to improve the density and adhesion of the insulating protective layer at the side wall of the epitaxial stack unit, thereby improving the water vapor resistance of the LED chip.

[0119] 5、Further, by setting the microstructure to extend from the surface of the table-shaped structure to the side wall of the table-shaped structure, the microstructure of the edge area of the table-shaped structure coincides with the microstructure of the side wall of the table-shaped structure, which is conducive to relieving stress concentration at the corner of the side wall of the epitaxial stack unit, further improving the density and adhesion of the insulating protective layer at the side wall of the epitaxial stack unit, thereby improving the water vapor resistance of the LED chip.

[0120] 6、Further, by setting the starting layer of the insulating protective layer to include an aluminum oxide layer, the microstructure is more conducive to the aluminum oxide layer to form an island-shaped structure in an atomic layer deposition manner on the microstructure, so that the aluminum oxide layer forms good density, which can relieve the stress of the aluminum oxide layer on the epitaxial stack unit, further improving the density and adhesion of the insulating protective layer.

[0121] 5、The manufacturing method of the LED chip provided by the embodiment forms the cutting path preset area and the groove through the first photoetching and etching of the epitaxial stack, and forms a concave-convex microstructure on the edge area of the upper surface of the second type semiconductor layer at the same time, which can be used as a nucleation point in the formation process of the insulating protective layer to improve the density and adhesion of the insulating protective layer, which is conducive to relieving stress concentration on the edge area of the upper surface of the LED chip to improve the water vapor resistance of the LED chip, thereby improving the reliability of the LED chip; and the microstructure on the second type semiconductor layer is formed in the first photoetching and etching process, without the need to increase the roughening process step, which can simplify the process, save costs, and improve yield.

[0122] Those skilled in the art should understand that in the disclosure of the present application, the orientation or positional relationship indicated by the terms "transverse", "longitudinal", "upper", "lower" and the like is based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore the above terms cannot be understood as a limitation on the present application.

[0123] It should be noted that each embodiment in the present specification adopts a progressive description manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between each embodiment can be referred to each other.

[0124] The above description of disclosed embodiments enables one of ordinary skill in the art to make or use the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED chip comprising a substrate and a plurality of LED light emitting units arranged on the surface of the substrate and spaced apart from each other by a cutting path, characterized in that, The LED light-emitting unit comprises: an epitaxial stack unit disposed on the substrate surface, the epitaxial stack unit comprising, from bottom to top, a first-type semiconductor layer, an active region, and a second-type semiconductor layer stacked in sequence on the substrate; a groove with a portion of the first-type semiconductor layer exposed on a side of the epitaxial stack unit facing away from the substrate, the sidewall of the groove being an inclined sidewall; wherein a concave-convex microstructure is provided on an edge region of an upper surface of the second-type semiconductor layer; a first electrode and a second electrode are disposed on the epitaxial stack unit: the first electrode is disposed at the bottom of the groove and forms an electrical connection with the first-type semiconductor layer, and is insulated from the sidewall of the groove; the second electrode is disposed on a side of the second-type semiconductor layer facing away from the active region and forms an electrical connection with the second-type semiconductor layer, and the first electrode and the second electrode are disposed remotely from each other; an insulating protective layer covering the microstructure and the exposed surface of the epitaxial stack unit, and exposing the first electrode and the second electrode.

2. The LED chip of claim 1, wherein: The roughness of the microstructure is not greater than 0.5 μm.

3. The LED chip of claim 1, wherein: The microstructure occupies 0%-3% of the area of the upper surface of the second-type semiconductor layer, excluding the end point.

4. The LED chip of claim 1, wherein: The microstructure extends at least to the sidewall of the second-type semiconductor layer.

5. The LED chip of claim 1, wherein: The sidewall of the epitaxial stack unit forms a mesa structure by exposing a portion of the first-type semiconductor layer; a concave-convex microstructure is provided on an edge region of the mesa structure.

6. The LED chip of claim 5, wherein: The microstructure occupies 0%-3% of the area of the surface of the mesa structure, excluding the end point.

7. The LED chip of claim 5, wherein: The microstructure extends from the surface of the mesa structure to the sidewall of the mesa structure.

8. The LED chip of claim 1, wherein: The starting layer of the insulating protective layer comprises an aluminum oxide layer, and the aluminum oxide layer forms an island structure on the microstructure in an atomic layer deposition manner.

9. The LED chip of claim 8, wherein: The insulating protective layer further comprises a first passivation layer, a reflective layer, and a second passivation layer stacked in sequence on the aluminum oxide layer.

10. The LED chip of claim 1, wherein: The epitaxial stack further comprises a transparent conductive layer, a first pad, and a second pad; wherein the transparent conductive layer is disposed on a side surface of the second-type semiconductor layer facing away from the active region, and the second electrode is deposited on a surface of the transparent conductive layer or embedded in the transparent conductive layer through a first via to form a connection with the second-type semiconductor layer; and the insulating protective layer has a second via exposing the first electrode and a third via exposing the second electrode; the first pad forms an electrical connection with the first electrode through the second via, the second pad forms an electrical connection with the second electrode through the third via, and the first pad and the second pad are disposed remotely from each other.

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