Chip packaging structure

By introducing a combined design of packaging base, adhesive layer and heat sink into the chip packaging structure, the problem of poor heat dissipation in the internal cavity of the chip packaging structure is solved, and better heat dissipation effect and soldering reliability are achieved.

CN224124569UActive Publication Date: 2026-04-14SHANGHAI SUO YE INT TRADE CO LTD
View PDF 1 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2025-06-04
Publication Date
2026-04-14

AI Technical Summary

Technical Problem

The existing chip packaging structure has poor internal heat dissipation, which makes the chip prone to damage due to prolonged exposure to high temperatures.

Method used

It adopts a combination structure of packaging base, adhesive layer, heat sink and limiting plate. The chip position is fixed by adhesive layer and heat sink is used to absorb and transfer the chip heat to the air to enhance heat dissipation.

Benefits of technology

It improves the chip's heat dissipation efficiency, prevents the chip from being damaged by high temperatures, and ensures the stability of the packaging structure and the reliability of the soldering.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN224124569U_ABST
    Figure CN224124569U_ABST
Patent Text Reader

Abstract

The utility model relates to the technical field of packaging, in particular to a chip packaging structure, which comprises a packaging base, a bonding layer is adhered to the top end of the packaging base, a chip body is adhered to the top end of the bonding layer, limiting plates are adhered to the middle of the periphery of the chip body, and the bottom ends of the limiting plates extend into the bonding layer. A bonding layer is arranged on the chip body, first cooling fins are pasted on the two sides of the bonding layer, two second cooling fins are fixedly connected between the two first cooling fins, the two second cooling fins are located at the two ends of the first cooling fins respectively, the top ends of the first cooling fins penetrate through the bonding layer to be flush with the top end of the bonding layer, and the first cooling fins are located on the two sides of the chip body. The top end of the packaging base is fixedly connected with a packaging shell, and the chip body is located in the packaging shell. Compared with the prior art, heat transfer of the outer wall of the chip body is fast, the heat dissipation performance of the chip body is enhanced, and therefore the chip body is not prone to being damaged in the using process.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] This utility model relates to the field of packaging technology, and in particular to a chip packaging structure. Background Technology

[0002] The housing used to mount semiconductor integrated circuit chips serves to place, fix, seal, and protect the chips, as well as enhance their electrothermal performance. It also acts as a bridge between the internal world of the chip and external circuits. The contacts on the chip are connected to the pins of the housing by wires, and these pins are then connected to other devices through wires on the printed circuit board.

[0003] In the prior art, Chinese patent CN219476674U proposes a chip packaging structure. By limiting the size and amount of solder in the soldering groove, a solder layer is formed inside the soldering groove when the soldering protrusion is fixed to the inner wall of the soldering groove with solder. This ensures the soldering strength between the chip and the substrate. The solder layer does not exceed the opening end face of the soldering protrusion, effectively blocking the solder in a certain area at the bottom of the soldering groove, preventing the solder from contacting the pads on the chip and the pins of the lead frame, thus effectively avoiding the problem of short circuits. However, in practical applications, the existing chip packaging structure is internally closed, resulting in poor heat dissipation. This causes the chip to operate at a high temperature for a long time, making the chip prone to damage. Therefore, we disclose a chip packaging structure. Utility Model Content

[0004] In view of this, the purpose of this utility model is to propose a chip packaging structure to solve the problem of poor heat dissipation in the internal cavity of the chip packaging structure.

[0005] To achieve the above objectives, this utility model provides a chip packaging structure, including a packaging base, an adhesive layer attached to the top of the packaging base, a chip body attached to the top of the adhesive layer, a limiting plate attached to the center of each perimeter of the chip body, the bottom end of the limiting plate extending into the adhesive layer, first heat sinks attached to both sides of the adhesive layer, two second heat sinks fixedly connected between the two first heat sinks, the two second heat sinks respectively located at both ends of the first heat sinks, the top of the first heat sinks extending through to the outside of the adhesive layer and flush with the top of the adhesive layer, the first heat sinks located on both sides of the chip body, and a packaging shell fixedly connected to the top of the packaging base, the chip body located inside the packaging shell.

[0006] Preferably, the length and width of the adhesive layer are both greater than the length and width of the chip body, and the length of the first heat sink is greater than the length of the chip body.

[0007] Preferably, a plurality of third heat sinks are fixedly connected between the two second heat sinks, and both the third heat sinks and the second heat sinks are wrapped in the adhesive layer.

[0008] Preferably, the limiting plate, the first heat sink, the second heat sink, and the third heat sink are all made of metal.

[0009] Preferably, the adhesive layer is a die bond adhesive.

[0010] Preferably, a first soldering base is soldered to both ends of the chip body, a wire harness is fixedly connected to one end of the first soldering base, a second soldering block is fixedly connected to one end of the wire harness, and a second soldering base is fixedly connected to both ends of the packaging base, and the second soldering block and the second soldering base are fixedly soldered together.

[0011] Preferably, the second welding block is a sphere, and a U-shaped groove is provided in the middle of the second welding base, and the second welding block is movably engaged with the U-shaped groove.

[0012] The beneficial effects of this utility model are as follows: the packaging base and the chip body are bonded by the adhesive layer, so that the relative positions of the packaging base and the chip body are fixed. The position of the limiting plate is fixed by the adhesive layer. The heat emitted by the chip body during use is transferred to the adhesive layer, absorbed by the adhesive layer and the second heat sink, and then transferred to the air, which accelerates the heat transfer of the outer wall of the chip body, enhances the heat dissipation of the chip body, and makes the chip body less prone to damage during use.

[0013] The chip body is connected to the packaging base through the connection points of the first soldering socket, wire harness, second soldering block and second soldering base, so that the chip can be used normally after packaging. The second soldering block and second soldering base make it easy to connect, making soldering easy and less likely to cause problems such as cold solder joints. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only for this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of an embodiment of the present utility model;

[0016] Figure 2 This is a partially cutaway three-dimensional structural diagram of the adhesive layer of this utility model;

[0017] Figure 3 This is a partial cross-sectional three-dimensional structural diagram of the adhesive layer of this utility model.

[0018] The diagram is marked as follows:

[0019] 1. Packaging base; 2. Adhesive layer; 3. Chip body; 4. Limiting plate; 5. First heat sink; 6. Second heat sink; 7. Third heat sink; 8. First soldering base; 9. Wire harness; 10. Second soldering block; 11. Second soldering base; 12. Packaging shell. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to specific embodiments.

[0021] It should be noted that, unless otherwise defined, the technical or scientific terms used in this utility model should have the ordinary meaning understood by one of ordinary skill in the art to which this utility model pertains. The terms "first," "second," and similar terms used in this utility model do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0022] like Figures 1-3As shown, a chip packaging structure includes a packaging base 1, an adhesive layer 2 attached to the top of the packaging base 1, a chip body 3 attached to the top of the adhesive layer 2, a limiting plate 4 attached to the center of each perimeter of the chip body 3, the bottom end of the limiting plate 4 extending into the adhesive layer 2, first heat sinks 5 attached to both sides of the adhesive layer 2, and two second heat sinks 6 fixedly connected between the two first heat sinks 5, the two second heat sinks 6 being located at both ends of the first heat sinks 5, the top of the first heat sinks 5 extending through to the outside of the adhesive layer 2 and flush with the top of the adhesive layer 2, the first heat sinks 5 being located on both sides of the chip body 3, a packaging shell 12 fixedly connected to the top of the packaging base 1, the chip body 3 being located inside the packaging shell 12, and the length and width of the adhesive layer 2 being greater than those of the chip body. The length and width of the chip body 3 are as follows: the length of the first heat sink 5 is greater than the length of the chip body 3; several third heat sinks 7 are fixedly connected between the two second heat sinks 6; the third heat sinks 7 and the second heat sinks 6 are both wrapped in the adhesive layer 2; the limiting plate 4, the first heat sink 5, the second heat sink 6, and the third heat sinks 7 are all made of metal, such as aluminum alloy; the adhesive layer 2 is die bond adhesive. In use, the chip body 3 is attached to the top of the encapsulation base 1, and the chip body 3 is attached to the top of the adhesive layer 2, so that the adhesive layer 2 adheres to the encapsulation base 1 and the chip body 3, thus fixing the relative position of the encapsulation base 1 and the chip body 3; the limiting plate 4 is attached to the center of the four sides of the chip body 3, so that the limiting plate 4 restricts the placement of the chip body 3. The relative position of the chip body 3 to the upper end of the packaging base 1 also enhances the stability of the chip body 3. The bottom end of the limiting plate 4 extends into the adhesive layer 2, allowing the adhesive layer 2 to fix the position of the limiting plate 4. First heat sinks 5 are attached to both sides of the adhesive layer 2, and two second heat sinks 6 are fixedly connected between the two first heat sinks 5. The two second heat sinks 6 are located at opposite ends of the first heat sinks 5. The top of the first heat sink 5 extends through to the outside of the adhesive layer 2 and is flush with the top of the adhesive layer 2. The first heat sinks 5 are located on both sides of the chip body 3, allowing the heat emitted by the chip body 3 during use to be transferred to the adhesive layer 2, absorbed by the adhesive layer 2 and the second heat sinks 6, and then transferred into the air, accelerating heat transfer to the outer wall of the chip body 3 and enhancing the stability of the chip body 3. The heat dissipation is excellent, thus making the chip body 3 less prone to damage during use. A package shell 12 is fixedly connected to the top of the package base 1, and the chip body 3 is located inside the package shell 12. The package base 1 and package shell 12 encapsulate the chip body 3, protecting it. The adhesive layer 2 has a length and width greater than the length and width of the chip body 3, allowing it to fix the limiting plate 4, which then restricts the position of the chip body 3. The first heat sink 5 has a length greater than the length of the chip body 3, resulting in a larger contact area with the air and better heat dissipation. Several third heat sinks 7 are fixedly connected between two second heat sinks 6, and both the third heat sinks 7 and the second heat sinks 6 are encased within the adhesive layer 2.This allows the heat absorbed by the adhesive layer 2 to be quickly absorbed by the third heat sink 7, transferred to the second heat sink 6, and then to the first heat sink 5 for dissipation, thus enhancing the heat dissipation of the adhesive layer 2. Since the limiting plate 4, the first heat sink 5, the second heat sink 6, and the third heat sink 7 are all metal, they have good thermal conductivity, thereby accelerating the heat dissipation efficiency of the chip body 3. Furthermore, the adhesive layer 2 is made of die-bonding adhesive, giving it high bonding strength and good thermal conductivity.

[0023] As a preferred embodiment of this example, Figure 2 and Figure 3 As shown, both ends of the chip body 3 are soldered with first soldering seats 8. One end of the first soldering seat 8 is fixedly connected to a wire harness 9, and one end of the wire harness 9 is fixedly connected to a second soldering block 10. Both ends of the packaging base 1 are fixedly connected with second soldering bases 11. The second soldering block 10 and the second soldering base 11 are fixedly soldered together. The second soldering block 10 is a sphere, and a U-shaped groove is formed in the middle of the second soldering base 11. The second soldering block 10 is movably engaged with the U-shaped groove. The chip body 3 has first soldering seats 8 soldered to both ends, and one end of the first soldering seat 8 is fixedly connected to a wire harness 9. One end of the wire harness 9 is fixedly connected to a second soldering block 10. The two welding blocks 10 and the two ends of the packaging base 1 are fixedly connected to the second welding base 11. The second welding blocks 10 and the second welding base 11 are fixedly welded, so that the chip body 3 is connected to the packaging base 1 through the connection point of the first welding base 8, the wire harness 9, the second welding blocks 10 and the second welding base 11, so that the chip can be used normally after packaging. The second welding block 10 is a sphere, and the second welding base 11 has a U-shaped groove in the middle. The second welding block 10 is movably engaged with the U-shaped groove, so that the second welding block 10 and the second welding base 11 are easy to connect, making welding easy and less prone to problems such as cold solder joints.

[0024] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the present invention (including the claims) is limited to these examples; within the framework of the present invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of the different aspects of the present invention as described above, which are not provided in the details for the sake of brevity.

[0025] This utility model is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A chip packaging structure, comprising a packaging base (1), characterized in that, An adhesive layer (2) is attached to the top of the packaging base (1), and a chip body (3) is attached to the top of the adhesive layer (2). A limiting plate (4) is attached to the center of the chip body (3) around its perimeter. The bottom end of the limiting plate (4) extends into the adhesive layer (2). A first heat sink (5) is attached to both sides of the adhesive layer (2). Two second heat sinks (6) are fixedly connected between the two first heat sinks (5). The two second heat sinks (6) are located at both ends of the first heat sinks (5). The top of the first heat sink (5) extends through to the outside of the adhesive layer (2) and is flush with the top of the adhesive layer (2). The first heat sink (5) is located on both sides of the chip body (3). A packaging shell (12) is fixedly connected to the top of the packaging base (1), and the chip body (3) is located inside the packaging shell (12).

2. The chip packaging structure according to claim 1, characterized in that, The length and width of the adhesive layer (2) are both greater than the length and width of the chip body (3), and the length of the first heat sink (5) is greater than the length of the chip body (3).

3. The chip packaging structure according to claim 1, characterized in that, A plurality of third heat sinks (7) are fixedly connected between the two second heat sinks (6), and the third heat sinks (7) and the second heat sinks (6) are both wrapped in the adhesive layer (2).

4. The chip packaging structure according to claim 3, characterized in that, The limiting plate (4), the first heat sink (5), the second heat sink (6) and the third heat sink (7) are all made of metal.

5. The chip packaging structure according to claim 1, characterized in that, The adhesive layer (2) is a die bond adhesive.

6. The chip packaging structure according to claim 1, characterized in that, The chip body (3) has a first soldering seat (8) welded to both ends. A wire harness (9) is fixedly connected to one end of the first soldering seat (8). A second soldering block (10) is fixedly connected to one end of the wire harness (9). A second soldering base (11) is fixedly connected to both ends of the packaging base (1). The second soldering block (10) and the second soldering base (11) are fixedly soldered together.

7. The chip packaging structure according to claim 6, characterized in that, The second welding block (10) is a sphere, and a U-shaped groove is provided in the middle of the second welding base (11). The second welding block (10) is movably engaged with the U-shaped groove.

Citation Information

Patent Citations

  • Chip packaging structure

    CN219476674U