Simulator JTAG isolation circuit
By using an isolation chip to achieve electrical isolation and power independence between the emulator and the target board, the problems of emulator susceptibility to damage and cumbersome power matching are solved, thereby improving equipment safety and debugging efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- 深圳市力芯微科技有限公司
- Filing Date
- 2025-04-18
- Publication Date
- 2026-04-17
AI Technical Summary
During simulation and debugging, existing JTAG simulators are susceptible to damage from overvoltage or overcurrent surges, and power matching relies on cumbersome manual operation, resulting in insufficient equipment safety and low debugging efficiency.
An isolation chip is used to achieve electrical isolation between the emulator and the target board. The isolation chip automatically adapts to the power supply voltage of the target board to achieve isolation between the power supply and the JTAG signal, preventing abnormal power supply surges.
It effectively protects the safety of the simulator and computer, automatically adapts to different power supply voltages, improves debugging efficiency, and avoids signal interference.
Smart Images
Figure CN224137712U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of JTAG emulator technology, and more particularly to a JTAG isolation circuit for an emulator. Background Technology
[0002] In the development of power electronic products such as charging devices and motor drives, researchers typically need to use a test system consisting of a computer, digital power supply, JTAG emulator, oscilloscope, and supporting debugging tools. This type of equipment requires a common ground connection to achieve simulation debugging, waveform monitoring, and data communication functions. However, actual debugging environments often present problems such as inconsistent ground levels and complex electromagnetic interference (EMI), leading to the persistent presence of the following technical defects:
[0003] Insufficient equipment safety: During simulation debugging, overvoltage or overcurrent may occur in the JTAG interface, which may burn out the emulator and the computer connected to the emulator. In addition, factors such as reversed target power supply, ESD, and large ground voltage difference between the target device and the emulator may cause damage to the emulator due to direct circuit connection, which may be conducted from the target device to the emulator and the computer connected to the emulator.
[0004] Power matching relies on manual operation: Existing JTAG emulators require manual adjustment or replacement of hardware modules to adapt to the target board's power supply voltage (such as 3.3V / 5V), which is cumbersome and prone to voltage mismatch issues on the target board due to misconfiguration, significantly reducing debugging efficiency. Summary of the Invention
[0005] This application provides a JTAG isolation circuit for an emulator to address the problems of overvoltage or overcurrent surges that may burn out the emulator and the connected computer during simulation debugging, as well as voltage mismatch issues with the target board. This application uses an isolation chip to electrically isolate the emulator from the target board, effectively protecting the emulator, the connected computer, and the target device. Furthermore, the isolation chip ensures that the emulator's power supply differs from the target board's power supply, automatically adapting to the target board's voltage to match different operating voltages and complete the simulation debugging task.
[0006] In a first aspect, this application provides an emulator JTAG isolation circuit, which includes an emulator JTAG interface circuit, an intermediate isolation circuit, and a target board JTAG interface circuit.
[0007] The intermediate isolation circuit includes at least one isolation chip for electrical isolation between the emulator and the target board;
[0008] The emulator JTAG interface circuit includes at least one emulator, and the output terminal of the emulator JTAG interface circuit is connected to the input terminal of the intermediate isolation circuit.
[0009] The target board JTAG interface circuit includes at least one target board, and the input terminal of the target board JTAG interface circuit is connected to the output terminal of the intermediate isolation circuit.
[0010] Optionally, the emulator includes multiple emulator JTAG terminals, each of which is connected to the input terminal of the isolation chip, and each of the emulator JTAG terminals transmits the JTAG signal of the emulator to the isolation chip;
[0011] The isolation chip responds to the JTAG signal and transmits the JTAG signal to the target board;
[0012] The target board includes multiple target board JTAG terminals, each of which is connected to the output terminal of the isolation chip. Each target board JTAG terminal responds to the JTAG signal to realize the simulation debugging of the target board.
[0013] Optionally, the emulator JTAG terminals include: a first JTAG data input terminal, a first JTAG test mode selection input terminal or a first SWDIO terminal, a first synchronization clock input terminal, a first JTAG data output terminal, an emulator power supply positive terminal, and an emulator power supply negative terminal.
[0014] Optionally, the target board JTAG terminals include: a second JTAG data input terminal, a second JTAG data output terminal, a second JTAG test mode selection terminal or a second SWDIO, a second synchronization clock input terminal, a target board power supply positive terminal, and a target board power supply negative terminal.
[0015] Optionally, the emulator's JTAG interface circuit is connected to the target board's JTAG interface circuit through the intermediate isolation circuit, enabling automatic adaptation to the target board's power supply voltage to match target boards with different operating voltages.
[0016] Optionally, the isolation chip employs four unidirectional isolation channels, one of which is a reverse channel and the other three are forward channels.
[0017] Optionally, the power supply of the emulator and the power supply of the target board can be made independent of each other through the isolation chip to achieve isolation between the power supply and the JTAG signal.
[0018] Optionally, the input and output terminals of the isolation chip circuit are further provided with overvoltage protection circuits. The overvoltage protection circuits are used to prevent abnormal power supply of the target board from impacting the simulator. The abnormal power supply includes interference signals and strong voltage and current.
[0019] Optionally, the emulator's JTAG interface circuit supports JTAG and SWD protocol switching, and protocol compatibility is achieved through the configuration of the TMS / SWD signal lines.
[0020] Optionally, a buffer drive circuit is further provided between the target board JTAG interface circuit and the intermediate isolation circuit. The buffer drive circuit is used to enhance signal driving capability and reduce signal delay.
[0021] Compared with the prior art, the above-mentioned technical solution provided in this application has the following advantages: This application uses an isolation chip to electrically isolate the emulator from the target board, effectively protecting the safety of the emulator and the computer and target device connected to the emulator. The isolation chip also makes the power supply of the emulator different from that of the target board, so as to automatically adapt to the power supply voltage of the target board to match the target board with different operating voltages and complete the simulation debugging task. At the same time, the power supply of the emulator and the power supply of the target board are independent of each other to achieve isolation between the power supply and the JTAG signal, which helps to avoid signal interference. Attached Figure Description
[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.
[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.
[0024] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0025] Figure 1 A schematic diagram of a JTAG isolation circuit for an emulator provided in an embodiment of this application;
[0026] Figure 2 A circuit diagram of a JTAG isolation circuit for an emulator provided in an embodiment of this application. Detailed Implementation
[0027] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0028] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.
[0029] To address the problems in the prior art, this application provides a JTAG isolation circuit for an emulator. An isolation chip electrically isolates the emulator from the target board, effectively protecting the emulator, the connected computer, and the target device. The isolation chip also ensures that the emulator's power supply differs from the target board's, automatically adapting to the target board's voltage to match different operating voltages and complete the simulation debugging task. Furthermore, the isolation chip ensures that the emulator's power supply and the target board's power supply are independent, isolating the power supply from the JTAG signal and helping to avoid signal interference.
[0030] Figure 1 This is a schematic diagram of a JTAG isolation circuit for an emulator provided in an embodiment of this application. The JTAG isolation circuit for the emulator includes:
[0031] The isolation circuit includes an emulator JTAG interface circuit, an intermediate isolation circuit, and a target board JTAG interface circuit.
[0032] The intermediate isolation circuit includes at least one isolation chip for electrical isolation between the emulator and the target board;
[0033] The emulator JTAG interface circuit includes at least one emulator, and the output terminal of the emulator JTAG interface circuit is connected to the input terminal of the intermediate isolation circuit.
[0034] The target board JTAG interface circuit includes at least one target board, and the input terminal of the target board JTAG interface circuit is connected to the output terminal of the intermediate isolation circuit.
[0035] Currently, the development of charging devices and motor drivers requires the use of computers, digital power supplies, USB-interface JTAG emulators, oscilloscopes, and other tools, all connected via a common ground for simulation, waveform monitoring, and communication. Since charging devices and motor drivers are inductive loads, overvoltage or overcurrent surges may occur in the target device during simulation and debugging, impacting the JTAG interface and conducting through the circuitry to the computer's motherboard, potentially burning out the emulator and motherboard. Furthermore, reversed target power connections and large ESD voltage differences between the target device and the emulator / computer's ground levels can also cause damage due to direct circuit connections, transmitting from the target device to the emulator and computer, resulting in the burnout of the emulator, the connected computer, and the target device. This application addresses this issue by using an intermediate isolation circuit, including at least one isolation chip, to electrically isolate the emulator and the connected computer from the target device, preventing damage to the target device from being transmitted to the emulator and the connected computer.
[0036] In this embodiment, the target circuit is electrically isolated from the end including the simulator and computer. Overvoltage and overcurrent signals are also implemented to avoid the effects of ground potential difference and ESD on the target device, thus protecting the simulator, the connected computer, and the target device. For debugging environments with inconsistent ground levels and severe EMI, and for objective requirements requiring input / output data, this approach effectively protects device safety while matching target boards with different power supply voltages to complete the debugging task.
[0037] Optionally, the emulator includes multiple emulator JTAG terminals, each of which is connected to the input terminal of the isolation chip, and each of the emulator JTAG terminals transmits the JTAG signal of the emulator to the isolation chip;
[0038] The isolation chip responds to the JTAG signal and transmits the JTAG signal to the target board;
[0039] The target board includes multiple target board JTAG terminals, each of which is connected to the output terminal of the isolation chip. Each target board JTAG terminal responds to the JTAG signal to realize the simulation debugging of the target board.
[0040] Because EMI from the target device causes electronic signal distortion, and the ground level inconsistency between the target device and the emulator / computer can cause common-mode interference, thus affecting simulation debugging and, in severe cases, even making debugging impossible. However, through an intermediate isolation circuit, the impact of EMI from the target device on the emulator and computer is significantly reduced, and common-mode interference between the target device and the emulator / computer is eliminated. A USB-to-UART data input / output interface is added to assist in simulation modulation. Electrical isolation between the target device and the emulator / computer is a key measure in this application to reduce the impact of EMI, ESD, overvoltage, and overcurrent from the target device on the emulator / computer, thereby protecting the equipment while enabling simulation debugging of the target board.
[0041] Figure 2 A circuit diagram of a JTAG isolation circuit for an emulator provided in an embodiment of this application.
[0042] Optionally, the emulator JTAG terminals include: a first JTAG data input terminal, a first JTAG test mode selection input terminal or a first SWDIO terminal, a first synchronization clock input terminal, a first JTAG data output terminal, an emulator power supply positive terminal, and an emulator power supply negative terminal.
[0043] In this embodiment, the signals of each port of the emulator's JTAG interface are as follows: VCC: positive power supply, TDI: data input, TMS / SWD: test mode selection input in JTAG (SWDIO in SW), TCK / SWCLK: synchronization clock input, TDO: data output, GND: negative power supply. The emulator's JTAG interface typically only requires 6 terminals to connect to the target device's JTAG, including: 4 digital signals (TDI, TMS, TCK, TDO), 1 power supply VCC, and 1 power supply GND. Relative to the target device, TDI, TMS, and TCK are three input signals, and TDO is an output signal.
[0044] Optionally, the target board JTAG terminals include: a second JTAG data input terminal, a second JTAG data output terminal, a second JTAG test mode selection terminal or a second SWDIO, a second synchronization clock input terminal, a target board power supply positive terminal, and a target board power supply negative terminal.
[0045] In this embodiment, the valid signal lines of the target board's JTAG interface are connected to the target board and the isolation chip. The signals of each port are as follows: VCC': positive power supply of the target board, TDI': JTAG data input, TMS' / SWD': test mode selection in JTAG (SWDIO in SW), TCK' / SWCLK': synchronization clock, TDO': JTAG data output, GND': negative power supply of the target board.
[0046] Optionally, the emulator's JTAG interface circuit is connected to the target board's JTAG interface circuit through the intermediate isolation circuit, enabling automatic adaptation to the target board's power supply voltage to match target boards with different operating voltages.
[0047] Different target devices may have different power supply VCCs, such as 3V or 5V. To adapt to the target device's VCC, the JTAG emulator has an internal VCC switching switch or jumper, which requires opening the emulator's casing. Through an intermediate isolation circuit, the JTAG emulator's power supply VCC is isolated from the target device's power supply VCC, each supplying its own voltage. This eliminates the need for VCC matching, allowing the emulator to automatically adapt to the target device's VCC without needing to open the casing to adjust it. This achieves automatic adaptation to the target board's power supply voltage to match target boards with different operating voltages.
[0048] Optionally, the isolation chip employs four unidirectional isolation channels, one of which is a reverse channel and the other three are forward channels.
[0049] In this embodiment, the isolation chip CA-IS461LVM has a communication rate of up to 0 to 100 Mbps, an isolation voltage of 5 kVrms, a high CMTI of ±150 kV / uS, and an operating voltage range of 3.0 to 5.5 V, which meets the requirements for JTAG interface isolation.
[0050] Optionally, the power supply of the emulator and the power supply of the target board can be made independent of each other through the isolation chip to achieve isolation between the power supply and the JTAG signal.
[0051] In this embodiment, the power supply VCC of the emulator is isolated from the power supply VCC of the target device, each supplying its own voltage. This eliminates the need for VCC matching and also isolates the signal from the power supply, preventing noise from the power supply from being transmitted into the JTAG signal, which helps to ensure a clean JTAG signal.
[0052] Optionally, the input and output terminals of the isolation chip circuit are further provided with overvoltage protection circuits. The overvoltage protection circuits are used to prevent abnormal power supply of the target board from impacting the simulator. The abnormal power supply includes interference signals and strong voltage and current.
[0053] In this embodiment, an overvoltage protection function is also provided. The overvoltage protection circuit prevents line burnout or signal noise problems caused by excessive voltage or abnormal power supply surges at either the simulator end or the target device end. This is beneficial for protecting the safety of the simulator, the computer connected to the simulator, and the target board, and for improving the accuracy of simulation debugging.
[0054] Optionally, the emulator's JTAG interface circuit supports JTAG and SWD protocol switching, and protocol compatibility is achieved through the configuration of the TMS / SWD signal lines.
[0055] Debugging interfaces commonly use two protocols: JTAG and SWD. To conserve I / O resources (e.g., in products with limited pins), different programmers / debuggers may default to using different protocols (e.g., J-Link and ST-Link support both). Some chips are configured to boot in JTAG mode by default, but projects may actually require SWD. Based on these reasons, the JTAG interface circuit of this application supports switching between JTAG and SWD protocols.
[0056] Optionally, a buffer drive circuit is further provided between the target board JTAG interface circuit and the intermediate isolation circuit. The buffer drive circuit is used to enhance signal driving capability and reduce signal delay.
[0057] In the embodiments of this application, the buffer drive circuit is a circuit structure used in digital or analog circuits for signal amplification, isolation, or driving load. It mainly plays the role of improving signal driving capability, preventing signal distortion or loading interference to isolate circuits before and after the signal, and improving system stability. It is beneficial to enhance signal driving capability and reduce signal delay.
[0058] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0059] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0060] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0061] In the embodiments provided in this application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.
[0062] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0063] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.
[0064] The implementation of all or part of the processes in the methods of the above embodiments can also be accomplished by a computer program product. When the computer program product is run on a terminal device, the terminal device can implement the steps in the various method embodiments described above.
[0065] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. An emulator JTAG isolation circuit, comprising: The emulator JTAG isolation circuit includes an emulator JTAG interface circuit, an intermediate isolation circuit, and a target board JTAG interface circuit. The intermediate isolation circuit includes at least one isolation chip for electrical isolation between the emulator and the target board; The emulator JTAG interface circuit includes at least one emulator, and the output terminal of the emulator JTAG interface circuit is connected to the input terminal of the intermediate isolation circuit. The target board JTAG interface circuit includes at least one target board, and the input terminal of the target board JTAG interface circuit is connected to the output terminal of the intermediate isolation circuit.
2. The emulator JTAG isolation circuit of claim 1, wherein, The emulator includes multiple emulator JTAG terminals, each of which is connected to the input terminal of the isolation chip, and each of the emulator JTAG terminals transmits the JTAG signal of the emulator to the isolation chip; The isolation chip responds to the JTAG signal and transmits the JTAG signal to the target board; The target board includes multiple target board JTAG terminals, each of which is connected to the output terminal of the isolation chip. Each target board JTAG terminal responds to the JTAG signal to realize the simulation debugging of the target board.
3. The emulator JTAG isolation circuit of claim 2, wherein, The emulator JTAG terminals include: a first JTAG data input terminal, a first JTAG test mode selection input terminal or a first SWDIO terminal, a first synchronization clock input terminal, a first JTAG data output terminal, an emulator power supply positive terminal, and an emulator power supply negative terminal.
4. The emulator JTAG isolation circuit of claim 2, wherein, The target board JTAG terminals include: a second JTAG data input terminal, a second JTAG data output terminal, a second JTAG test mode selection terminal or a second SWDIO, a second synchronous clock input terminal, a target board power supply positive terminal, and a target board power supply negative terminal.
5. The emulator JTAG isolation circuit of claim 1 or 2, wherein, The emulator's JTAG interface circuit is connected to the target board's JTAG interface circuit through the intermediate isolation circuit, enabling it to automatically adapt to the target board's power supply voltage to match target boards with different operating voltages.
6. The emulator JTAG isolation circuit of claim 1, wherein, The isolation chip employs four unidirectional isolation channels, one of which is a reverse channel and the other three are forward channels.
7. The emulator JTAG isolation circuit of claim 2, wherein, The isolation chip makes the power supply of the emulator and the power supply of the target board independent of each other, thereby achieving isolation between the power supply and the JTAG signal.
8. The emulator JTAG isolation circuit of claim 6, wherein, The input and output terminals of the intermediate isolation circuit are also provided with overvoltage protection circuits. The overvoltage protection circuits are used to prevent abnormal power supply of the target board from impacting the simulator. Abnormal power supply includes interference signals and strong voltage and current.
9. The emulator JTAG isolation circuit of claim 1, wherein, The emulator's JTAG interface circuit supports switching between JTAG and SWD protocols, and protocol compatibility is achieved through the configuration of the TMS / SWD signal lines.
10. The emulator JTAG isolation circuit of claim 1, wherein, A buffer drive circuit is also provided between the target board JTAG interface circuit and the intermediate isolation circuit. The buffer drive circuit is used to enhance the signal driving capability and reduce the signal delay.