Low-power-consumption LDO voltage stabilizing circuit

Abstract

The utility model discloses a low power consumption LDO voltage stabilizing circuit relates to voltage stabilizing circuit field, including LDO chip, input capacitor, output capacitor and is used for reducing the power consumption reduction unit of LDO chip power consumption, wherein the power consumption reduction unit includes the resistor R1 that connects between LDO chip input terminal and output terminal and / or the resistor R2 that connects with LDO chip input terminal in series; one end of the input capacitor is connected with the input end of the LDO chip, the other end of the input capacitor is grounded, one end of the output capacitor is connected with the output end of the LDO chip, and the other end of the output capacitor is grounded. The LDO voltage stabilizing circuit can effectively reduce power consumption, remarkably reduce temperature rise and avoid overheating, and has the advantages of being low in cost, high in compatibility and high in reliability.

Description

Technical Field

[0001] This utility model relates to the field of voltage regulator circuits, and in particular to a low-power LDO voltage regulator circuit. Background Technology

[0002] In motor controllers, LDOs (Low Dropout Voltage Regulators) are commonly used to convert drive voltage inputs (e.g., 15V) to low-voltage outputs (e.g., 5V). Traditional LDOs consume power equal to the product of the voltage drop (10V) and the load current, resulting in low efficiency, significant heat generation, and a tendency to trigger overheat protection, thus affecting system reliability. Existing solutions often rely on heat sinks or replacing the switching regulator, but the former increases size, while the latter introduces electromagnetic interference and increases cost. Therefore, a low-cost, low-complexity improvement solution is needed. Utility Model Content

[0003] In response to the aforementioned problems and technical requirements, the applicant has proposed a low-power LDO voltage regulator circuit.

[0004] The technical solution of this utility model is as follows:

[0005] A low-power LDO voltage regulator circuit includes an LDO chip, an input capacitor, an output capacitor, and a power reduction unit for reducing the power consumption of the LDO chip.

[0006] The power consumption reduction unit includes a resistor R1 connected between the input and output terminals of the LDO chip and / or a resistor R2 connected in series with the input terminal of the LDO chip.

[0007] One end of the input capacitor is connected to the input terminal of the LDO chip, and the other end of the input capacitor is grounded. One end of the output capacitor is connected to the output terminal of the LDO chip, and the other end of the output capacitor is grounded.

[0008] A further technical solution is that the output terminal of the LDO chip is electrically connected to the load, and the resistance value of the resistor R1 satisfies:

[0009]

[0010] Among them, V in(LDO) V is the input voltage of the LDO chip. out(LDO) I is the output voltage of the LDO chip. LDO(max) I is the maximum allowable current of the LDO chip. load(max) This represents the maximum operating current of the load.

[0011] A further technical solution is that one end of the resistor R2 is connected to the input voltage V. inThe other end of resistor R2 is connected to the input terminal of the LDO chip, and the output terminal of the LDO chip is electrically connected to the load. The resistance value R2 satisfies:

[0012]

[0013] Among them, V out(LDO) V is the output voltage of the LDO chip. drop_LDO I is the minimum input voltage drop of the LDO chip. load(max) This represents the maximum operating current of the load.

[0014] A further technical solution is that, when the power reduction unit includes a resistor R2 connected in series with the input terminal of the LDO chip, the low-power LDO voltage regulator circuit further includes a current-limiting protection unit for limiting the current of the LDO chip. The current-limiting protection unit includes resistors R3, R4, R5, R6, and R7, and switching transistors Q1, Q2, and Q3.

[0015] The third electrode of the switching transistor Q2 is connected to the second electrode of the switching transistor Q2 through resistor R5. The third electrode of the switching transistor Q2 is connected to the input voltage. The first electrode of the switching transistor Q2 is connected to the first electrode of the switching transistor Q1, one end of resistor R3, and one end of resistor R2. The other end of resistor R3 is connected to the second electrode of the switching transistor Q1 and one end of resistor R4. The other end of resistor R4 is connected to the other end of resistor R2.

[0016] A further technical solution is that the third electrode of the switching transistor Q1 is connected to one end of resistor R6 and resistor R7, the other end of resistor R7 is grounded, the other end of resistor R6 is connected to the second electrode of the switching transistor Q3, the third electrode of the switching transistor Q3 is connected to the second electrode of the switching transistor Q2, and the first electrode of the switching transistor Q3 is grounded.

[0017] A further technical solution is that the switching transistor Q1 is a PNP transistor, and the switching transistors Q2 and Q3 are NPN transistors.

[0018] A further technical solution is that when the current limiting protection unit limits the output current of the LDO chip, the current limiting current I... LIMIT It can be represented as:

[0019]

[0020] Wherein, the V be(Q1) R1 is the voltage between the base and emitter of the switching transistor Q1, R2 is the resistance of resistor R2, R3 is the resistance of resistor R3, and R4 is the resistance of resistor R4.

[0021] A further technical solution includes a high-voltage protection unit, which includes diode D1 and diode D2. The positive terminal of diode D1 is connected to the ground terminal of the LDO chip, and the negative terminal of diode D1 is grounded.

[0022] The positive terminal of diode D2 is connected to the output terminal of the LDO chip, and the negative terminal of diode D2 is connected to the load.

[0023] The beneficial technical effects of this utility model are:

[0024] This utility model discloses a low-power LDO voltage regulator circuit, mainly used in motor controllers. It reduces the load current by using a parallel shunt resistor and / or a series current-limiting resistor to decrease the LDO voltage drop and reduce the LDO's own power consumption. Simultaneously, a current-limiting protection unit and a high-voltage protection unit are designed to provide current-limiting protection and high-voltage protection for the LDO. It has the advantages of low cost, strong compatibility, and high reliability, significantly reducing temperature rise and preventing overheating. Attached Figure Description

[0025] Figure 1 This is a circuit diagram of a first embodiment of the low-power LDO voltage regulator circuit provided by this utility model.

[0026] Figure 2 This is a circuit diagram of Embodiment 2 of the low-power LDO voltage regulator circuit provided by this utility model.

[0027] Figure 3 This is a circuit diagram of Embodiment 4 of the low-power LDO voltage regulator circuit provided by this utility model. Detailed Implementation

[0028] The specific embodiments of this utility model will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0029] This invention provides a low-power LDO voltage regulator circuit, including an LDO chip, an input capacitor, an output capacitor, and a power reduction unit for reducing the power consumption of the LDO chip.

[0030] The power reduction unit includes a resistor R1 connected between the input and output terminals of the LDO chip and / or a resistor R2 connected in series with the input terminal of the LDO chip.

[0031] One end of the input capacitor is connected to the input terminal of the LDO chip, and the other end of the input capacitor is grounded. One end of the output capacitor is connected to the output terminal of the LDO chip, and the other end of the output capacitor is grounded.

[0032] Specifically, in the power reduction unit, the resistor R1 connected in parallel with the LDO chip can reduce its power consumption by shunting the current flowing through the LDO chip, and the resistor R2 connected in series with the input terminal of the LDO chip can reduce its power consumption by reducing the voltage drop across the LDO. The input capacitor (C1) is used to filter out high-frequency noise and ripple in the input voltage of the LDO chip, and the output capacitor (C2) is used to reduce transient fluctuations in the output voltage of the LDO chip and improve its output stability. The resistor R1 connected in parallel with the LDO chip and the resistor R2 connected in series with the input terminal of the LDO chip can be used independently or simultaneously. The specific form of the LDO chip can be consistent with existing technology.

[0033] Example 1

[0034] Please refer to Figure 1 In the first embodiment of this utility model, the power consumption reduction unit only includes a resistor R1 connected in parallel with the LDO chip. One end of resistor R1 is connected to the input terminal of the LDO chip, and the other end of resistor R1 is connected to the output terminal of the LDO chip and one end of capacitor C2, forming the output terminal Vout. Resistor R1 controls the current I flowing through the LDO chip. LDO The current shunted through resistor R1 is I. R1 The current output at the output terminal Vout is I. load Then the current I flowing through the LDO chip LDO It can be represented as:

[0035] I LDO =I load -I R1

[0036] The power consumption P of the LDO chip LDO It can be represented as:

[0037] P LDO =(V in(LDO) -V out(LDO) )×I LDO

[0038] The V in(LDO) V is the input voltage of the LDO chip. out(LDO) The LDO voltage regulator circuit provided in this invention is mainly used in motor controllers, where the output voltage of the LDO chip is V. in(LDO) V in(LDO) and I load It is generally fixed, so by connecting a parallel resistor R1, a portion of the load current can flow through the resistor R1, reducing the amount of current flowing through the LDO chip and thus reducing the power consumption of the LDO.

[0039] The power P of resistor R1 R1 Must meet:

[0040]

[0041] The resistance value of resistor R1 can be set according to the required current shunt ratio, and the resistance value of resistor R1 must meet the following requirements:

[0042]

[0043] Among them, I LDO(max) I is the maximum allowable current of the LDO chip. load(max) This represents the maximum operating current of the load.

[0044] Example 2

[0045] Please refer to Figure 2 In the second embodiment of this utility model, the power consumption reduction unit only includes a resistor R2 connected in series with the input terminal of the LDO chip. One end of the resistor R2 is connected to the input terminal of the LDO chip, and the input voltage V... in The voltage is input from the other end of resistor R2, and after being divided by resistor R2, it is input to the input terminal (VIN) of the LDO chip, thus reducing the input voltage V of the LDO chip. in(LDO) This reduces the voltage drop across the LDO chip and lowers its power consumption. The output terminal (VOUT) of the LDO chip is connected to one end of capacitor C2 to form the output terminal Vout, and the current output from Vout is I. load The input voltage V of the LDO chip in(LDO) It can be represented as:

[0046] V in(LDO) =V in -I load ×R2

[0047] Then the power consumption P of the LDO chip LDO It can be represented as:

[0048] P LDO =(V in -V out(LDO) -I load ×R2)×I load

[0049] Among them, V out(LDO) R1 is the output voltage of the LDO chip, and R2 is the resistance value of resistor R2.

[0050] It should be noted that LDO chips typically have a minimum input voltage drop V. drop_LDO Minimum input voltage drop refers to the minimum input voltage V of the LDO chip when it can operate normally and provide a stable output voltage. in(LDO) With output voltage V out(LDO)The minimum voltage difference between them. That is, for the LDO chip to function properly, the input voltage V of the LDO chip must be... in(LDO) It must be at least V higher than the output voltage. drop_LDO Therefore, the resistance value R2 must satisfy:

[0051]

[0052] Among them, I load(max) This represents the maximum operating current of the load.

[0053] Example 3

[0054] In Embodiment 3 of this application, the power consumption reduction unit includes a resistor R1 connected between the input and output terminals of the LDO chip and a resistor R2 connected in series with the input terminal of the LDO chip. The connection method of resistors R1 and R2 is consistent with the connection method described in Embodiments 1 and 2 above. Resistor R1 is used to reduce the current flowing through the LDO chip, while resistor R2 is used to reduce the voltage drop of the LDO chip, thereby further reducing the power consumption of the LDO chip.

[0055] Example 4

[0056] Please refer to Figure 3 The difference between Embodiment 4 and Embodiment 2 is that Embodiment 4 further includes a current-limiting protection unit for limiting the output current of the LDO chip, and a high-voltage protection unit. The current-limiting protection unit includes resistors R3, R4, R5, R6, and R7, and switching transistors Q1, Q2, and Q3.

[0057] The third electrode of the switching transistor Q2 is connected to the second electrode of the switching transistor Q2 through resistor R5. The third electrode of the switching transistor Q2 is connected to the input voltage. The first electrode of the switching transistor Q2 is connected to the first electrode of the switching transistor Q1, one end of resistor R3, and one end of resistor R2. The other end of resistor R3 is connected to the second electrode of the switching transistor Q1 and one end of resistor R4. The other end of resistor R4 is connected to the other end of resistor R2. The third electrode of the switching transistor Q1 is connected to one end of resistor R6 and resistor R7. The other end of resistor R7 is grounded. The other end of resistor R6 is connected to the second electrode of the switching transistor Q3. The third electrode of the switching transistor Q3 is connected to the second electrode of the switching transistor Q2. The first electrode of the switching transistor Q3 is grounded.

[0058] In Embodiment 4, the switching transistor Q1 is a PNP transistor, and the switching transistors Q2 and Q3 are NPN transistors. For both NPN and PNP transistors, the first electrode is the emitter, the second electrode is the base, and the third electrode is the collector.

[0059] The high-voltage protection unit includes diode D1 and diode D2. The positive terminal of diode D1 is connected to the ground terminal of the LDO chip, and the negative terminal of diode D1 is grounded. The positive terminal of diode D2 is connected to the output terminal of the LDO chip, and the negative terminal of diode D2 is connected to the load.

[0060] The specific working principle of the current limiting protection unit is as follows:

[0061] In Example 4, the output terminal Vout is formed using the cathode of diode D2, and the current flowing out of the output terminal Vout is I. load When a short circuit occurs in the load, I load The voltage across resistor R2 increases sharply. By adjusting the values ​​of resistors R3 and R4, the PNP transistor Q1 can be made to conduct when the current across resistor R2 reaches the current-limiting threshold, thereby triggering the NPN transistor Q3 to conduct. The voltage between the collector and emitter of the NPN transistor Q3 approaches 0V, causing the NPN transistor Q2 to transition from the on to the off state, thus allowing the current I to increase dramatically. load Get smaller, I load As the resistor R2 decreases, the voltage across it also decreases, ultimately causing both PNP transistor Q1 and NPN transistor Q3 to operate in the amplification region. load Limited by current-limiting current I LIMIT To achieve stable current limiting, the current limiting threshold can be set according to actual conditions. Generally, the voltage V between the base and emitter of the PNP transistor Q1 is... be(Q1) Between -0.5V and -0.7V. Current limiting current I. LIMIT It can be represented as:

[0062]

[0063] Wherein, the V be(Q1) R1 is the voltage between the base and emitter of the switching transistor Q1, R2 is the resistance of resistor R2, R3 is the resistance of resistor R3, and R4 is the resistance of resistor R4.

[0064] In the high-voltage protection unit, the function of the diode D1 connected in series with the ground terminal (GND) of the LDO chip is to raise the output voltage U of the regulator. D1 U D1 The forward voltage of diode D1 is U, at which point the output voltage of the LDO chip is U. U1 U U1 =U LDO +U D1 U LDO This is the regulated voltage specified in the LDO chip datasheet, i.e., the output voltage of the LDO chip when diode D1 is not used.

[0065] The output voltage V at the output terminal Vout out =U U1 -U D2 U D2 Given the forward voltage of diode D2, the output voltage Vout at the output terminal is V. out =U LDO +U D1 -U D2 Because the LDO chip itself typically consumes very little current, U D1 ≈U D2 Therefore, the output voltage Vout at the output terminal is V out =U LDO In other words, diode D1 is used to ensure that the forward voltage drop of diode D2 will not affect the regulated output voltage of the LDO chip, while diode D2 is used to prevent high voltage input, ensuring that the power supply module supplying power to the LDO chip will not be damaged if the user makes a wiring error.

[0066] The use of terms such as "an embodiment / method" indicates that a specific feature, structure, or characteristic described in connection with that embodiment / method is included in at least one embodiment / method of this application. Without contradiction, those skilled in the art can combine and integrate the different embodiments / methods and features described in this specification. Those skilled in the art should understand that the above embodiments are merely for clearly illustrating this disclosure and are not intended to limit the scope of this disclosure. Other improvements and variations directly derived or conceived by those skilled in the art without departing from the spirit and concept of this utility model should be considered to be included within the protection scope of this utility model.

Claims

1. A low-power LDO voltage regulator circuit, characterized in that, It includes an LDO chip, input capacitors, output capacitors, and a power reduction unit to reduce the power consumption of the LDO chip. The power reduction unit includes a resistor R1 connected between the input and output terminals of the LDO chip and / or a resistor R2 connected in series with the input terminal of the LDO chip. One end of the input capacitor is connected to the input terminal of the LDO chip, and the other end of the input capacitor is grounded. One end of the output capacitor is connected to the output terminal of the LDO chip, and the other end of the output capacitor is grounded.

2. The low-power LDO regulator circuit of claim 1, wherein, The output terminal of the LDO chip is electrically connected to the load, and the resistance value of the resistor R1 satisfies: Among them, V in(LDO) V is the input voltage of the LDO chip. out(LDO) I is the output voltage of the LDO chip. LDO(max) I is the maximum allowable current of the LDO chip. load(max) This represents the maximum operating current of the load.

3. The low-power LDO regulator circuit of claim 1, wherein, One end of the resistor R2 is connected to an input voltage V in The other end of the resistor R2 is connected to an input terminal of an LDO chip, an output terminal of the LDO chip is connected to a load, and the resistance R2 of the resistor R2 satisfies: where V out(LDO) is the output voltage of the LDO chip, V drop_LDO is the minimum input voltage drop of the LDO chip, I load(max) is the maximum operating current of the load.

4. The low-power LDO regulator circuit of claim 1, wherein, When the power reduction unit includes a resistor R2 connected in series with the input terminal of the LDO chip, the low-power LDO voltage regulator circuit also includes a current limiting protection unit for limiting the current of the LDO chip. The current limiting protection unit includes resistors R3, R4, R5, R6, and R7, and switching transistors Q1, Q2, and Q3. The third electrode of the switching transistor Q2 is connected to the second electrode of the switching transistor Q2 through resistor R5. The third electrode of the switching transistor Q2 is connected to the input voltage. The first electrode of the switching transistor Q2 is connected to the first electrode of the switching transistor Q1, one end of resistor R3, and one end of resistor R2. The other end of resistor R3 is connected to the second electrode of the switching transistor Q1 and one end of resistor R4. The other end of resistor R4 is connected to the other end of resistor R2.

5. The low-power LDO regulator circuit of claim 4, wherein, The third electrode of the switching transistor Q1 is connected to one end of resistor R6 and resistor R7. The other end of resistor R7 is grounded. The other end of resistor R6 is connected to the second electrode of the switching transistor Q3. The third electrode of the switching transistor Q3 is connected to the second electrode of the switching transistor Q2. The first electrode of the switching transistor Q3 is grounded.

6. The low-power LDO regulator circuit of claim 5, wherein, The switching transistor Q1 is a PNP transistor, and the switching transistors Q2 and Q3 are NPN transistors.

7. The low-power LDO regulator circuit of claim 6, wherein, The current limiting protection unit limits the current of the LDO chip output current, and the current limiting current I LIMIT Can be expressed as: Wherein, the V be(Q1) Is the voltage between the base and the emitter of the switch tube Q1, R2 is the resistance value of the resistor R2, R3 is the resistance value of the resistor R3, and R4 is the resistance value of the resistor R4.

8. The low-power LDO regulator circuit of claim 1, wherein, It also includes a high-voltage protection unit, which includes diode D1 and diode D2. The positive terminal of diode D1 is connected to the ground terminal of the LDO chip, and the negative terminal of diode D1 is grounded. The positive terminal of diode D2 is connected to the output terminal of the LDO chip, and the negative terminal of diode D2 is connected to the load.

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