Micro LED FPCB bonding pad heightening structure

Abstract

The utility model discloses a Micro LED FPCB (Flexible Printed Circuit Board) bonding pad heightening structure. The Micro LED FPCB bonding pad heightening structure comprises a heat dissipation substrate, a CMOS (Complementary Metal Oxide Semiconductor) circuit chip, an LED chip and an FPC (Flexible Printed Circuit) board, the CMOS circuit chip and the LED chip are connected through flip-chip bonding to form a semi-finished product module, and then the semi-finished product module is fixed on the heat dissipation substrate; the FPC circuit board is arranged on the heat dissipation substrate, and the FPC circuit board and the CMOS circuit chip are arranged at an interval; a golden finger bonding pad is arranged on the FPC circuit board; a heightening mechanism for heightening the position of the golden finger bonding pad so as to reduce the arc height of the bonding wire is arranged above or below the golden finger bonding pad; the heightening mechanism is connected and conducted to the CMOS circuit chip through a gold wire; according to the invention, the height of a wire arc of a welding wire is effectively reduced, the risk of electrical failure of a product caused by too high wire arc is reduced, and the reliability of the product is improved; meanwhile, the use amount of gold threads is reduced by reducing the height of the wire arc, and the production cost is reduced; the performance of the product is improved, and high practical value and economic value are achieved.

Description

Technical Field

[0001] This utility model relates to the technical field of semiconductor FPCB circuit structure, specifically to a Micro LED FPCB pad elevation structure. Background Technology

[0002] In the combined application of Micro LED and FPCB, traditional pad structures present numerous problems. With the continuous development of display technology, the requirements for FPCB circuit structures are becoming increasingly stringent, especially in products pursuing high quality and high reliability. Excessive wire arc height has become a key factor restricting product performance improvement. Excessive arc height not only increases product thickness, affecting the design for thinner and lighter products, but also negatively impacts appearance, reducing aesthetics. More importantly, during product use, the arc is prone to deformation under thermal shock, easily leading to breakage and electrical failure, severely affecting product reliability and lifespan. Furthermore, excessive arc height increases the amount of gold wire used, raising production costs. Therefore, developing a Micro LED FPCB pad elevation structure that can effectively reduce wire arc height, improve product performance and reliability, and reduce costs is of significant practical importance. Utility Model Content

[0003] The purpose of this invention is to provide a Micro LED FPCB pad elevation structure. By setting up an elevation mechanism, the arc height of the solder wire is effectively reduced, the reliability of the product is improved, the amount of gold wire used is reduced, the production cost is reduced, and the overall performance of the product is improved.

[0004] To achieve the above objectives, the technical solution adopted by this utility model is: a Micro LED FPCB pad elevation structure, including a heat dissipation substrate, a CMOS circuit chip, an LED chip, and an FPC circuit board;

[0005] The CMOS circuit chip and LED chip are connected by flip-chip bonding to form a semi-finished module, which is then fixed on the heat dissipation substrate;

[0006] The FPC circuit board is disposed on the heat dissipation substrate and is spaced apart from the CMOS circuit chip.

[0007] The FPC circuit board is provided with gold finger pads; a shim mechanism is provided above or below the gold finger pads to raise the position of the gold finger pads so as to reduce the arc height of the solder wires.

[0008] The elevation mechanism is connected to the CMOS circuit chip via a gold wire.

[0009] In a preferred embodiment, the elevation mechanism includes a first elevation unit; the first elevation unit includes a CMOS silicon wafer circuit board; the CMOS silicon wafer circuit board has through-hole pads; the through-hole pads are filled with conductive metal; the top and bottom surfaces of the CMOS silicon wafer circuit board are gold-plated; the CMOS silicon wafer circuit board is connected to the gold finger pads by flip-chip bonding.

[0010] In a preferred embodiment, the width and thickness of the CMOS silicon wafer circuit substrate are consistent with the width and thickness of the CMOS circuit chip.

[0011] In a preferred embodiment, the conductive metal is made of copper, silver, or tin; and the gold plating thickness on the top and bottom surfaces of the CMOS silicon wafer circuit board is 300-600 nm.

[0012] In a preferred embodiment, the elevation mechanism includes a second elevation unit; the second elevation unit is a heat dissipation substrate with an L-shaped structure and a step, wherein the height of the step is 0.1 mm lower than that of the CMOS circuit chip; the FPC circuit board is attached to the step of the heat dissipation substrate, and the thickness of the FPC circuit board is 0.1 mm.

[0013] In a preferred embodiment, the semi-finished module is fixed to the heat dissipation substrate using a die bonding machine with a fixing material, wherein the fixing material is one of epoxy resin, silicone, silver paste, or UV adhesive.

[0014] In a preferred embodiment, the semi-finished module is fixed to the FPCB heat dissipation substrate using an adhesive material via SMT bonding, wherein the adhesive material is one of epoxy resin, silicone, silver paste, or UV adhesive.

[0015] Due to the application of the above technical solution, the beneficial effects of this application compared with the prior art are as follows:

[0016] This application discloses a Micro LED FPCB pad elevation structure. By setting a first elevation unit or a second elevation unit, it effectively reduces the arc height of the solder wires, thereby reducing the risk of electrical failure caused by excessive arc height and improving product reliability. Simultaneously, the reduced arc height decreases the amount of gold wire used, lowering production costs. Furthermore, the design of the first elevation unit utilizing a CMOS silicon wafer circuit board allows for the recycling of CMOS circuit chip scraps to some extent, further reducing costs. The second elevation unit, through a simple shape improvement of the heat dissipation substrate—designed as an L-shaped stepped structure—is simple to manufacture and has low production difficulty. Overall, this invention's elevation structure improves product performance and has high practical and economic value. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Appendix Figure 1 This is a schematic diagram of the Micro LED FPCB pad elevation structure of this utility model;

[0019] Appendix Figure 2 This is a schematic diagram of the first elevation unit of this utility model;

[0020] Appendix Figure 3 This is another schematic diagram of the Micro LED FPCB pad elevation structure of this utility model;

[0021] The components are: 1. Heat dissipation substrate; 2. CMOS circuit chip; 3. LED chip; 4. FPC circuit board; 5. Gold finger pads; 6. First elevation unit; 7. CMOS silicon wafer circuit board; 8. Pad holes; 9. Conductive metal; 10. Second elevation unit; 11. Step. Detailed Implementation

[0022] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing the present invention and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0025] Furthermore, in addition to indicating direction or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this utility model according to the specific circumstances.

[0026] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this utility model based on the specific circumstances.

[0027] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] Example 1

[0029] Appendix Figure 1 and 2 The present invention provides a Micro LED FPCB pad elevation structure (wherein the elevation mechanism adopts a first elevation unit 6), which includes a heat dissipation substrate 1, a CMOS circuit chip 2, an LED chip 3, and an FPC circuit board 4.

[0030] The CMOS circuit chip 2 and LED chip 3 are connected by flip-chip bonding to form a semi-finished module. This connection method can achieve efficient electrical connection between the chips. Then, the module is fixed on the heat dissipation substrate 1, providing a foundation for subsequent circuit connection and heat dissipation.

[0031] The FPC circuit board 4 is disposed on the heat dissipation substrate 1 and spaced apart from the CMOS circuit chip 2; this layout is conducive to the rational planning of the circuit and signal transmission.

[0032] The FPC circuit board 4 is provided with gold finger pads 5, which are important components for realizing the electrical connection between the FPC circuit board and other components. Above or below the gold finger pads 5, there is a shim mechanism for raising the position of the gold finger pads 5 to reduce the arc height of the solder wires. The function of the shim mechanism is to raise the position of the gold finger pads 5, thereby reducing the arc height of the solder wires.

[0033] The elevation mechanism is connected to the CMOS circuit chip 2 via a gold wire to achieve electrical connection and ensure stable signal transmission.

[0034] The elevation mechanism includes a first elevation unit 6; the first elevation unit 6 includes a CMOS silicon wafer circuit board 7; the CMOS silicon wafer circuit board 7 is provided with through-hole pads 8; the through-hole pads 8 are filled with conductive metals 9, such as copper, silver or tin, which have good conductivity and can ensure the reliability of electrical connection; the top and bottom surfaces of the CMOS silicon wafer circuit board 7 are gold-plated with a gold plating thickness of 300-600nm, preferably 400-450nm, which can ensure the reliability of soldering and control costs to a certain extent; the CMOS silicon wafer circuit board 7 is connected to the gold finger pads 5 by flip-chip soldering, thereby elevating the gold finger pads 5.

[0035] To ensure accurate alignment of the pads, the width and thickness of the CMOS silicon circuit substrate 7 are consistent with the width and thickness of the CMOS circuit chip 2.

[0036] The specific production steps include the following:

[0037] First, based on product design requirements, Micro LED chips 3 that meet the size requirements are fabricated. Their emission color can be selected according to actual applications, such as red, green, blue, or purple light. The fabrication process of the Micro LED chip includes epitaxial growth, chip fabrication, and substrate lift-off. During epitaxial growth, III-V group semiconductor materials (such as GaN and InGaN) are typically selected on sapphire or silicon substrates, and multilayer structures (n-type layer, quantum well, p-type layer) are grown using MOCVD (metal-organic chemical vapor deposition) technology. In the chip fabrication stage, the Micro LED chip is defined by photolithography. The LED pattern (typically <50μm in size) is then formed using dry etching (such as ICP-RIE) to create a mesa structure, exposing the n-type and p-type layers. Then, a transparent conductive layer (such as ITO) and metal electrodes (Au, Al) are deposited to create electrodes, and a SiO2 or SiN protective layer is applied as a passivation layer. During substrate lift-off, for sapphire substrates, laser lift-off (LLO) technology is used to decompose the GaN buffer layer at the interface, transfer the epitaxial layer to a temporary substrate, and then the epitaxial layer is thinned by chemical mechanical polishing (CMP) to improve the light extraction efficiency.

[0038] Simultaneously, CMOS circuit chip 2 is fabricated according to design requirements. The fabrication process of CMOS circuit chip 2 includes substrate preparation, well region formation, isolation technology, gate fabrication, source / drain region formation, siliconization, interconnect layer, passivation, and packaging. In the substrate preparation stage, silicon wafers (single-crystal silicon, mainly 300mm / 12 inches in diameter) are commonly used. Different doping types are selected according to the transistor type. For example, P-type substrates (boron doped) are used for NMOS transistors, while N-type substrates (phosphorus / arsenic doped) need to form P-wells (PMOS regions) through epitaxial growth or ion implantation. Well region formation is achieved through photolithography and ion implantation. The process involves defining the well pattern and implanting boron (P-well) or phosphorus / arsenic (N-well). A twin-well process is used to simultaneously form N-wells and P-wells on a P-type substrate, followed by high-temperature annealing to activate doped atoms and repair lattice damage (approximately 1000°C). For isolation, shallow trench isolation (STI, the mainstream technology) is employed. Dry etching of silicon forms shallow trenches, which are then filled with SiO2 (HDP-CVD) and planarized using chemical mechanical polishing (CMP). During gate fabrication, ultrathin SiO2 (1-3 nm) is grown by thermal oxidation or high-dielectric-constant materials (such as HfO2) are deposited, using HKMG ( For a high-k dielectric metal gate (using modern processes), first deposit a high-k dielectric such as HfO2, then cover it with a metal gate such as TiN / TaN (post-gate processing avoids high-temperature damage); source / drain region formation includes lightly doped drain (LDD) implantation of low-dose impurities (such as phosphorus / boron) to reduce short-channel effects, deposition of SiN or SiO2 followed by anisotropic etching to form protective sidewalls, high-concentration implantation of arsenic (NMOS) or boron (PMOS) to form low-resistance source / drain regions, and finally, rapid thermal annealing (RTA) to activate impurities; during silicide formation, Ni or Co is deposited, followed by high-temperature annealing to form low-resistance silicides (NiSi / Co). Si2) reduces gate / source / drain contact resistance; the interconnect layer reduces parasitic capacitance by depositing SiO2 (CVD) or low-κ dielectric (such as SiCOH) as interlayer dielectric, and uses dual damascene process (the mainstream of copper interconnect) for via and metallization, including etching via / trench patterns, depositing TaN / Ta barrier layer and copper seed layer, electroplating copper fill, and CMP polishing. Modern chips can have 10-15 metal layers; in the passivation and packaging stage, SiN or polyimide is deposited as passivation layer to protect the chip from moisture / mechanical damage, and the passivation layer is etched to expose aluminum / copper pads for wire bonding or flip-chip bonding.

[0039] Next, the Micro LED chip 3 and the CMOS circuit chip 2 are connected by hybrid bonding using micro-soldering points (such as Cu-Cu, indium balls, and solder balls) to form a semi-finished module. The CMOS silicon circuit substrate 7 is then fabricated, with some steps consistent with the fabrication process of the CMOS circuit chip 2, but requiring additional hole-punching and filling processes to make the top and bottom of the CMOS silicon circuit substrate 7 conductive, obtaining pad holes 8 of uniform size. Conductive metal 9 (such as copper, silver, or tin) is then filled into the pad holes 8, and gold plating is applied to the top and bottom surfaces, with the gold plating thickness controlled at 400-450nm. Finally, flip-chip bonding is used to connect the conductive metal in the pad holes 8 on the CMOS silicon circuit substrate 7. Metal 9 and the gold finger pads 5 of the FPC circuit board 4 are bonded together. Flip-chip bonding can be performed using vacuum soldering (vacuum gas is nitrogen) or soldering with solder paste and silver paste. The semi-finished module is fixed to the FPCB heat sink substrate 1 by SMT bonding, using silver paste as the bonding material. Finally, ultrasonic welding is performed using wire bonding equipment (such as a KS wire bonding machine) to connect the semi-finished module and the CMOS silicon wafer circuit board 7 with gold wire. The gold wire welding parameters are controlled by certain pressure, power, and friction. After welding is completed, photoelectric detection is performed to check brightness, wavelength, power consumption, uniformity, and display defects such as dead pixels and dead pixels (no light).

[0040] Example 2

[0041] Appendix Figure 3 The present invention discloses a Micro LED FPCB pad elevation structure, wherein the elevation mechanism adopts a second elevation unit 10; the second elevation unit 10 is an L-shaped heat dissipation substrate 1 with a step 11, wherein the height of the step 11 is 0.1mm lower than that of the CMOS circuit chip 2; the FPC circuit board 4 is attached to the step 11 of the heat dissipation substrate 1, and the thickness of the FPC circuit board 4 is 0.1mm. This design cleverly achieves the elevation of the FPC circuit board 4, thereby reducing the arc height of the solder wires.

[0042] The specific production steps include the following:

[0043] The FPCB heat dissipation substrate 1 is designed as an L-shaped structure with a step 11, ensuring that the height of the step 11 is 0.1mm lower than the CMOS circuit chip 2 after die bonding. An FPC circuit board 4 with a thickness of 0.1mm is prepared and bonded to the step 11 of the heat dissipation substrate 1 by SMT bonding. The bonding adhesive is epoxy resin or silicone system, and the adhesive is cured by heating. The Micro LED chip 3 and the CMOS circuit chip 2 are connected by hybrid bonding using micro solder joints (such as Cu-Cu, indium balls, solder balls) to form a semi-finished module. The semi-finished module is fixed to the FPCB heat dissipation substrate 1 by SMT bonding, and silver paste is preferred as the bonding material. Ultrasonic welding is performed using wire bonding equipment (such as KS wire bonding machine) to connect the gold finger pads 5 on the semi-finished module and the FPC circuit board 4 with gold wire. The gold wire welding parameters are controlled by certain pressure, power and friction. Finally, photoelectric testing is performed to check brightness, wavelength, power consumption, uniformity, and display defects such as dead pixels and blank pixels (not lit).

[0044] In the above embodiments, there are multiple ways to fix the semi-finished module. On the one hand, the semi-finished module can be fixed to the heat dissipation substrate 1 using a die bonder and a fixing material, which can be one of epoxy resin, silicone, silver paste, or UV adhesive. On the other hand, the semi-finished module can also be fixed to the FPCB heat dissipation substrate 1 by SMT bonding, and the bonding material can also be one of epoxy resin, silicone, silver paste, or UV adhesive. Among these fixing and bonding materials, silver paste is preferred due to its good heat dissipation and strong adhesion.

[0045] This application discloses a Micro LED FPCB pad elevation structure. By setting a first elevation unit 6 or a second elevation unit 10, it effectively reduces the arc height of the solder wires, thereby reducing the risk of electrical failure caused by excessive arc height and improving product reliability. Simultaneously, the reduced arc height decreases the amount of gold wire used, lowering production costs. Furthermore, the design of the first elevation unit 6 utilizing the CMOS silicon wafer circuit board 7 allows for the recycling of scrap materials from the CMOS circuit chip 2, further reducing costs. The second elevation unit 10, through a simple shape improvement of the heat dissipation substrate 1—designed as an L-shaped step 11 structure—is simple to manufacture and has low production difficulty. Overall, the elevation structure of this invention improves product performance and has high practical and economic value.

[0046] Finally, it should be noted that the above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A Micro LED FPCB pad elevation structure, characterized in that: This includes a heat dissipation substrate, CMOS circuit chips, LED chips, and FPC circuit boards. The CMOS circuit chip and LED chip are connected by flip-chip bonding to form a semi-finished module, which is then fixed on the heat dissipation substrate; The FPC circuit board is disposed on the heat dissipation substrate and is spaced apart from the CMOS circuit chip. The FPC circuit board is provided with gold finger pads; a shim mechanism is provided above or below the gold finger pads to raise the position of the gold finger pads so as to reduce the arc height of the solder wires. The elevation mechanism is connected to the CMOS circuit chip via a gold wire.

2. The Micro LED FPCB pad elevation structure according to claim 1, characterized in that: The elevation mechanism includes a first elevation unit; the first elevation unit includes a CMOS silicon wafer circuit board; the CMOS silicon wafer circuit board has through-hole pads; the through-hole pads are filled with conductive metal; the top and bottom surfaces of the CMOS silicon wafer circuit board are gold-plated; the CMOS silicon wafer circuit board is connected to the gold finger pads by flip-chip bonding.

3. The Micro LED FPCB pad elevation structure according to claim 2, characterized in that: The width and thickness of the CMOS silicon wafer circuit substrate are the same as the width and thickness of the CMOS circuit chip.

4. The Micro LED FPCB pad elevation structure according to claim 2, characterized in that: The conductive metal is made of copper, silver, or tin; the gold plating thickness on the top and bottom surfaces of the CMOS silicon wafer circuit board is 300-600 nm.

5. The Micro LED FPCB pad elevation structure according to claim 1, characterized in that: The elevation mechanism includes a second elevation unit; the second elevation unit is a heat dissipation substrate with an L-shaped structure and a step, wherein the height of the step is 0.1 mm lower than that of the CMOS circuit chip; the FPC circuit board is attached to the step of the heat dissipation substrate, and the thickness of the FPC circuit board is 0.1 mm.

6. The Micro LED FPCB pad elevation structure according to claim 1, characterized in that: The semi-finished module is fixed to the heat dissipation substrate using a die bonding machine with a fixing material, wherein the fixing material is one of epoxy resin, silicone, silver paste, or UV adhesive.

7. The Micro LED FPCB pad elevation structure according to claim 1, characterized in that: The semi-finished module is fixed to the FPCB heat dissipation substrate by SMT bonding using an adhesive, wherein the adhesive is one of epoxy resin, silicone, silver paste, or UV adhesive.

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