Ultra-wideband high-linearity low-noise amplifier circuit based on common-source structure

Abstract

The utility model discloses an ultra-wideband high-linearity low-noise amplifier circuit based on a common source structure, which comprises a first amplifying circuit, an inter-stage matching circuit and a second amplifying circuit which are sequentially cascaded, the drain electrode of the first transistor of the first amplification circuit and the drain electrode of the second transistor of the second amplification circuit are provided with a common drain electrode power supply matching network. The drain electrode power supply mode of the two-stage amplification circuit is optimized and adjusted, so that the drain electrode power supply of the first amplification circuit and the drain electrode power supply of the second amplification circuit jointly pass through the common drain electrode power supply matching network, and the power supply firstly passes through the common drain electrode power supply matching network and then independently supplies power to the first amplification circuit and the second amplification circuit. In addition, in order to expand the bandwidth, LC parallel connection is added to the input matching network of the first amplification circuit and the output matching network of the second amplification circuit, and the bandwidth is expanded by introducing the LC parallel connection to the ground.

Description

An ultrawideband high-linearity low-noise amplifier circuit based on a common-source structure Technical Field

[0001] This invention relates to the field of microwave and millimeter-wave technology, and specifically to an ultrawideband, high-linearity, low-noise amplifier circuit based on a common-source structure. Background Technology

[0002] Wideband high-linearity low-noise amplifier circuits are key circuits that amplify weak signals over a wide frequency range while maintaining low noise figure and high linearity. They are widely used in communication systems, radar, RF receivers, and test instruments. Designing a wideband high-linearity low-noise amplifier circuit requires comprehensive consideration of bandwidth, noise, linearity, and stability. Its key technology lies in extending the frequency band while maintaining a low noise figure and high linearity within the passband. Maintaining a low noise figure, such as NF < 2dB, can improve receiver sensitivity. Generally, high-linearity transistors have an OIP3 > 20dBm to suppress intermodulation distortion. Input and output return losses are typically kept < -15dB to ensure good matching between input and output ports and reduce port losses.

[0003] Currently, common broadband low-noise amplifier circuit topologies include distributed circuits and cascode (CC) structures. Distributed circuits can achieve ultra-wide bandwidth, but their high-frequency noise is poor, and they often use multiple stages, resulting in a larger overall area. Cascode structures can achieve high gain and high power, reducing the Miller effect, but their power consumption is relatively high. Designing ultra-wideband, high-linearity, low-noise transistors using cascode structures is challenging and not widely used. How to use cascode structures to extend bandwidth and improve linearity while optimizing the noise figure has become a pressing problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide an ultra-wideband, high-linearity, low-noise amplifier circuit based on a common-source structure. With this common-source structure, the common drain power supply matching network supplies power to the drains of the first amplifier circuit and the second amplifier circuit respectively, thereby widening the bandwidth of the circuit and improving its linearity.

[0005] To solve the above-mentioned technical problems, the present invention adopts the following solution:

[0006] An ultrawideband high linearity low noise amplifier circuit based on a common-source structure includes a first amplifier circuit, an interstage matching circuit, and a second amplifier circuit cascaded in sequence, wherein the drain of the first transistor in the first amplifier circuit and the drain of the second transistor in the second amplifier circuit have a common drain power supply matching network.

[0007] In some specific implementations, the first amplifier circuit includes an input matching network, a first gate bias network, a first-stage feedback network, and a first transistor, wherein the input matching network and the first gate bias network are respectively connected to the gate of the first transistor, and the first-stage feedback network is disposed between the first gate bias network and the common drain power supply matching network.

[0008] In some specific implementations, the input matching network includes a DC blocking capacitor C10, an input broadband matching circuit, microstrip lines TL11, TL12, and TL13. The DC blocking capacitor C10, microstrip line TL11, and microstrip line TL12 are connected in series, and microstrip line TL12 is connected to the gate of the first transistor. Microstrip line TL13 is connected to the source of the first transistor. The input broadband matching circuit is connected in parallel between the DC blocking capacitor C10 and microstrip line TL11. The first gate bias network is connected in parallel between microstrip line TL11 and microstrip line TL12.

[0009] In some specific implementations, the input broadband matching circuit includes an inductor L4 and a capacitor C11 connected in series. One end of the inductor L4 is connected in parallel between the DC blocking capacitor C10 and the microstrip line TL11, and the other end of the inductor L4 is connected in series with the capacitor C11 and grounded.

[0010] In some specific implementations, the common drain common matching network includes a resistor R8, a filter capacitor C18, and a choke inductor L6. One end of the resistor R8 is connected to the power supply VD, and the other end is connected to ground in series with the filter capacitor C18. One end of the choke inductor L6 is connected to the power supply VD, and the other end is connected to the first amplifier circuit and the second amplifier circuit, respectively.

[0011] In some specific implementations, the interstage matching circuit includes capacitors C14 and C15 connected in series and a microstrip line TL18. Capacitor C14 is connected to the drain of the first transistor, and microstrip line TL18 is connected to the gate of the second transistor. Microstrip line TL16 is connected in parallel between capacitors C14 and C15 to ground.

[0012] In some specific implementations, the second amplifier circuit includes a second gate bias network, a second transistor, a second-stage feedback network, and an output matching network. The second gate bias network is connected to the gate of the second transistor, the second-stage feedback network is connected in parallel between the inter-stage matching network and the output matching network, and the output matching network is connected to the drain of the second transistor.

[0013] In some specific implementations, the output matching network includes microstrip line TL21, microstrip line TL22, microstrip line TL20, capacitor C19, and output broadband matching circuit. Microstrip line TL21, microstrip line TL22, and capacitor C19 are connected in series. Microstrip line TL21 is connected to the drain of the second transistor. Capacitor C19 is connected to the RF output terminal. The output broadband matching circuit is connected in parallel between capacitor C19 and microstrip line TL22. The second-stage feedback network is connected in parallel between microstrip line TL21 and microstrip line TL22. An inductor L7 is provided between the common drain power supply matching network and the output matching network. One end of inductor L7 is connected in parallel between microstrip line TL21 and microstrip line TL22, and the other end is connected to the common drain power supply matching network.

[0014] In some specific implementations, the output broadband matching circuit includes an inductor L8 and a capacitor C20 connected in series. One end of the inductor L8 is connected in parallel between the capacitor C19 and the microstrip line TL22, and the other end is connected in series with the capacitor C20 and then grounded.

[0015] In some specific implementations, microstrip lines TL14, TL15, and TL17 are connected between the common drain power supply matching network and the drain of the first transistor. One end of microstrip line TL14 is connected to the drain of the first transistor, and the other end is connected to the interstage matching network. One end of microstrip line TL15 is connected in parallel between microstrip line TL14 and the interstage matching network, and the other end is connected in series with one end of microstrip line TL17. The other end of microstrip line TL17 is connected to the common drain power supply matching network. The first-stage feedback network is connected in parallel between microstrip lines TL15 and TL17.

[0016] The beneficial effects of this utility model are:

[0017] This application optimizes the drain power supply method of the two-stage amplifier circuit. The drain power supplies of the first and second amplifier circuits share a common drain power supply matching network. The power supply first passes through the common drain power supply matching network before supplying power to the first and second amplifier circuits separately. Furthermore, to expand the bandwidth, LC circuits connected in parallel to ground are added to the input matching network of the first amplifier circuit and the output matching network of the second amplifier circuit. This LC parallel connection to ground expands the bandwidth.

[0018] The interstage matching network has been changed from the original single-capacitor matching method to a microstrip line-to-ground matching network with two capacitors connected in series and then connected in parallel between the two capacitors, which is equivalent to an inductor. This can better match the output impedance of the first-stage transistor and the input impedance of the second-stage transistor. Attached Figure Description

[0019] Figure 1 is a schematic diagram of an ultrawideband high linearity low noise amplifier circuit based on a common source structure provided in an embodiment of the present invention.

[0020] Figure 2 is a schematic diagram of the circuit connection of an ultrawideband high linearity low noise amplifier circuit based on a common source structure provided in an embodiment of this utility model.

[0021] Figure 3 is a schematic diagram of the gain S21 simulation curve of the low noise amplifier of this application compared with the general common source structure provided in the embodiment of this utility model;

[0022] Figure 4 is a schematic diagram of the noise figure NF simulation curve of this utility model embodiment compared with a general common-source low-noise amplifier.

[0023] Figure 5 is a schematic diagram of the linearity OIP3 simulation curve of this application compared with a general common-source low-noise amplifier in this embodiment of the present invention. Detailed Implementation

[0024] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the implementation of the present invention is not limited thereto.

[0025] In the description of this utility model, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "longitudinal", "lateral", "horizontal", "inner", "outer", "front", "rear", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the utility model product is in use. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0026] In the description of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set up," "have," "install," "connect," and "connect" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0027] The present invention will now be described in detail with reference to the accompanying drawings and embodiments:

[0028] Example 1:

[0029] As shown in Figure 1, this embodiment provides an ultra-wideband, high-linearity, low-noise amplifier circuit based on a common-source structure, including a first amplifier circuit, an inter-stage matching circuit, and a second amplifier circuit cascaded in sequence. The drains of the first transistor in the first amplifier circuit and the drains of the second transistor in the second amplifier circuit share a common drain power supply matching network. Both the first transistor M1 and the second transistor M2 are E-mode transistors.

[0030] As shown in Figure 2, the first amplifier circuit includes an input matching network, a first gate bias network, a first-stage feedback network, and a first transistor M1. The input matching network and the first gate bias network are respectively connected to the gate of the first transistor M1, and the first-stage feedback network is disposed between the first gate bias network and the common drain power supply matching network.

[0031] The input matching network includes a DC blocking capacitor C10, an input broadband matching circuit, microstrip lines TL11, TL12, and TL13. The DC blocking capacitor C10, microstrip line TL11, and microstrip line TL12 are connected in series, with microstrip line TL12 connected to the gate of the first transistor and microstrip line TL13 connected to the source of the first transistor M1. The input broadband matching circuit is connected in parallel between the DC blocking capacitor C10 and microstrip line TL11. The first gate bias network is connected in parallel between microstrip lines TL11 and TL12. The DC blocking capacitor C10 is connected to the RF input terminal RFin.

[0032] Specifically, the input broadband matching circuit includes an inductor L4 and a capacitor C11 connected in series. One end of the inductor L4 is connected in parallel between the DC blocking capacitor C10 and the microstrip line TL11, and the other end of the inductor L4 is connected in series with the capacitor C11 and grounded. The input broadband matching circuit can extend the bandwidth and also block DC at the input. Adjusting the length of the microstrip line TL13 connected to the first transistor M1 can balance the noise figure and gain.

[0033] The first gate bias network includes a filter capacitor C13 and an inductor L5. The first-stage feedback network includes a resistor R6 and a capacitor C12. One end of the inductor L5 is connected in parallel between microstrip lines TL11 and TL12, and the other end is connected to power supply VG1. One end of the filter capacitor C13 is connected in parallel with the inductor L5 and then connected to power supply VG1, while the other end is grounded. One end of the resistor R6 is connected in parallel with the inductor L5, and the other end is connected in series with the capacitor C12. The capacitor C12 is connected in parallel between microstrip lines TL15 and TL17. The first-stage feedback network can participate in noise figure and VSWR matching, and can also expand the bandwidth and adjust the gain flatness.

[0034] Specifically, the second amplifier circuit includes a second gate bias network, a second transistor M2, a second-stage feedback network, and an output matching network. The second gate bias network is connected to the gate of the second transistor M2, the second-stage feedback network is connected in parallel between the inter-stage matching network and the output matching network, and the output matching network is connected to the drain of the second transistor M2.

[0035] Specifically, the output matching network is connected to the external environment via the RF output terminal RFout. The output matching network includes microstrip lines TL21, TL22, and TL20, capacitor C19, and an output broadband matching circuit. Microstrip lines TL21, TL22, and capacitor C19 are connected in series. Microstrip line TL21 is connected to the drain of the second transistor, and capacitor C19 is connected to the RF output terminal. The output broadband matching circuit is connected in parallel between microstrip line TL22 and capacitor C19. The output broadband matching circuit includes an inductor L8 and capacitor C20 connected in series. One end of inductor L8 is connected in parallel between microstrip line TL22 and capacitor C19, and the other end is connected in series with capacitor C20 and then grounded. Capacitor C11 and inductor L4 can extend the bandwidth and also block DC output. Adjusting the length of microstrip line TL20, which is connected to the second-stage transistor M2, can balance the output VSWR and gain.

[0036] Specifically, the second gate bias network consists of a filter capacitor C16 and a resistor R7. One end of resistor R7 is connected in parallel between the gate of microstrip line TL18 and the second transistor M2, and the other end is connected to the power supply VG2. One end of capacitor C17 is connected in parallel with resistor R7 and then connected to the power supply VG2, and the other end is grounded. The value of resistor R7 is relatively large, typically around several thousand ohms. The first gate bias network participates in matching, while the second-stage transistor gate bias network basically does not participate in circuit matching.

[0037] The second-stage feedback network includes a microstrip line TL19 connected in series, a resistor R9, and a capacitor C17. Microstrip line TL19 is connected in parallel between microstrip lines TL21 and TL22, and capacitor C17 is connected in parallel between microstrip lines TL21 and TL22. Due to the existence of the second-stage feedback network, the bandwidth can be further extended, the shape of the gain curve can be adjusted, and it also participates in the matching of output return loss and output power.

[0038] Specifically, to better match the output impedance of the first transistor M1 and the input impedance of the second transistor M2, the interstage matching network is improved. The interstage matching circuit includes capacitors C14 and C15 connected in series and a microstrip line TL18. Capacitor C14 and microstrip line TL14 are connected in series and then connected to the drain of the first transistor M1. Microstrip line TL18 is connected to the gate of the second transistor. A microstrip line TL16 is connected in parallel between capacitors C14 and C15 to ground. Microstrip line TL16 is equivalent to an inductor. This allows the matching network to be changed from a general single-capacitor matching network to a matching network structure consisting of a capacitor, a parallel inductor to ground, and another capacitor. This allows for better matching of the output impedance of the first-stage transistor and the input impedance of the second-stage transistor over a wide bandwidth.

[0039] To achieve drain power supply for the two-stage transistors, the common drain power supply matching network includes a resistor R8, a filter capacitor C18, and a choke inductor L6. One end of resistor R8 is connected to the power supply VD, and the other end is connected in series with the filter capacitor C18 and then grounded. One end of choke inductor L6 is connected to the power supply VD, and the other end is connected in parallel with microstrip line TL17 and inductor L7. Microstrip lines TL14, TL15, and TL17 connect the common drain power supply matching network to the drain of the first transistor M1. One end of microstrip line TL14 is connected to the drain of the first transistor M1, and the other end is connected to capacitor C14 in the interstage matching network. One end of microstrip line TL15 is connected in parallel between microstrip line TL14 and the interstage matching network, and the other end is connected in series with one end of microstrip line TL17. The other end of microstrip line TL17 is connected to inductor L6 in the common drain power supply matching network. An inductor L7 is provided between the common drain power supply matching network and the output matching network. One end of the inductor L7 is connected in parallel between microstrip line TL21 and microstrip line TL22, and the other end is connected to the inductor L6 of the common drain power supply matching network.

[0040] The power supply VD first passes through R8, filter capacitor C18, and choke inductor L6 in the common branch, and then supplies power to the drain of each stage transistor individually. The first stage supplies power to the drain of the first transistor M1 through microstrip lines TL17, TL15, and TL14. The second stage supplies power to the drain of the second transistor M2 through inductor L7 and microstrip line TL21. Simulation results for gain, noise figure (NF), output P-1dB, linearity OIP3, and input / output return loss show that the improved common-source structure ultra-wideband high-linearity low-noise amplifier circuit outperforms the general common-source structure low-noise amplifier.

[0041] It is understandable that the usage flow design concept of this embodiment is as follows:

[0042] When designing low-noise amplifiers using a conventional two-stage common-source structure, the bandwidth, noise figure, and gain flatness are often limited. To address these issues, this invention improves upon the common-source structure, designing an ultra-wideband, high-linearity, low-noise amplifier that simultaneously meets the technical specifications of ultra-wideband, high linearity, and low noise.

[0043] Compared to traditional two-stage common-source amplifiers, the ultra-wideband high-linearity low-noise amplifier features structural optimizations in input matching, output matching, inter-stage matching, first-stage drain power supply network, and second-stage drain power supply network. The input and output matching networks incorporate parallel LC circuits to ground, expanding the bandwidth. The inter-stage matching network has been changed from a typical single-capacitor matching network to a network consisting of a capacitor, a parallel inductor to ground, and another capacitor. This allows for better matching of the output impedance of the first-stage transistor and the input impedance of the second-stage transistor. Furthermore, the drain power supply method has been adjusted. Power is first supplied through R8, filter capacitor C18, and choke inductor L6 in the common branch, and then individually to each stage. The first stage supplies power to transistor M1 via microstrip lines TL17, TL15, and TL14. The second stage supplies power to transistor M2 via inductor L7 and microstrip line TL21. Simulation results for indicators such as gain, noise figure (NF), output P-1dB, linearity OIP3, and input / output return loss show that the novel ultra-wideband high-linearity low-noise amplifier circuit based on common-source structure outperforms the general low-noise amplifier based on common-source structure.

[0044] As shown in Figure 3, during the three-temperature test simulation (where T1 and tempv represent the three test temperatures), compared to a typical common-source low-noise amplifier, the improved common-source ultra-wideband high-linearity low-noise amplifier circuit proposed in this application exhibits a flatter gain curve in the 6-14 GHz range, without gain drop at high frequencies, and also possesses a certain positive slope. Typical common-source low-noise amplifiers experience gain drop in the mid-frequency band and reduced gain flatness within the band, often due to the limited bandwidth of the common-source low-noise amplifier. In systems, it is generally desirable to achieve a positive slope in the amplifier gain to compensate for the higher losses at high frequencies.

[0045] As shown in Figure 4, the noise figure (nf) of a typical common-source low-noise amplifier is 1.4 dB in the 6-14 GHz range, while the noise figure of the improved common-source low-noise amplifier is 1.2 dB in the same range. Compared to the typical common-source low-noise amplifier, the improved common-source ultra-wideband high-linearity low-noise amplifier improves the noise figure by 0.2 dB in the 6-14 GHz range. As shown in Figure 5, the OIP3 of a typical common-source low-noise amplifier is 27 dBm in the 6-14 GHz range, while the OIP3 of the improved common-source ultra-wideband high-linearity low-noise amplifier of this application is 28 dBm in the same range. Compared to the typical common-source low-noise amplifier, the improved common-source ultra-wideband high-linearity low-noise amplifier improves the OIP3 by 1 dBm in the 6-14 GHz range. A typical common-source low-noise amplifier (LNOA) has an input return of -10dB in the 6-14GHz range, while an improved common-source ultra-wideband high-linearity LNOA has an input return of -15dB in the same range. This represents a 5dB improvement in input return compared to the typical common-source LNOA, indicating a significant reduction in input return loss. The typical common-source LNOA also has an output return of -15dB in the 6-14GHz range, as does the improved common-source ultra-wideband high-linearity LNOA. Compared to the typical common-source LNOA, the improved common-source ultra-wideband high-linearity LNOA shows little difference in output return across the 6-14GHz range.

[0046] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of this utility model, and the utility model is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of this utility model, and these modifications and improvements are also considered to be within the protection scope of this utility model.

Claims

1. A common-source structure based ultra-wideband high linearity low noise amplifier circuit, characterized by, It includes a first amplifier circuit, an interstage matching circuit, and a second amplifier circuit cascaded in sequence, wherein the drain of the first transistor in the first amplifier circuit and the drain of the second transistor in the second amplifier circuit have a common drain power supply matching network.

2. The ultra-wideband, high-linearity, low-noise amplifier circuit based on a common-source structure according to claim 1, characterized in that, The first amplifier circuit includes an input matching network, a first gate bias network, a first-stage feedback network, and a first transistor. The input matching network and the first gate bias network are respectively connected to the gate of the first transistor, and the first-stage feedback network is disposed between the first gate bias network and the common drain power supply matching network.

3. The ultra-wideband, high-linearity, low-noise amplifier circuit based on a common-source structure according to claim 2, characterized in that, The input matching network includes a DC blocking capacitor C10, an input broadband matching circuit, microstrip lines TL11, TL12, and TL13. The DC blocking capacitor C10, microstrip line TL11, and microstrip line TL12 are connected in series, and microstrip line TL12 is connected to the gate of the first transistor. Microstrip line TL13 is connected to the source of the first transistor. The input broadband matching circuit is connected in parallel between the DC blocking capacitor C10 and microstrip line TL11. The first gate bias network is connected in parallel between microstrip line TL11 and microstrip line TL12.

4. The ultra-wideband high-linearity low-noise amplifier circuit based on common-source structure according to claim 3, characterized in that, The input broadband matching circuit includes an inductor L4 and a capacitor C11 connected in series. One end of the inductor L4 is connected in parallel between the DC blocking capacitor C10 and the microstrip line TL11, and the other end of the inductor L4 is connected in series with the capacitor C11 and grounded.

5. The ultra-wideband high linearity low noise amplifier circuit based on common-source structure according to claim 2, wherein, The common drain matching network includes a resistor R8, a filter capacitor C18, and a choke inductor L6. One end of the resistor R8 is connected to the power supply VD, and the other end is connected to ground in series with the filter capacitor C18. One end of the choke inductor L6 is connected to the power supply VD, and the other end is connected to the first amplifier circuit and the second amplifier circuit, respectively.

6. The ultra-wideband high linearity low noise amplifier circuit based on common-source structure according to claim 2, wherein, The interstage matching circuit includes capacitors C14 and C15 connected in series and microstrip line TL18. Capacitor C14 is connected to the drain output of the first transistor, and microstrip line TL18 is connected to the gate of the second transistor. Microstrip line TL16 is connected in parallel between capacitors C14 and C15 to ground.

7. The ultra-wideband, high-linearity, low-noise amplifier circuit based on a common-source structure according to claim 6, characterized in that, The second amplifier circuit includes a second gate bias network, a second transistor, a second-stage feedback network, and an output matching network. The second gate bias network is connected to the gate of the second transistor, the second-stage feedback network is connected in parallel between the inter-stage matching network and the output matching network, and the output matching network is connected to the drain of the second transistor.

8. The ultra-wideband high linearity low noise amplifier circuit based on common-source structure according to claim 7, characterized in that, The output matching network includes microstrip lines TL21, TL22, and TL20, capacitor C19, and an output broadband matching circuit. Microstrip lines TL21, TL22, and capacitor C19 are connected in series. Microstrip line TL21 is connected to the drain of the second transistor, and capacitor C19 is connected to the RF output terminal. The output broadband matching circuit is connected in parallel between microstrip line TL22 and capacitor C19. The second-stage feedback network is connected in parallel between microstrip lines TL21 and TL22. An inductor L7 is provided between the common drain power supply matching network and the output matching network. One end of inductor L7 is connected in parallel between microstrip lines TL21 and TL22, and the other end is connected to the common drain power supply matching network.

9. The ultra-wideband high linearity low noise amplifier circuit based on common-source structure according to claim 2, wherein, The output broadband matching circuit includes an inductor L8 and a capacitor C20 connected in series. One end of the inductor L8 is connected in parallel between the capacitor C19 and the microstrip line TL22, and the other end is connected in series with the capacitor C20 and then grounded.

10. The ultra-wideband, high-linearity, low-noise amplifier circuit based on a common-source structure according to claim 9, characterized in that, Microstrip lines TL14, TL15, and TL17 are connected between the common drain power supply matching network and the drain of the first transistor. One end of microstrip line TL14 is connected to the drain of the first transistor, and the other end is connected to the interstage matching network. One end of microstrip line TL15 is connected in parallel between microstrip line TL14 and the interstage matching network, and the other end is connected in series with one end of microstrip line TL17. The other end of microstrip line TL17 is connected to the common drain power supply matching network. The first-stage feedback network is connected in parallel between microstrip lines TL15 and TL17.

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