Digital twin data management device

Abstract

The utility model discloses a digital twin data management device, and belongs to the technical field of industrial Internet of Things data management. A multi-protocol conversion chip is compatible with an RS485 interface, an Ethernet interface and an optical fiber interface, a PCIe interface is adopted to realize high-speed data interaction among a processing module, a security module and a storage module, a dual-redundancy circuit is utilized to guarantee verification signal transmission reliability, and hierarchical data management is realized in combination with a hierarchical storage architecture (an SSD cache layer, an RAID6 disk array layer and a distributed node layer). And the data integrity is ensured through a model checking unit (double-precision floating point residual calculation) and a self-checking unit (CRC checking and heartbeat packet detection) of the synchronous checking module. The method has the advantages that the protocol conversion delay is smaller than or equal to 2 microseconds, the encryption throughput of the SM4 algorithm reaches 5 Gbps, RAID6 double-disk fault tolerance and parameter updating batch processing efficiency are improved by two times, the system availability is larger than or equal to 99.999%, and the high-real-time, high-safety and high-reliability digital twin data management requirements in industrial scenes are met.

Description

Technical Field

[0001] This utility model belongs to the field of industrial Internet of Things data management technology, specifically a digital twin data management device. Background Technology

[0002] Digital twin technology is being used more and more widely in the field of industrial IoT, but its data management faces the following technical bottlenecks:

[0003] 1. Insufficient protocol compatibility: Although the existing system supports interfaces such as RS485 and Ethernet, the protocol conversion delay generally exceeds 5μs and there is a lack of Fibre Channel support, resulting in low efficiency of heterogeneous device access.

[0004] 2. Weak secure storage capabilities: Traditional encryption schemes rely on software to implement national cryptographic algorithms, with a throughput of only 1-2Gbps, which cannot meet the real-time data encryption needs of industry, and physical isolation mechanisms are lacking;

[0005] 3. Poor storage architecture reliability: The single-layer storage architecture has insufficient fault tolerance, and the RAID5 reconstruction speed is slow (≤500GB / h), which cannot meet the needs of high-speed caching and persistent storage.

[0006] 4. Low data verification accuracy: Existing verification methods (such as the "Model Verification System" in CN112527876A) use single-precision floating-point calculations, with an error ≥ 1 × 10⁻⁶. -6 Furthermore, it lacks a self-checking mechanism, making it difficult to detect millisecond-level data anomalies.

[0007] As is known to those skilled in the art, the aforementioned deficiencies result in high data packet loss rates (≥0.1%), low security protection levels (IP20), and insufficient storage availability (≤99.9%) in digital twin systems in scenarios such as intelligent manufacturing and smart cities. Therefore, there is an urgent need for a digital twin data management device that integrates high-throughput protocol conversion, hardware-level security encryption, multi-level fault-tolerant storage, and high-precision dynamic verification to meet industrial-grade requirements for real-time performance (latency ≤1ms), security (encryption strength ≥128 bits), and reliability (availability ≥99.999%). Utility Model Content

[0008] The technical problems solved: Existing digital twin systems suffer from low data transmission efficiency, poor protocol compatibility, and insufficient secure storage capabilities.

[0009] Technical solution: A digital twin data management device includes a data interface module, a processing module, a security module, a storage module, and a synchronization verification module. The data interface module is connected to the input of the processing module via a data bus. The output of the processing module is connected to the security module and the storage module via PCIe interfaces. The synchronization verification module is connected to both the processing module and the security module via dual redundant circuits. The data interface module includes an RS485 physical interface, an Ethernet interface, and a Fibre Channel interface, with the three interfaces connected in parallel to a bus converter.

[0010] Beneficial effects: Enables multi-protocol compatibility (RS485 / Ethernet / fiber optic), high-speed data transmission (PCIe interface), secure data storage (separation of security module and storage module), and real-time verification (dual redundancy circuit).

[0011] Working principle: Data is uniformly accessed by the bus converter through a multi-protocol interface. After being cleaned and converted by the processing module, it is forwarded to the security module for encryption or the storage module for persistence. The synchronization verification module ensures data consistency through a dual-channel redundancy design.

[0012] In a better implementation scenario, the technical problems addressed are: improving data processing capabilities and protocol conversion efficiency.

[0013] Technical solution: The internal components include a data cleaning unit, a heterogeneous converter, and a real-time synchronization unit. The input of the data cleaning unit is connected to the differential signal output of the bus converter, and the output of the data cleaning unit is connected to the register input of the heterogeneous converter through the IO pin of the FPGA chip.

[0014] Beneficial effects: FPGA accelerates data cleaning (delay ≤2μs), and heterogeneous converters support dynamic parsing of multiple protocols.

[0015] Working principle: The bus converter outputs a differential signal to the data cleaning unit for filtering. After the FPGA processes the data in parallel, it is pushed to the heterogeneous converter for protocol conversion.

[0016] In optimal implementation scenarios, the technical problems addressed are: optimizing industrial protocol parsing capabilities and data timing consistency.

[0017] Technical solution: The aforementioned solution consists of a protocol parsing subunit, a timestamp calibration subunit, and a format encoding subunit connected in series. The protocol parsing subunit includes a parallel structure of Modbus parsing circuit, OPCUA parsing circuit, and MQTT parsing circuit.

[0018] Beneficial effects: Supports parallel parsing of Modbus / OPCUA / MQTT protocols (throughput ≥ 1Gbps), timestamp alignment accuracy ±1μs.

[0019] Working principle: The protocol parsing subunit processes data from different protocols in parallel, the timestamp calibration subunit unifies timing, and the format encoding subunit standardizes output.

[0020] In a preferred implementation scenario, the technical problem solved is achieving low-latency data synchronization and high-precision clock control.

[0021] Technical solution: The device includes an edge computing node and a 5G communication module. The GPIO port of the edge computing node is connected to the data pin of the 5G communication module through the SPI interface. The edge computing node has a built-in clock calibration circuit with a crystal oscillator frequency of 24MHz±50ppm.

[0022] Beneficial effects: 5G communication latency ≤10ms, clock synchronization error ≤1ppm.

[0023] Working principle: Edge computing nodes interact with 5G modules via the SPI interface, and the clock calibration circuit drives high-precision timing control.

[0024] In a best-case scenario, the technical problem addressed is: strengthening data security and access control.

[0025] Technical solution: The above-mentioned hardware encryption engine consists of a hardware encryption engine and an access control unit. The hardware encryption engine adopts an ASIC chip with the national cryptographic SM4 algorithm and its data throughput is 5Gbps±5%. The access control unit includes a physical isolation relay and a digital certificate verification circuit.

[0026] Beneficial effects: Hardware encryption speed reaches line speed (5Gbps), and physical isolation withstand voltage ≥2500Vrms.

[0027] Working principle: The ASIC chip implements SM4 algorithm encryption, and the physical isolation relay cuts off the illegal access link.

[0028] In a best-case scenario, the technical problem addressed is optimizing storage performance and fault tolerance.

[0029] Technical solution: The aforementioned layered storage architecture includes an SSD cache layer, a disk array layer, and a distributed storage node layer; the SSD cache layer is connected to the processing module through an NVMe protocol interface, the disk array layer adopts a RAID6 redundant structure, and the distributed storage node layer contains 3-5 storage nodes.

[0030] Beneficial effects: NVMe interface read / write speed ≥3.5GB / s, RAID6 supports dual-disk fault tolerance.

[0031] Working principle: Hot data is stored in the SSD high-speed cache layer, and cold data is archived to the RAID6 disk array. Distributed nodes realize data redundancy backup.

[0032] In optimal implementation, the technical problems addressed are: improving data verification accuracy and model iteration efficiency.

[0033] Technical solution: The aforementioned solution includes a model verification unit and an incremental learning unit. The model verification unit consists of a residual calculation circuit and a threshold comparator connected in parallel. The residual calculation circuit has an operation precision of IEEE 754 double-precision floating-point format.

[0034] Beneficial effects: Double-precision floating-point calculation error ≤1×10-15, model verification response time ≤5ms.

[0035] Working principle: The residual calculation circuit and the threshold comparator work in parallel to detect data deviations in real time and trigger alarms.

[0036] In a best-case scenario, the technical issues addressed include supporting large-scale parameter updates and version control.

[0037] Technical solution: The aforementioned solution includes a parameter update queue and a model version controller. The depth of the parameter update queue is 64-256 parameter groups, and the model version controller triggers a verification signal through a version number generation circuit.

[0038] Beneficial effects: Supports batch parameter updates (64-256 groups / times), with version switching time ≤100μs.

[0039] Working principle: The parameter update queue caches parameters that are about to take effect, and the version controller generates a unique version number and triggers the verification process.

[0040] In optimal implementation, the technical problem solved is improving the stability of bus protocol conversion.

[0041] Technical solution: The multi-protocol conversion chip has an input impedance of 120Ω±2%, an output level range of 0-3V, and a signal conversion delay of ≤2μs.

[0042] Beneficial effects: impedance matching error ≤2%, signal conversion fidelity ≥99%.

[0043] Working principle: The multi-protocol conversion chip dynamically adjusts the impedance and level to match the electrical characteristics of different interfaces.

[0044] In the best implementation scenario, the technical problem solved is: enhancing the anti-interference capability of signal transmission.

[0045] Technical solution: The system consists of two independent signal channels, each containing an opto-isolator and a differential amplifier. The opto-isolator has an insulation withstand voltage ≥2500Vrms, and the differential amplifier has an adjustable gain range of 10-100 times.

[0046] Beneficial effects: Inter-channel interference attenuation ≥60dB, gain adjustment accuracy ±1%.

[0047] Working principle: The opto-isolator eliminates common-mode interference, and the differential amplifier adaptively amplifies the effective signal.

[0048] In a better implementation scenario, the technical problems addressed are: suppressing data acquisition noise and standardizing the time base.

[0049] Technical solution: The solution includes a noise filter and a timestamp aligner. The noise filter is a fourth-order Butterworth low-pass filter with a cutoff frequency set at 4 to 6 times the sampling frequency.

[0050] Beneficial effects: Noise suppression ratio ≥40dB, timestamp alignment error ≤1μs.

[0051] Working principle: The Butterworth filter removes high-frequency noise, and the timestamp aligner corrects the data timing.

[0052] In optimal implementation, the technical problem solved is to achieve system self-testing and rapid fault location.

[0053] Technical solution: The additional connection self-test unit includes a CRC check circuit and a heartbeat packet generator. The polynomial generator of the CRC check circuit is 0xEDB88320.

[0054] Beneficial effect: CRC check bit error rate ≤ 1×10 -9 The heart rate detection interval is ≤100ms.

[0055] Working principle: The CRC check circuit verifies data integrity, and the heartbeat packet generator periodically sends status signals. Attached Figure Description

[0056] Figure 1 This is a schematic diagram of the overall structure of the digital twin data management device;

[0057] Figure 2 This is a schematic diagram of the internal structure of the processing module;

[0058] Figure 3 This is a schematic diagram of the heterogeneous converter's structure;

[0059] Figure 4 This is a schematic diagram of the real-time synchronization unit connection;

[0060] Figure 5 This is a schematic diagram of the security module's structural composition;

[0061] Figure 6 This is a schematic diagram of the layered architecture of the storage module;

[0062] Figure 7This is a schematic diagram of the synchronous verification module structure;

[0063] Figure 8 This is a schematic diagram of the incremental learning unit composition;

[0064] Figure 9 This is a schematic diagram of a bus converter structure;

[0065] Figure 10 This is a schematic diagram of a dual-redundant circuit.

[0066] Figure 11 This is a schematic diagram of the data cleaning unit structure;

[0067] Figure 12 This is a schematic diagram of the self-test unit.

[0068] In the diagram: 1. Data interface module; 2. Processing module; 3. Security module; 4. Storage module; 5. Synchronization verification module; 6. Data bus; 7. PCIe interface; 8. Dual redundancy circuit; 11. RS485 physical interface; 12. Ethernet interface; 13. Fibre Channel interface; 14. Bus converter; 21. Data cleaning unit; 22. Heterogeneous converter; 23. Real-time synchronization unit; 24. FPGA chip; 221. Protocol parsing subunit; 222. Timestamp calibration subunit; 223. Format encoding subunit; 2211. Modbus parsing circuit; 2212. OPCUA parsing circuit; 2213. MQTT parsing circuit; 231. Edge computing node; 232. 5G communication module; 2311. GPIO port; 233. SPI interface; 234. Clock calibration circuit; 31. Hardware encryption engine; 2. Access Control Unit; 311. ASIC Chip; 321. Physical Isolation Relay; 322. Digital Certificate Verification Circuit; 41. SSD Cache Layer; 42. Disk Array Layer; 43. Distributed Storage Node Layer; 44. NVMe Protocol Interface; 45. RAID6 Redundancy Structure; 46. Storage Node; 51. Model Verification Unit; 52. Incremental Learning Unit; 511. Residual Calculation Circuit; 512. Threshold Comparator; 521. Parameter Update Queue; 522. Model Version Controller; 523. Version Number Generation Circuit; 53. Self-Test Unit; 531. CRC Verification Circuit; 532. Heartbeat Packet Generator; 82. Independent Signal Channel; 83. Opto-isolator; 84. Differential Amplifier; 141. Multi-Protocol Conversion Chip; 211. Noise Filter; 212. Timestamp Aligner; 213. Fourth-Order Butterworth Low-Pass Filter. Detailed Implementation

[0069] To enable those skilled in the art to better understand the technical solution, the present invention will be described in detail below with reference to the embodiments. The description in this part is only exemplary and explanatory, and should not be used to limit the scope of protection of the present invention in any way.

[0070] Combined with appendix Figure 1-12 The implementation method will be further explained below.

[0071] Example 1: Configuration of Basic Industrial Data Management

[0072] Technical solution:

[0073] Data interface module 1 includes an RS485 physical interface 11, an Ethernet interface 12, and a fiber channel interface 13. These three interfaces are connected in parallel to a multi-protocol conversion chip 141. The multi-protocol conversion chip 141 has an input impedance of 120Ω ± 2%, an output level range of 0V to 3V, and a signal conversion delay of 2μs. Processing module 2 receives differential signals from data interface module 1 via data bus 6. The data cleaning unit 21 inside processing module 2 uses a fourth-order Butterworth low-pass filter 213, with a cutoff frequency set to 5 times the sampling frequency. The output of data cleaning unit 21 is connected to the register input of heterogeneous converter 22 via the IO pin of FPGA chip 24. Heterogeneous converter 22 is sequentially connected to protocol parsing subunit 221, timestamp calibration subunit 222, and format encoding subunit 223. Protocol parsing subunit 221 includes a parallel structure of Modbus parsing circuit 2211, OPCUA parsing circuit 2212, and MQTT parsing circuit 2213. Processing module 2 connects to security module 3 and storage module 4 via PCIe interface 7. Security module 3's hardware encryption engine 31 uses an ASIC chip 311 with the national cryptographic SM4 algorithm, achieving a data throughput of 5Gbps. Access control unit 32 includes a physical isolation relay 321 and a digital certificate verification circuit 322. Storage module 4's SSD cache layer 41 receives data from processing module 2 via NVMe protocol interface 44. Disk array layer 42 employs a RAID6 redundant structure 45, and distributed storage node layer 43 contains four storage nodes 46. Synchronization verification module 5 connects to processing module 2 and security module 3 via dual-redundancy circuit 8. The two independent signal channels 82 of dual-redundancy circuit 8 each include an opto-isolator 83 and a differential amplifier 84. The opto-isolator 83 has an insulation withstand voltage of 2500Vrms, and the differential amplifier 84 has a gain of 50. The model verification unit 51 of the synchronization verification module 5 consists of a residual calculation circuit 511 and a threshold comparator 512 connected in parallel. The residual calculation circuit 511 adopts the IEEE754 double-precision floating-point format. The parameter update queue 521 of the incremental learning unit 52 has a depth of 128 parameter groups. The model version controller 522 triggers the verification signal through the version number generation circuit 523. The CRC verification circuit 531 of the self-test unit 53 uses a polynomial generator of 0xEDB88320. The heartbeat packet generator 532 sends status signals at 100ms intervals.

[0074] Technical effects:

[0075] 1. Supports parallel parsing of Modbus / OPCUA / MQTT protocols, with a protocol conversion latency of ≤2μs;

[0076] 2. The SM4 algorithm achieves encryption speeds of up to 5Gbps, and physical isolation withstands voltages of 2500Vrms;

[0077] 3. Data verification error rate ≤ 1×10 -9 The efficiency of batch processing for model parameter updates is improved by 2 times.

[0078] Example 2: High-Security Data Management Configuration

[0079] Technical solution:

[0080] The fiber optic channel interface 13 of data interface module 1 is the main communication link, and the multi-protocol conversion chip 141 has a fixed output level of 3V. The real-time synchronization unit 23 of processing module 2 includes an edge computing node 231 and a 5G communication module 232. The GPIO port 2311 of the edge computing node 231 is connected to the data pin of the 5G communication module 232 via an SPI interface 233. The crystal oscillator frequency of the built-in clock calibration circuit 234 is 24MHz±50ppm. The physical isolation relay 321 of security module 3 has a switching response time of 1ms, and the digital certificate verification circuit 322 supports 1000 certificate verifications per second. The distributed storage node layer 43 of storage module 4 is expanded to 5 storage nodes 46, and the data reconstruction speed of the RAID6 redundant structure 45 is 1TB / h. In the dual-redundancy circuit 8 of synchronization verification module 5, the gain of the differential amplifier 84 is adjusted to 100 times, and the insulation withstand voltage of the opto-isolator 83 is increased to 3000Vrms. The interval of the heartbeat generator 532 in the self-test unit 53 is shortened to 50ms, and the CRC check circuit 531 adds redundant check bits.

[0081] Technical effects:

[0082] 1.5G communication latency ≤ 5ms, clock synchronization error ≤ 0.5ppm;

[0083] 2. Certificate verification throughput increased to 1000 times / second;

[0084] 3. Data reconstruction speed is improved by 30%, and system fault recovery time is ≤10s.

[0085] Example 3: High-performance data processing configuration

[0086] Technical solution:

[0087] The Ethernet interface 12 of data interface module 1 supports 10Gbps bandwidth, and the signal conversion delay of the multi-protocol conversion chip 141 is compressed to 1.5μs. The FPGA chip 24 of processing module 2 is upgraded to a programmable AI acceleration chip, and the protocol parsing subunit 221 of heterogeneous converter 22 adds a TSN protocol parsing circuit 2214. The SSD cache layer 41 of storage module 4 adopts a PCIe 4.0 interface with NVMe protocol 44, achieving a read / write speed of 7GB / s, and the disk array layer 42 adopts a dual RAID6 redundant structure 45 parallel architecture. The residual calculation circuit 511 of synchronization verification module 5 improves the operation precision to extended double precision format, the parameter update queue 521 is extended to a depth of 256 parameter groups, and the switching time of model version controller 522 is shortened to 10μs. The self-test unit 53 integrates a quantum random number generator 533, and the CRC verification circuit 531 supports dynamic polynomial switching.

[0088] Technical effects:

[0089] 1. Ethernet bandwidth utilization is increased by 80%, and protocol parsing throughput is ≥2Gbps;

[0090] 2. SSD read and write speeds doubled, and RAID6 parallel architecture improved fault tolerance by 50%;

[0091] 3. Model version switching time ≤ 10μs, meeting the requirements of millisecond-level real-time control.

[0092] Technical Feature Coverage Description

[0093] 1. Example 1 fully covers all technical features;

[0094] 2. Example 2 enhances the security module 3, the dual redundant circuit 8 gain, and the self-test unit 53 based on Example 1;

[0095] 3. Example 3 optimizes the FPGA chip 24 upgrade, storage module 4 architecture and parameter update queue 521 depth based on Example 1.

[0096] Industrial applicability

[0097] The above embodiments are applicable to intelligent manufacturing (Embodiment 1), financial data security (Embodiment 2), and autonomous driving simulation (Embodiment 3), respectively. The technical parameters and connection relationships meet the requirements of "clear and complete" in Article 26, Paragraph 3 of the Chinese Patent Law.

[0098] It should be noted that, in this document, the terms "comprising," "including," and any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Specific examples have been used in this document to illustrate the principles and implementation methods of the present invention. These examples are merely for the purpose of helping to understand the method and core ideas of the present invention. The above descriptions are only preferred embodiments of the present invention. It should be pointed out that, due to the limitations of written expression and the objective existence of infinite specific structures, those skilled in the art can make several improvements, modifications, or variations without departing from the principles of the present invention, and can also combine the above technical features in an appropriate manner. These improvements, modifications, variations, or combinations, or the direct application of the concept and technical solution of the present invention to other situations without modification, should all be considered within the scope of protection of the present invention.

Claims

1. A digital twin data management device, characterized in that... include: The system comprises a data interface module (1), a processing module (2), a security module (3), a storage module (4), and a synchronization verification module (5). The data interface module (1) is connected to the input of the processing module (2) via a data bus (6). The output of the processing module (2) is connected to the security module (3) and the storage module (4) via a PCIe interface (7). The synchronization verification module (5) is connected to both the processing module (2) and the security module (3) via a dual redundant circuit (8). The data interface module (1) includes an RS485 physical interface (11), an Ethernet interface (12), and a fiber channel interface (13). The three interfaces are connected in parallel to the bus converter (14).

2. The digital twin data management device according to claim 1, characterized in that: The processing module (2) integrates a data cleaning unit (21), a heterogeneous converter (22), and a real-time synchronization unit (23). The input of the data cleaning unit (21) is connected to the differential signal output of the bus converter (14), and the output of the data cleaning unit (21) is connected to the register input of the heterogeneous converter (22) through the IO pin of the FPGA chip (24).

3. The digital twin data management device according to claim 2, characterized in that: The heterogeneous converter (22) is composed of a protocol parsing subunit (221), a timestamp calibration subunit (222), and a format encoding subunit (223) connected in series. The protocol parsing subunit (221) includes a parallel structure of Modbus parsing circuit (2211), OPCUA parsing circuit (2212), and MQTT parsing circuit (2213).

4. The digital twin data management device according to claim 2, characterized in that: The real-time synchronization unit (23) includes an edge computing node (231) and a 5G communication module (232). The GPIO port (2311) of the edge computing node (231) is connected to the data pin of the 5G communication module (232) through the SPI interface (233). The edge computing node (231) has a built-in clock calibration circuit (234) with a crystal oscillator frequency of 24MHz±50ppm.

5. The digital twin data management device according to claim 1, characterized in that: The security module (3) consists of a hardware encryption engine (31) and an access control unit (32). The hardware encryption engine (31) uses an ASIC chip (311) with the national cryptographic SM4 algorithm, and its data throughput is 5Gbps±5%. The access control unit (32) includes a physical isolation relay (321) and a digital certificate verification circuit (322).

6. The digital twin data management device according to claim 1, characterized in that: The storage module (4) adopts a hierarchical storage architecture, including an SSD cache layer (41), a disk array layer (42), and a distributed storage node layer (43). The SSD cache layer (41) is connected to the processing module (2) through the NVMe protocol interface (44). The disk array layer (42) adopts a RAID6 redundant structure (45). The distributed storage node layer (43) contains 3-5 storage nodes (46).

7. The digital twin data management device according to claim 1, characterized in that: The synchronous verification module (5) includes a model verification unit (51) and an incremental learning unit (52). The model verification unit (51) is composed of a residual calculation circuit (511) and a threshold comparator (512) connected in parallel. The operation precision of the residual calculation circuit (511) is IEEE754 double-precision floating-point format.

8. The digital twin data management device according to claim 7, characterized in that: The incremental learning unit (52) includes a parameter update queue (521) and a model version controller (522). The parameter update queue (521) has a depth of 64-256 parameter groups, and the model version controller (522) triggers a verification signal through a version number generation circuit (523).

9. The digital twin data management device according to claim 1, characterized in that: The bus converter (14) uses a multi-protocol conversion chip (141) with an input impedance of 120Ω±2%, an output level range of 0-3V, and a signal conversion delay of ≤2μs.

10. The digital twin data management device according to claim 1, characterized in that: The dual-redundant circuit (8) consists of two independent signal channels (82), each channel containing an opto-isolator (83) and a differential amplifier (84). The insulation withstand voltage of the opto-isolator (83) is ≥2500Vrms, and the gain of the differential amplifier (84) is adjustable from 10 to 100 times.

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