Capacitor and electronic equipment

Abstract

The utility model relates to a capacitor and electronic equipment. The capacitor comprises a silicon substrate and a plurality of mutually independent silicon capacitors. A plurality of mutually independent silicon capacitors are arranged on the surface of one side of the same silicon substrate in an array mode, each silicon capacitor is provided with a corresponding signal transmission module, and the capacitance values of the silicon capacitors are the same or different. A plurality of silicon capacitors are integrated on a silicon substrate by using a semiconductor process. Based on a semiconductor technology, each silicon capacitor integrated on the same silicon substrate has an independent capacitance value and signal transmission module, and can work independently or be used in cooperation with other units according to needs, so that the requirements of different circuits are met, and the flexibility and the integration level of the circuit are greatly improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a capacitor and an electronic device. Background Technology

[0002] As an indispensable basic component in electronic circuits, capacitors are widely used in various fields such as filtering, energy storage, coupling, decoupling, and signal processing. They play a particularly crucial role in high-speed signal processing, power management, and radio frequency (RF) circuits.

[0003] As electronic devices continue to evolve towards higher performance and miniaturization, the requirements for capacitors are also increasing. For example, in power amplifier (PA) modules, multiple capacitors are typically required, with capacitance values ​​ranging from a few picofarads (pF) to tens of picofarads (pF). These capacitors not only need to have high reliability and stability, but also must be placed as close as possible to the component ports to reduce parasitic inductance or capacitance on the signal path, thereby improving the performance of the entire circuit system.

[0004] Currently, the widely used multilayer ceramic capacitors (MLCCs) often occupy a lot of circuit board space when multiple capacitors need to be equipped at the same time, making it difficult to achieve high-density arrangement in the limited board space. Utility Model Content

[0005] This application provides a capacitor and an electronic device, which aims to solve the problems of capacitors occupying a large space and being difficult to arrange in a high density.

[0006] To achieve the above objectives, according to a first aspect of this application, a capacitor is provided, comprising:

[0007] silicon substrate;

[0008] Several independent silicon capacitors are arranged in an array on one side surface of the same silicon substrate. Each silicon capacitor has a corresponding signal transmission module, and the capacitance values ​​of each silicon capacitor may be the same or different.

[0009] Optionally, the silicon capacitor includes:

[0010] A reused bottom electrode is located on one side surface of the silicon substrate;

[0011] Multiple independent capacitor modules are arranged in an array on the surface of the same multiplexed bottom electrode facing away from the silicon substrate;

[0012] A signal transmission module, located on one side surface of the multiplexed bottom electrode, is used to output the electrical signal of the multiplexed bottom electrode;

[0013] The connection module is located between two adjacent capacitor modules and electrically connects the two adjacent capacitor modules.

[0014] Each of the capacitor modules includes an independent top electrode, and the top electrode of any capacitor module is used to output the top electrode signal of the silicon capacitor. The multiplexed bottom electrodes of each silicon capacitor are independent of each other.

[0015] Optionally, the capacitor module includes:

[0016] The first dielectric layer is located between the multiplexed bottom electrode and the top electrode. The first dielectric layers of each capacitor module are independent of each other, and the capacitance value of the capacitor module is related to the thickness of the first dielectric layer.

[0017] Optionally, the signal transmission module includes:

[0018] The second dielectric layer is located on the side surface of the multiplexed bottom electrode facing away from the silicon substrate, and the second dielectric layer has a conductive hole that passes through itself.

[0019] A signal transmission layer covers the side surface of the second dielectric layer opposite to the multiplexed bottom electrode and fills the conductive hole.

[0020] Optionally, the connection module includes:

[0021] A support layer is located on the side surface of the multiplexed bottom electrode that is away from the silicon substrate;

[0022] An electrical connection layer is located on the side surface of the support layer opposite to the multiplexed bottom electrode and is connected to the top electrodes of two adjacent capacitor modules.

[0023] The projected area of ​​the connection module on the silicon substrate is smaller than the projected area of ​​the capacitor module on the silicon substrate.

[0024] Optionally, the electrical connection layer and the top electrode of the capacitor module are integrally formed.

[0025] Optionally, the silicon capacitor includes:

[0026] The electrode structure is spaced apart along a direction perpendicular to the surface of the silicon substrate;

[0027] Dielectric structure, located between two adjacent electrode structures;

[0028] The signal transmission module includes a first transmission unit and a second transmission unit;

[0029] In this configuration, along a direction perpendicular to the surface of the silicon substrate, two adjacent electrode structures and a dielectric structure located between them together constitute a capacitor unit. One of the two adjacent electrode structures is the bottom electrode, and the other is the top electrode. The first transmission unit is electrically connected to the bottom electrode, and the second transmission unit is electrically connected to the top electrode.

[0030] Optionally, both the first transmission unit and the second transmission unit include:

[0031] Electrical connection structures are spaced apart along a direction perpendicular to the surface of the silicon substrate and are connected one-to-one with the electrode structures to be connected. The electrical connection structures located in the same transmission unit are electrically connected to each other.

[0032] A support structure is located between two adjacent electrical connection structures, and / or between the electrical connection structure and the silicon substrate;

[0033] The signal transmission structure is located on the electrical connection structure away from the silicon substrate;

[0034] The transmission unit is capable of outputting electrical signals to the electrode structure connected to the transmission unit.

[0035] Optionally, the silicon substrate has multiple heat dissipation holes on the side opposite to the silicon capacitor.

[0036] According to a second aspect of this application, an electronic device is provided, comprising any of the capacitors disclosed above.

[0037] In the capacitors of this application embodiment, multiple silicon capacitors are integrated on a silicon substrate using semiconductor technology. Based on semiconductor technology, each silicon capacitor integrated on the same silicon substrate has an independent capacitance value and signal transmission module, which can work independently or be used in conjunction with other units as needed to meet the requirements of different circuits, greatly improving the flexibility and integration of the circuit.

[0038] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0041] Figure 1 This is a schematic diagram of the overall structure of the capacitor provided in the embodiments of this application;

[0042] Figure 2 This is a top view of a capacitor provided in an embodiment of this disclosure;

[0043] Figure 3 yes Figure 2 Sectional view at point AA;

[0044] Figure 4 This is a schematic diagram of the structure of a capacitor provided in another embodiment of this disclosure.

[0045] Explanation of reference numerals in the attached figures:

[0046] 1. Silicon substrate; 11. Heat dissipation holes;

[0047] 2. Silicon capacitors;

[0048] 21. Signal transmission module; 211. Second dielectric layer; 212. Signal transmission layer; 213. First transmission unit; 214. Second transmission unit; 2131. Support structure; 2132. Electrical connection structure; 2133. Signal transmission structure;

[0049] 22. Reusable bottom electrode; 23. Capacitor module; 231. Top electrode; 232. First dielectric layer; 24. Connection module; 241. Support layer; 242. Electrical connection layer;

[0050] 25. Electrode structure; 26. Dielectric structure. Detailed Implementation

[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0052] This application provides a capacitor, with reference to... Figures 1 to 3 The capacitor includes a silicon substrate 1 and several independent silicon capacitors 2. The several independent silicon capacitors 2 are arranged in an array on one side surface of the same silicon substrate 1, and each silicon capacitor 2 has a corresponding signal transmission module 21. The capacitance values ​​of each silicon capacitor 2 may be the same or different.

[0053] This application utilizes semiconductor technology to integrate multiple silicon capacitors 2 on a silicon substrate 1. Based on semiconductor technology, each silicon capacitor 2 integrated on the same silicon substrate 1 has an independent capacitance value and signal transmission module 21, which can work independently or be used in conjunction with other units as needed to meet the requirements of different circuits, greatly improving the flexibility and integration of the circuit.

[0054] The embodiment disclosed in this application is as follows: Figure 2 and Figure 3 As shown, in Embodiment 1, each silicon capacitor 2 includes: a multiplexed bottom electrode 22, multiple independent capacitor modules 23, a signal transmission module 21, and a connection module 24. The multiplexed bottom electrode 22 is located on one side surface of the silicon substrate 1. The multiple independent capacitor modules 23 are arranged in an array on the side surface of the same multiplexed bottom electrode 22 facing away from the silicon substrate 1. The signal transmission module 21 and the capacitor modules 23 are located on the same multiplexed bottom electrode 22 and are used to output electrical signals from the multiplexed bottom electrode 22. The connection module 24 is located between two adjacent capacitor modules 23 to electrically connect the two adjacent capacitor modules 23.

[0055] In Embodiment 1, each capacitor module 23 includes an independent top electrode 231 and a first dielectric layer 232. The first dielectric layer 232 is located between the multiplexed bottom electrode 22 and the top electrode 231. The first dielectric layer 232 and the top electrode 231 of each capacitor module 23 are independent of each other. The multiplexed bottom electrodes 22 of each silicon capacitor 2 are independent of each other. Since each capacitor module 23 in the same silicon capacitor 2 is located on the same multiplexed bottom electrode 22, the signal of the multiplexed bottom electrode 22 can be output through the same signal transmission module 21. Because each capacitor module 23 in the same silicon capacitor 2 is connected in parallel through the connection module 24, the top electrode 231 of any capacitor module 23 can be used to output the signal of the top electrode 231 of the silicon capacitor 2.

[0056] In Embodiment 1, the signal transmission module 21 includes a second dielectric layer 211 and a signal transmission layer 212. The second dielectric layer 211 is located on the side of the multiplexed bottom electrode 22 facing away from the silicon substrate 1, and has a conductive hole extending through it. The signal transmission layer 212 covers the side of the second dielectric layer 211 facing away from the multiplexed bottom electrode 22 and fills the conductive hole. With this configuration, the electrical signal of the multiplexed bottom electrode 22 can be output through the signal transmission layer 212.

[0057] In Embodiment 1, the connection module 24 includes a support layer 241 and an electrical connection layer 242. The support layer 241 is located on the side surface of the multiplexed bottom electrode 22 facing away from the silicon substrate 1. The electrical connection layer 242 is located on the side surface of the support layer 241 facing away from the multiplexed bottom electrode 22 and is connected to the top electrodes 231 of two adjacent capacitor modules 23. The projected area of ​​the connection module 24 on the silicon substrate 1 is smaller than the projected area of ​​the capacitor modules 23 on the silicon substrate 1. Specifically, the support layer 241 is an insulating material used to support the electrical connection layer 242 and prevent the electrical connection layer 242 from contacting the multiplexed bottom electrode 22, thereby preventing a short circuit between the top electrode 231 and the multiplexed bottom electrode 22.

[0058] In Embodiment 1, the first dielectric layer 232, the second dielectric layer 211, and the support layer 241 are located on the same layer, and their materials can be the same or different. The materials of the first dielectric layer 232, the second dielectric layer 211, and the support layer 241 can be SiO2, Si3N4, or other materials with high dielectric constants. The first dielectric layer 232, the second dielectric layer 211, and the support layer 241 can be formed by processes such as thermal oxidation, low-pressure chemical vapor deposition, or plasma-enhanced chemical vapor deposition. Specifically, in Embodiment 1, the first dielectric layer 232, the second dielectric layer 211, and the support layer 241 can be formed in the same step by any of the above processes and separated by an etching process; alternatively, they can be formed separately by different processes and steps, and are separated from each other. The first dielectric layer 232, the second dielectric layer 211, and the support layer 241 are fabricated using semiconductor processes. This allows for precise control of the spacing between the first dielectric layer 232, the second dielectric layer 211, and the support layer 241 within the same silicon capacitor 2, thereby improving the capacitor's integration density. Conductive vias on the second dielectric layer 211 can be formed simultaneously during the etching of the second dielectric layer 211. It is worth noting that the first dielectric layer 232, the second dielectric layer 211, and the support layer 241 located in different silicon capacitors 2 can also be formed in the same step and separated from each other through etching processes.

[0059] In Embodiment 1, the top electrode 231, signal transmission layer 212, and electrical connection layer 242 are located on the same layer and are made of the same material. The materials of the top electrode 231, signal transmission layer 212, and electrical connection layer 242 can be metals such as AlCu, Mo, Ti, and Au. Specifically, in Embodiment 1, the top electrode 231, signal transmission layer 212, and electrical connection layer 242 can be formed by a deposition process and simultaneously etched using a single photomask. During deposition, the backfilling of the conductive vias by the signal transmission layer 212 is completed simultaneously. It is worth mentioning that the top electrode 231, signal transmission layer 212, and electrical connection layer 242 located in different silicon capacitors 2 can also be formed in the same step and simultaneously etched using a single photomask.

[0060] In some other embodiments, a transition metal layer is provided between the top electrode 231 and the first dielectric layer 232, and between the first dielectric layer 232 and the multiplexed bottom electrode 22. The transition metal layer can be used to improve the adhesion between the two layers, and the material of the transition metal layer can be metals such as Ti, Ni, and Cr.

[0061] In Example 1, the reused bottom electrode 22 can be formed by diffusing 15%-25% concentration of n-type or p-type ions on the silicon substrate 1 to form a diffusion layer with a thickness of 10nm-100nm, followed by heat treatment. Alternatively, it can be formed by depositing metal on the silicon substrate 1, such as AlCu, Mo, Ti, Au, or other metallic materials.

[0062] In Embodiment 1, the number of capacitor modules 23 in different silicon capacitors 2 is not limited. The capacitance value of the silicon capacitor 2 is related to the number of capacitors it contains; the more capacitors, the larger the capacitance value. The capacitance value of the silicon capacitor 2 is also related to the material and thickness of the first dielectric layer 232. Materials with higher dielectric constants can provide higher capacitance values, while thicker first dielectric layers 232 will reduce capacitance values. The capacitance value of the silicon capacitor 2 is also related to the area of ​​the projection of the top electrode 231 onto the multiplexed bottom electrode 22; the larger the projected area, the larger the capacitance value.

[0063] In Embodiment 1, the projected area of ​​the connection module 24 on the silicon substrate 1 is smaller than the projected area of ​​the capacitor module 23 on the silicon substrate 1. When the capacitance value in the same silicon capacitor 2 needs to be corrected, the connection between the electrical connection layer 242 of any connection module 24 and the top electrode 231 of the capacitor module 23 can be severed by laser correction. The capacitor module 23 can be polygonal, circular, or other shapes.

[0064] The capacitor disclosed in Embodiment 1, by setting a reused bottom electrode 22, allows multiple capacitor modules 23 to share the same bottom electrode, thereby reducing the space occupied by individual electrodes and improving the circuit integration. Multiple capacitor modules 23 are connected in parallel via connection modules 24, allowing users to flexibly adjust the total capacitance of the silicon capacitor 2 according to their needs. Furthermore, the capacitor disclosed in Embodiment 1 can precisely adjust the capacitance of the silicon capacitor 2 by laser-cutting certain connection modules 24, adapting to different application requirements and improving product adjustability and applicability.

[0065] Embodiment two disclosed in this application is as follows: Figure 4 As shown, the structure of the silicon capacitor 2 in Embodiment 2 differs from that in Embodiment 1. Specifically, in Embodiment 2, the silicon capacitor 2 includes electrode structures 25 and dielectric structures 26. The electrode structures 25 are spaced apart along a direction perpendicular to the surface of the silicon substrate 1. The dielectric structures 26 are located between two adjacent electrode structures 25. Along the direction perpendicular to the surface of the silicon substrate 1, two adjacent electrode structures 25 and the dielectric structures 26 located between them together constitute a capacitor unit, and one of the two adjacent electrode structures 25 is the bottom electrode and the other is the top electrode.

[0066] In some embodiments, the number of electrode structures 25 in different silicon capacitors 2 varies, and the capacitance value of the silicon capacitor 2 is related to the number of capacitor cells; the more capacitor cells, the larger the capacitance value. The capacitance value of the silicon capacitor 2 is also related to the overlap area of ​​two adjacent electrode structures 25; the larger the overlap area, the larger the capacitance value. The capacitance value of the silicon capacitor 2 is also related to the thickness of the dielectric structure 26; the smaller the thickness of the dielectric structure 26, the larger the capacitance value.

[0067] The structure of the signal transmission module 21 in Embodiment 2 differs from that in Embodiment 1. In Embodiment 2, the signal transmission module 21 includes a first transmission unit 213 and a second transmission unit 214. The first transmission unit 213 is electrically connected to the bottom electrode, and the second transmission unit 214 is electrically connected to the top electrode.

[0068] Both the first transmission unit 213 and the second transmission unit 214 include: an electrical connection structure 2132, a support structure 2131, and a signal transmission structure 2133. The electrical connection structures 2132 are spaced apart along a direction perpendicular to the surface of the silicon substrate 1, and are connected one-to-one with the electrode structures 25 to be connected. Electrical connection structures 2132 within the same transmission unit are electrically connected to each other. The support structure 2131 is located between two adjacent electrical connection structures 2132, and / or between the electrical connection structure 2132 and the silicon substrate 1. The signal transmission structure 2133 is located on the electrical connection structure 2132 located away from the silicon substrate 1. Each transmission unit can output electrical signals from the electrode structures 25 connected to it; that is, the first transmission unit 213 can output electrical signals from each bottom electrode, and the second transmission unit 214 can output electrical signals from each top electrode.

[0069] In Embodiment 2, the silicon capacitor 2 includes a four-layer electrode structure 25, with a dielectric structure 26 between adjacent electrode structures 25. The dielectric structure 26 has three layers. The electrode structure 25 connected to the silicon substrate 1 is the first electrode structure 25 and serves as the bottom electrode. The second and fourth electrode structures 25 are the top electrodes, and the third electrode structure 25 is also the bottom electrode. The first transmission unit 213 has two electrical connection structures 2132, one connected to the first electrode structure 25 and the other connected to the third electrode structure 25. A support structure 2131 is located between the two electrical connection structures 2132. A signal transmission structure 2133 covers the electrical connection structure 2132 connected to the third electrode structure 25. Simultaneously, the side of the electrical connection structure 2132 connected to the first electrode structure 25 facing away from the silicon substrate 1 is exposed and also connected to the signal transmission structure 2133. The second transmission unit 214 has two electrical connection structures 2132, one connected to the second electrode structure 25 and the other connected to the fourth electrode structure 25. A support structure 2131 is provided between the two electrical connection structures 2132, and a support structure 2131 is also provided between the electrical connection structure 2132 connected to the second electrode structure 25 and the silicon substrate 1. A signal transmission structure 2133 is covered on the electrical connection structure 2132 connected to the fourth electrode structure 25, and the side surface of the electrical connection structure 2132 connected to the second electrode structure 25 facing away from the silicon substrate 1 is exposed and is also connected to the signal transmission structure 2133.

[0070] Furthermore, in Embodiment 2, the electrical connection structure 2132 of each transmission unit and the connected electrode structure 25 are on the same layer and made of the same material. The electrical connection structure 2132 and the electrode structure 25 on the same layer can be formed by a deposition process and simultaneously etched on the same photomask. The support structure 2131 can be composed of the material used to form the electrode structure 25 and the material used to form the dielectric structure 26. For example, the support structure 2131 in the first transmission unit 213 is formed by the dielectric material and electrode material deposited between the first layer electrode structure 25 and the third layer electrode structure 25. At the same time, the side of the support structure 2131 facing the signal transmission structure 2133 is formed of dielectric material to avoid short circuit between the top electrode and the bottom electrode of the capacitor unit.

[0071] Embodiment 2 employs a vertically stacked structure, arranging multiple capacitor units vertically. Adjacent capacitor units share a top or bottom electrode, shortening the connection path between parallel capacitor units and reducing signal interference and loss during transmission. A dielectric layer is inserted between different electrode structures 25, reducing parasitic capacitance and crosstalk between electrode structures 25 and optimizing capacitor performance. Furthermore, arranging multiple capacitor units vertically in Embodiment 2 allows for the integration of more capacitors on the same silicon substrate 1 area, increasing the capacitance per unit area and improving the capacitor integration density.

[0072] In some embodiments, the number of electrode structures 25 in the silicon capacitor 2 of the same capacitor may be the same or different.

[0073] In Embodiments 1 and 2, to improve the heat dissipation performance of the capacitor, multiple heat dissipation holes 11 can be formed on the side of the silicon substrate 1 away from the silicon capacitor 2. When the capacitor is used in a high-frequency, high-power-density operating environment, it will generate a lot of heat. If the heat dissipation is insufficient, the internal temperature of the capacitor may rise, which may cause the dielectric constant to drift and the insulation performance to decrease. Forming multiple heat dissipation holes 11 on the silicon substrate 1 can improve the heat dissipation performance of the capacitor and thus improve its reliability.

[0074] This application also discloses an electronic device including any of the capacitors disclosed above.

[0075] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0076] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0077] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0078] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A capacitor, characterized in that, include: Silicon substrate (1); Several independent silicon capacitors (2) are arranged in an array on one side surface of the same silicon substrate (1). Each silicon capacitor (2) has a corresponding signal transmission module (21). The capacitance values ​​of each silicon capacitor (2) may be the same or different.

2. The capacitor according to claim 1, characterized in that, The silicon capacitor (2) includes: A reused bottom electrode (22) is located on one side surface of the silicon substrate (1); Multiple independent capacitor modules (23) are arranged in an array on the surface of the same multiplexed bottom electrode (22) facing away from the silicon substrate (1); The signal transmission module (21) is located on one side surface of the multiplexed bottom electrode (22) and is used to output the electrical signal of the multiplexed bottom electrode (22); The connecting module (24) is located between two adjacent capacitor modules (23) and electrically connects the two adjacent capacitor modules (23); Each of the capacitor modules (23) includes an independent top electrode (231). The top electrode (231) of any capacitor module (23) is used to output the signal of the top electrode (231) of the silicon capacitor (2). The multiplexed bottom electrodes (22) of each silicon capacitor (2) are independent of each other.

3. The capacitor according to claim 2, characterized in that, The capacitor module (23) includes: The first dielectric layer (232) is located between the multiplexed bottom electrode (22) and the top electrode (231). The first dielectric layer (232) of each capacitor module (23) is independent of each other, and the capacitance value of the capacitor module (23) is related to the thickness of the first dielectric layer (232).

4. The capacitor according to claim 2, characterized in that, The signal transmission module (21) includes: The second dielectric layer (211) is located on the side surface of the multiplexed bottom electrode (22) facing away from the silicon substrate (1), and the second dielectric layer (211) has a conductive hole through itself; A signal transmission layer (212) covers the side surface of the second dielectric layer (211) away from the multiplexed bottom electrode (22) and fills the conductive hole.

5. The capacitor according to claim 2, characterized in that, The connection module (24) includes: A support layer (241) is located on the side surface of the multiplexed bottom electrode (22) facing away from the silicon substrate (1); An electrical connection layer (242) is located on the side surface of the support layer (241) opposite to the multiplex bottom electrode (22) and is connected to the top electrode (231) of two adjacent capacitor modules (23). The projection area of ​​the connection module (24) on the silicon substrate (1) is smaller than the projection area of ​​the capacitor module (23) on the silicon substrate (1).

6. The capacitor according to claim 5, characterized in that, The electrical connection layer (242) and the top electrode (231) of the capacitor module (23) are integrally formed.

7. The capacitor according to claim 1, characterized in that, The silicon capacitor (2) includes: Electrode structures (25) are spaced apart along a direction perpendicular to the surface of the silicon substrate (1); The dielectric structure (26) is located between two adjacent electrode structures (25); The signal transmission module (21) includes a first transmission unit (213) and a second transmission unit (214); In this configuration, along a direction perpendicular to the surface of the silicon substrate (1), two adjacent electrode structures (25) and a dielectric structure (26) located between them together constitute a capacitor unit. One of the two adjacent electrode structures (25) is the bottom electrode, and the other is the top electrode. The first transmission unit (213) is electrically connected to the bottom electrode, and the second transmission unit (214) is electrically connected to the top electrode.

8. The capacitor according to claim 7, characterized in that, Both the first transmission unit (213) and the second transmission unit (214) include: Electrical connection structures (2132) are spaced apart along a direction perpendicular to the surface of the silicon substrate (1) and are connected one-to-one with the electrode structures (25) to be connected. Electrical connection structures (2132) located in the same transmission unit are electrically connected to each other. A support structure (2131) is located between two adjacent electrical connection structures (2132), and / or between the electrical connection structure (2132) and the silicon substrate (1); The signal transmission structure (2133) is located on the electrical connection structure (2132) away from the silicon substrate (1); The transmission unit is capable of outputting electrical signals from the electrode structure (25) connected to the transmission unit.

9. The capacitor according to any one of claims 1-8, characterized in that, The silicon substrate (1) has multiple heat dissipation holes (11) on the side opposite to the silicon capacitor (2).

10. An electronic device, characterized in that, Includes the capacitor as described in any one of claims 1-9.

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