An interface circuit compatible with both PWM speed control and analog speed control

Abstract

This utility model relates to the technical field of interface circuits for brushless electronic fan controllers, and discloses an interface circuit compatible with PWM speed control and analog speed control. The circuit includes a surge protection unit, a first filter unit, a first voltage divider unit, a second voltage divider unit, an integrator circuit, and a second filter unit. The surge protection unit is electrically connected to the input terminal of the first filter unit for inputting a PWM speed control signal. In practical use, when an analog speed control signal is required, the PWM signal, after being protected by the surge protection unit, sequentially passes through the first voltage divider unit, the second voltage divider unit, the integrator circuit, and the second filter unit to become a stable analog speed control signal. This allows a single interface circuit to satisfy the input of both PWM and analog speed control signals, simplifying the interface circuit structure of the drive signal in the brushless electronic controller, reducing costs, and facilitating practical use.

Description

Technical Field

[0001] This utility model relates to the technical field of interface circuits for brushless electronic fan controllers, specifically to an interface circuit compatible with both PWM speed control and analog speed control. Background Technology

[0002] Brushless electric fans are widely used in automobiles, data centers, and smart homes due to their advantages such as high efficiency and energy saving, intelligent control, long lifespan and low maintenance costs, low noise and quiet operation, wide environmental adaptability, reliability and electromagnetic compatibility. The operation control of brushless electric fans is realized by corresponding controllers.

[0003] Existing brushless electronic fan controllers accept PWM signals and analog signals as input drive signals. To enable the input of these two types of drive signals, existing controllers require separate PWM speed control signal interface circuits and analog speed control signal interfaces. This setup leads to complex circuitry, high costs, and inconvenient application. Utility Model Content

[0004] In view of the shortcomings of the prior art, the present invention provides an interface circuit that is compatible with both PWM speed regulation and analog speed regulation.

[0005] To solve the above technical problems, this utility model provides the following technical solution: an interface circuit compatible with PWM speed regulation and analog speed regulation, including a surge protection unit, a first filter unit, a first voltage divider unit, a second voltage divider unit, an integrator circuit, and a second filter unit;

[0006] The surge protection unit is electrically connected to the input terminal of the first filter unit and is used to input a PWM speed control signal; the output terminal of the first filter unit is electrically connected to the input terminal of the first voltage divider unit, one voltage divider node of the first voltage divider unit is electrically connected to the input terminal of the second voltage divider unit, one voltage divider node of the second voltage divider unit is electrically connected to the input terminal of the integrator circuit, the output terminal of the integrator circuit is electrically connected to the input terminal of the second filter unit, and the output terminal of the second filter unit is used to output an analog speed control signal.

[0007] In one embodiment, the surge protection unit includes a TVS diode TVS1, the cathode of the TVS diode TVS1 is the input terminal of the surge protection unit, and the anode of the TVS diode TVS1 is grounded.

[0008] In one embodiment, the first filtering unit includes an inductor L1 and a capacitor C1. One end of the inductor L1 is the input terminal of the first filtering unit, and the other end of the inductor L1 is the output terminal of the first filtering unit, and is grounded through the capacitor C1.

[0009] In one embodiment, the first voltage divider unit includes resistor R1 and resistor R2. One end of resistor R1 is the input terminal of the first voltage divider unit, and the other end of resistor R1 is the voltage divider node of the first voltage divider unit, and is grounded through resistor R2.

[0010] In one embodiment, the resistance of resistor R2 is 2.5 times the resistance of resistor R1.

[0011] In one embodiment, the second voltage divider unit includes resistor R3 and resistor R4. One end of resistor R3 is the input terminal of the second voltage divider unit, and the other end of resistor R3 is the voltage divider node of the second voltage divider unit, and is grounded through resistor R4.

[0012] In one embodiment, the resistance value of resistor R3 is the same as that of resistor R4.

[0013] In one embodiment, the integrating circuit includes a resistor R5 and a capacitor C2. One end of the resistor R5 is the input terminal of the integrating circuit, and the other end of the resistor R5 is the output terminal of the integrating circuit, and is grounded through the capacitor C2.

[0014] In one embodiment, the second filter unit includes a resistor R6 and a capacitor C3. One end of the resistor R6 is the input terminal of the second filter unit, and the other end of the resistor R6 is the output terminal of the second filter unit, and is grounded through the capacitor C3.

[0015] In one embodiment, the output terminal of the first voltage divider unit is also electrically connected to a voltage regulator unit, the voltage regulator unit including a Zener diode Z1, the cathode of the Zener diode Z1 being electrically connected to the output terminal of the first voltage divider unit, and the anode of the Zener diode Z1 being grounded.

[0016] Compared with the prior art, the beneficial effects of this utility model are as follows: In actual use, when a simulated speed control signal is required, the PWM signal is protected by the surge protection unit, and then sequentially passes through the first voltage divider unit, the second voltage divider unit, the integrator circuit, and the second filter unit to become a stable simulated speed control signal. This allows a single interface circuit to meet the input of both PWM speed control signals and simulated speed control signals, making the interface circuit structure of the drive signal in the brushless electronic controller simpler, lower in cost, and more convenient for practical use. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of the present invention as shown in the embodiments. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the present invention, and therefore only show the components relevant to the present invention.

[0019] like Figure 1 As shown, this embodiment provides an interface circuit compatible with PWM speed regulation and analog speed regulation, including a surge protection unit 1, a first filter unit 2, a first voltage divider unit 3, a second voltage divider unit 4, an integrator circuit 5, and a second filter unit 6.

[0020] The surge protection unit 1 is electrically connected to the input terminal of the first filter unit 2 and is used to input the PWM speed control signal; the output terminal of the first filter unit 2 is electrically connected to the input terminal of the first voltage divider unit 3, one voltage divider node of the first voltage divider unit 3 is electrically connected to the input terminal of the second voltage divider unit 4, one voltage divider node of the second voltage divider unit 4 is electrically connected to the input terminal of the integrator circuit 5, the output terminal of the integrator circuit 5 is electrically connected to the input terminal of the second filter unit 6, and the output terminal of the second filter unit 6 is used to output the analog speed control signal.

[0021] In practical use, surge protection unit 1 can improve the effect of external electrical shock and enhance circuit performance. First filter unit 2 can improve the circuit's anti-interference capability. First voltage divider unit 3 and second voltage divider unit 4 can divide the input signal into a readable voltage range. Integrator circuit 5 can convert the PWM signal into an analog signal. Low-pass filtering by second filter unit 6 can make the output analog speed regulation signal more stable.

[0022] In practical use, when a simulated speed control signal is required, the PWM signal is protected by the surge protection unit 1, and then sequentially passes through the first voltage divider unit 3, the second voltage divider unit 4, the integrator circuit 5, and the second filter unit 6 to become a stable simulated speed control signal. This allows a single interface circuit to meet the input of both PWM speed control signals and simulated speed control signals, making the interface circuit structure of the drive signal in the brushless electronic controller simpler, lowering the cost, and facilitating practical use.

[0023] Specifically, in this embodiment, as Figure 1 As shown, the surge protection unit 1 includes a TVS diode TVS1. The cathode of the TVS diode TVS1 is the input terminal of the surge protection unit 1, and the anode of the TVS diode TVS1 is grounded.

[0024] Specifically, in this embodiment, as Figure 1 As shown, the first filter unit 2 is an LC filter circuit, including an inductor L1 and a capacitor C1. One end of the inductor L1 is the input terminal of the first filter unit 2, and the other end of the inductor L1 is the output terminal of the first filter unit 2, and is grounded through the capacitor C1.

[0025] Specifically, in this embodiment, as Figure 1 As shown, the first voltage divider unit 3 includes resistors R1 and R2. One end of resistor R1 is the input terminal of the first voltage divider unit 3, and the other end of resistor R1 is the voltage divider node of the first voltage divider unit 3, and is grounded through resistor R2. Furthermore, the resistance value of resistor R2 is 2.5 times the resistance value of resistor R1. For example, the resistance value of resistor R1 can be 10KΩ, and the resistance value of resistor R2 can be 25KΩ. In some embodiments, the resistance values ​​of resistors R1 and R2 can be adjusted according to the voltage division requirements.

[0026] Specifically, in this embodiment, as Figure 1 As shown, the second voltage divider unit 4 includes resistors R3 and R4. One end of resistor R3 is the input terminal of the second voltage divider unit 4, and the other end of resistor R3 is the voltage dividing node of the second voltage divider unit 4, and is grounded through resistor R4. In this embodiment, the resistance values ​​of resistor R3 and resistor R4 are the same. For example, the resistance value of resistor R3 can be 10KΩ, and the resistance value of resistor R4 can be 25KΩ. In some implementations, the resistance values ​​of resistors R3 and R4 can be adjusted according to the voltage dividing requirements.

[0027] Specifically, in this embodiment, as Figure 1 As shown, the integrator circuit 5 includes a resistor R5 and a capacitor C2. One end of the resistor R5 is the input terminal of the integrator circuit 5, and the other end of the resistor R5 is the output terminal of the integrator circuit 5, and is grounded through the capacitor C2.

[0028] Specifically, in this embodiment, as Figure 1 As shown, the second filter unit 6 is an RC filter unit, including a resistor R6 and a capacitor C3. One end of the resistor R6 is the input terminal of the second filter unit 6, and the other end of the resistor R6 is the output terminal of the second filter unit 6, and is grounded through the capacitor C3.

[0029] In practical use, the resistance value of resistor R6 and the capacitance value of capacitor C3 can be set according to the filtering frequency. For example, the resistance value of resistor R6 can be 5.1K and the capacitance value of capacitor C3 can be 10nF.

[0030] Specifically, in this embodiment, as Figure 1 As shown, in order to ensure the stability of the voltage input to the second voltage divider unit 4, the output terminal of the first voltage divider unit 3 is also electrically connected to a voltage regulator unit 7. The voltage regulator unit 7 includes a Zener diode Z1. The cathode of the Zener diode Z1 is electrically connected to the output terminal of the first voltage divider unit 3, and the anode of the Zener diode Z1 is grounded.

[0031] Based on the above description and inspired by this utility model, those skilled in the art can make various changes and modifications without departing from the technical concept of this utility model. The technical scope of this utility model is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. An interface circuit compatible with PWM speed regulation and analog speed regulation, characterized in that, It includes a surge protection unit, a first filter unit, a first voltage divider unit, a second voltage divider unit, an integrating circuit, and a second filter unit; The surge protection unit is electrically connected to the input terminal of the first filter unit and is used to input a PWM speed control signal; the output terminal of the first filter unit is electrically connected to the input terminal of the first voltage divider unit, one voltage divider node of the first voltage divider unit is electrically connected to the input terminal of the second voltage divider unit, one voltage divider node of the second voltage divider unit is electrically connected to the input terminal of the integrator circuit, the output terminal of the integrator circuit is electrically connected to the input terminal of the second filter unit, and the output terminal of the second filter unit is used to output an analog speed control signal.

2. The interface circuit compatible with PWM speed regulation and analog speed regulation according to claim 1, characterized in that, The surge protection unit includes a TVS diode TVS1, the cathode of which is the input terminal of the surge protection unit, and the anode of which is grounded.

3. The interface circuit compatible with PWM speed regulation and analog speed regulation according to claim 1, characterized in that, The first filtering unit includes an inductor L1 and a capacitor C1. One end of the inductor L1 is the input terminal of the first filtering unit, and the other end of the inductor L1 is the output terminal of the first filtering unit, and is grounded through the capacitor C1.

4. The interface circuit compatible with PWM speed regulation and analog speed regulation according to claim 1, characterized in that, The first voltage divider unit includes resistor R1 and resistor R2. One end of resistor R1 is the input terminal of the first voltage divider unit, and the other end of resistor R1 is the voltage divider node of the first voltage divider unit, and is grounded through resistor R2.

5. The interface circuit compatible with PWM speed regulation and analog speed regulation according to claim 4, characterized in that, The resistance of resistor R2 is 2.5 times that of resistor R1.

6. The interface circuit compatible with PWM speed regulation and analog speed regulation according to claim 1, characterized in that, The second voltage divider unit includes resistor R3 and resistor R4. One end of resistor R3 is the input terminal of the second voltage divider unit, and the other end of resistor R3 is the voltage divider node of the second voltage divider unit, and is grounded through resistor R4.

7. The interface circuit compatible with PWM speed regulation and analog speed regulation according to claim 6, characterized in that, The resistance value of resistor R3 is the same as that of resistor R4.

8. The interface circuit compatible with PWM speed regulation and analog speed regulation according to claim 1, characterized in that, The integrating circuit includes a resistor R5 and a capacitor C2. One end of the resistor R5 is the input terminal of the integrating circuit, and the other end of the resistor R5 is the output terminal of the integrating circuit, and is grounded through the capacitor C2.

9. The interface circuit compatible with PWM speed regulation and analog speed regulation according to claim 1, characterized in that, The second filter unit includes a resistor R6 and a capacitor C3. One end of the resistor R6 is the input terminal of the second filter unit, and the other end of the resistor R6 is the output terminal of the second filter unit, and is grounded through the capacitor C3.

10. The interface circuit compatible with PWM speed regulation and analog speed regulation according to claim 1, characterized in that, The output terminal of the first voltage divider unit is also electrically connected to a voltage regulator unit, which includes a Zener diode Z1. The cathode of the Zener diode Z1 is electrically connected to the output terminal of the first voltage divider unit, and the anode of the Zener diode Z1 is grounded.

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