Goa driving circuit and display device

Abstract

A GOA driving circuit and a display device belong to the technical field of display, and the voltage of a pull-up control node is inverted by an inverter module to output a pull-down control signal to a pull-down control node; a pull-down enhancement module enhances the pull-down control signal according to a pull-down adjustment signal; wherein the voltage of the high level of the enhanced pull-down control signal is raised; a pull-down maintenance module maintains the pull-up control node and the output end of the GOA driving circuit at a low level according to the enhanced pull-down control signal; in the case that the threshold voltage of the transistor in the pull-down maintenance module is long-term opened and forward drift occurs, the enhanced pull-down control signal reduces the possibility of the transistor in the pull-down maintenance module failing to open, thereby reducing the possibility of GOA failure.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a GOA driving circuit and display device. Background Technology

[0002] Integrating a gate driver on array (GOA) circuitry onto a glass substrate creates a scanning drive for the display panel. Compared to traditional gate chip-based driving techniques, GOA technology significantly reduces manufacturing costs and allows for smaller left and right bezels on the display panel. Each GOA driving module outputs a scan signal for each row, driving the pixel units in that row. Multiple GOA driving modules are cascaded to form a GOA driving circuit, enabling line-by-line scanning of the display panel.

[0003] In the relevant GOA driver circuit, the output signal of the inverter module is opposite to that of Qn, and is used as the control signal for the pull-down sustaining circuit. When the threshold voltage of the transistor in the pull-down sustaining module drifts in the positive direction due to long-term on-time, it often leads to the failure of the transistor in the pull-down sustaining module to turn on, which in turn causes the GOA to fail.

[0004] Therefore, the relevant GOA driver circuit has a problem where the transistor in the pull-down sustaining module fails to turn on, causing the GOA to fail. Utility Model Content

[0005] The purpose of this application is to provide a GOA driving circuit and display device, which aims to solve the problem that the GOA fails due to the failure of the transistor to turn on in the pull-down sustaining module in the relevant GOA driving circuit.

[0006] This application provides a GOA driving circuit, including a pull-up module, an input module, a pull-down module, a pull-down sustaining module, an inverter module, and a pull-down enhancement module;

[0007] The input module is connected to the first input signal terminal and the pull-up control node;

[0008] The pull-up module is connected to the clock signal terminal, the pull-up control node, and the output terminal of the GOA driver circuit.

[0009] The inverter module is connected to the pull-up control node and the pull-down control node, and is used to invert the voltage of the pull-up control node to output a pull-down control signal to the pull-down control node.

[0010] The pull-down enhancement module is connected to the pull-down control node and the pull-down enhancement signal terminal, and is used to enhance the pull-down control signal according to the pull-down enhancement signal; wherein, the voltage of the high level of the enhanced pull-down control signal is increased;

[0011] The pull-down sustaining module is connected to the output terminal of the pull-down control node, the pull-up control node, and the GOA drive circuit, and is used to maintain the output terminals of the pull-up control node and the GOA drive circuit at a low level according to the enhanced pull-down control signal.

[0012] The pull-down module is connected to the pull-up control node and the second input signal terminal.

[0013] This utility model embodiment also provides a display device, which includes the above-described GOA driving circuit.

[0014] The beneficial effects of this utility model embodiment compared with the prior art are as follows: Because the voltage of the pull-up control node is inverted by the inverter module to output the pull-down control signal to the pull-down control node; the pull-down enhancement module strengthens the pull-down control signal according to the pull-down enhancement signal; wherein, the high-level voltage of the strengthened pull-down control signal increases; the pull-down sustaining module maintains the output terminals of both the pull-up control node and the GOA drive circuit at a low level according to the adjusted pull-down control signal; when the threshold voltage of the transistor in the pull-down sustaining module is continuously turned on and undergoes positive drift, the strengthened pull-down control signal can reduce the possibility of transistor failure in the pull-down sustaining module, thereby reducing the possibility of GOA failure. Attached Figure Description

[0015] To more clearly illustrate the technical utility model in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic diagram of a GOA driving circuit provided in an embodiment of this application;

[0017] Figure 2 This is a schematic diagram of another structure of the GOA driving circuit provided in one embodiment of this application;

[0018] Figure 3 A waveform diagram of various signals of a GOA driving circuit provided in an embodiment of this application;

[0019] Figure 4 This is a partial example circuit schematic diagram of a GOA driving circuit provided in an embodiment of this application. Detailed Implementation

[0020] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0021] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0022] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0024] Figure 1 A schematic diagram of the GOA driving circuit provided in a preferred embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0025] The aforementioned GOA driving circuit includes a pull-up module 10, an input module 20, a pull-down module 30, a pull-down sustaining module 40, an inverter module 50, and a pull-down enhancement module 60.

[0026] Input module 20 connects the first input signal terminal and the pull-up control node.

[0027] Pull-up module 10 connects to the clock signal terminal, the pull-up control node, and the output terminal of the GOA drive circuit.

[0028] Inverter module 50 connects the pull-up control node and the pull-down control node, and is used to invert the voltage of the pull-up control node to output the pull-down control signal to the pull-down control node.

[0029] The pull-down enhancement module 60 connects the pull-down control node and the pull-down enhancement signal terminal, and is used to enhance the pull-down control signal according to the pull-down enhancement signal; wherein, the voltage of the high level of the enhanced pull-down control signal is increased.

[0030] The pull-down sustaining module 40 is connected to the output terminals of the pull-down control node, the pull-up control node, and the GOA drive circuit. It is used to maintain the output terminals of the pull-up control node and the GOA drive circuit at a low level according to the enhanced pull-down control signal.

[0031] The pull-down module 30 is connected to the pull-up control node and the second input signal terminal.

[0032] In one embodiment, the input module 20 is used to receive a first input signal and transmit the first input signal to the pull-up control node; the pull-up module 10 is used to receive a clock signal and, in response to a high-level clock signal and a high-level pull-up control node signal, outputs a high-level output signal from the output terminal of the GOA driver circuit; the pull-down module 30 is used to receive a second input signal and, in response to a high-level second input signal, pulls the pull-up control node down to a low level.

[0033] The pull-down boost signal is the clock signal of the GOA driver circuit of the previous row; the first input signal is the output signal of the GOA driver circuit of the previous k rows; the second input signal is the output signal of the GOA driver circuit of the next k rows, where k is a positive integer and m is a positive integer less than 2k.

[0034] like Figure 2 As shown, the GOA driving circuit also includes a reset module 70.

[0035] The reset module 70 connects the reset signal terminal and the pull-up control node, and is used to receive the reset signal and pull down the pull-down control node to a low level according to the reset signal.

[0036] It should be noted that the reset signal is located before the output signal Gn-k of the GOA driver circuit in the upper k rows and after the output signal Gn+k of the GOA driver circuit in the lower k rows.

[0037] Setting the RESET signal between the output signal Gn-k of the upper k-row GOA driver circuit and the output signal Gn+k of the lower k-row GOA driver circuit allows the GOA driver circuit to be reset during the scanning interval, thereby releasing excess charge in the GOA driver circuit and enabling the GOA driver circuit to enter a stable operating state, thus improving the stability and reliability of the GOA driver circuit.

[0038] Figure 3 The following is a waveform diagram of the various signals of the GOA driving circuit. Figure 3 right Figure 1 or Figure 2 The principle of the GOA driving circuit shown will be further explained:

[0039] Before stage A, the pull-down enhancement signal CLKm-1 is a square wave, and the reset signal RESET, clock signal CLK, first input signal Gn-k, and second input signal Gn+k are all at low levels. The pull-down module 30 is turned off according to the low-level second input signal Gn+k. The input module 20 transmits the low-level first input signal Gn-k to the pull-up control node Qn. The pull-up control node Qn is at a low level. The inverter module 50 inverts the low-level signal of the pull-up control node Qn and outputs the inverted signal (high level) to the pull-down control node Kn. At the same time, the reset module 70 is turned off according to the low-level reset control signal. The pull-down enhancement module 60 enhances the pull-down control signal according to the pull-down enhancement signal. The pull-down control node Kn switches between high level and ultra-high level, so that the pull-down maintenance module 40 is in the open state. According to the high-level and ultra-high-level signals, the output terminals of the pull-up control node Qn and the GOA drive circuit are maintained at low levels. The output terminal of the GOA drive circuit outputs a low-level output signal Gn. The voltage of the ultra-high level is greater than that of the high level.

[0040] During phase A to B, the first input signal Gn-k is high, while the reset signal RESET, the first clock signal CLK, and the second input signal Gn+k are all low. The pull-down enhancement signal CLKm-1 is a square wave. The pull-down module 3030 is turned off based on the low-level second input signal Gn+k. The input module 2020 transmits the high-level first input signal Gn-k to the pull-up control node Qn. The pull-up control node Qn quickly rises to a high level (first voltage). The inverter module 5050 inverts the high-level signal of the pull-up control node Qn and outputs the inverted signal (low voltage) to the pull-up control node Qn. The output is sent to the pull-down control node Kn. At the same time, the reset module 70 is turned off according to the low-level reset control signal. Since the pull-down enhancement module 60 is only used to increase the voltage of the high-level pull-down control signal after enhancement, the pull-down control node Kn is at a low level, so the pull-down maintenance module 4040 is in the off state. The pull-up module 1010 is connected to the low-level clock signal CLK and responds to the signal of the high-level pull-up control node Qn, and transmits the low-level clock signal CLK to the output terminal of the GOA driver circuit. The output terminal of the GOA driver circuit outputs a low-level output signal Gn.

[0041] During phases B to C, the clock signal CLK is high, while the first input signal Gn-k, the reset signal RESET, and the second input signal Gn+k are all low. The pull-down enhancement signal CLKm-1 is a square wave. The pull-down module 30 is turned off based on the low-level second input signal Gn+k, the input module 20 is turned off based on the low-level first input signal Gn-k, the pull-up control node Qn remains high, the inverter module 5050 inverts the high-level signal of the pull-up control node Qn, and outputs the inverted signal (low level) to the pull-down control node Kn. Simultaneously, the reset module 70 is turned off based on the low-level reset control signal, and the pull-down... Since the reinforcement module 60 is only used to increase the voltage of the enhanced pull-down control signal, the pull-down control node Kn is at a low level, thus the pull-down maintenance module 40 is in a closed state. The pull-up module 1010 is connected to a high-level clock signal CLK, and in response to the high-level pull-up control node Qn, it transmits the high-level clock signal CLK to the output of the GOA driver circuit. It is worth noting that due to the bootstrap effect of the capacitor in the pull-up module 10, the high level maintained by the pull-up control node Qn is a second voltage, wherein the second voltage is greater than the first voltage, and the output of the GOA driver circuit outputs a high-level output signal Gn.

[0042] During stages C to D, the second input signal Gn+k, the reset signal RESET, the clock signal CLK, and the first input signal Gn-k are all at low levels; the pull-down enhancement signal CLKm-1 is a square wave; the pull-down module 30 is turned off according to the low-level second input signal Gn+k, the input module 2020 is turned off according to the low-level first input signal Gn-k, the pull-up control node Qn remains at a high level, the inverter module 5050 inverts the high-level signal of the pull-up control node Qn, and outputs the inverted signal (low level) to the pull-down control node Kn. Simultaneously, the reset module 70, according to the low-level reset control signal... With the signal closed, the pull-down enhancement module 60 is only used to increase the voltage of the enhanced pull-down control signal at a high level, so the pull-down control node Kn is at a low level, thus the pull-down maintenance module 4040 is in a closed state. The pull-up module 10 is connected to a low-level clock signal CLK, and in response to the high-level pull-up control node Qn, it transmits the low-level clock signal CLK to the output of the GOA driver circuit. It is worth noting that since the capacitor in the pull-up module 10 is no longer bootstrapping, the high level maintained by the pull-up control node Qn is the first voltage, and the output of the GOA driver circuit outputs a low-level output signal Gn.

[0043] During stages D to E, the second input signal Gn+k is high, while the reset signal RESET, clock signal CLK, and first input signal Gn-k are all low; the pull-down enhancement signal CLKm-1 is a square wave; input module 20 transmits the low-level first input signal Gn-k to the pull-up control node Qn, pull-down module 30 receives the high-level second input signal Gn+k, and pulls the pull-up control node Qn down to a low level in response to the high-level second input signal Gn+k; inverter module 50 inverts the low-level signal of pull-up control node Qn. The inverted signal (high level) is output to the pull-down control node Kn. At the same time, the reset module 70 is turned off according to the low-level reset control signal, and the pull-down enhancement module 60 enhances the pull-down control signal according to the pull-down enhancement signal. The pull-down control node Kn switches between high level and ultra-high level, so that the pull-down maintenance module 40 is in the open state. According to the high level and ultra-high level signals, the output terminals of the pull-up control node Qn and the GOA drive circuit are both kept at low level. The output terminal of the GOA drive circuit outputs a low-level output signal Gn.

[0044] In stages E to F, the working principle of the GOA drive circuit is the same as in the stages before A, and will not be repeated here.

[0045] During stages F to G, the reset signal RESET is high, while the clock signal CLK, the first input signal Gn-k, and the second input signal Gn+k are low; the pull-down enhancement signal CLKm-1 is a square wave; the pull-down module 30 is turned off based on the low-level second input signal Gn+k, and the input module 20 transmits the low-level first input signal Gn-k to the pull-up control node Qn. The pull-up control node Qn is low, and the inverter module 5050 inverts the low-level signal of the pull-up control node Qn and outputs the inverted signal (high level) to the pull-down control node Kn. Simultaneously, the reset... Module 70 is activated based on a high-level reset control signal. Pull-down enhancement module 60 amplifies the pull-down control signal based on the pull-down enhancement signal. The pull-down control node Kn switches between high and ultra-high levels, thereby keeping the pull-down maintenance module 40 in the activated state. Based on the high-level signal, both the pull-up control node Qn and the output of the GOA drive circuit are kept at a low level. The output of the GOA drive circuit outputs a low-level output signal Gn. The reset module 70 is activated, the pull-up control node Qn is effectively reset, and the output of the GOA drive circuit outputs a low-level output signal Gn.

[0046] Figure 4 The illustration shows a partial example circuit structure of the GOA driving circuit provided in an embodiment of the present invention. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:

[0047] The input module 20 includes a first transistor T1.

[0048] The drain and gate of the first transistor T1 are connected to the first input signal terminal; the source of the first transistor T1 is connected to the pull-up control node Qn.

[0049] The pull-up module 10 includes a second transistor T2 and a bootstrap capacitor C1.

[0050] The gate of the second transistor T2 and the first terminal of the bootstrap capacitor C1 are connected to the pull-up control node Qn; the source of the second transistor T2 and the second terminal of the bootstrap capacitor C1 are connected to the output terminal of the GOA driving circuit; the drain of the second transistor T2 is connected to the clock signal terminal to receive the clock signal CLK.

[0051] The pull-down sustaining module 40 includes a third transistor T3 and a fourth transistor T4.

[0052] The drain of the third transistor T3 is connected to the output of the GOA drive circuit, the drain of the fourth transistor T4 is connected to the pull-up control node Qn, the gates of the third transistor T3 and the fourth transistor T4 are connected to the pull-down control node Kn, and the sources of the third transistor T3 and the fourth transistor T4 are connected to the low voltage source VSS.

[0053] The inverter module 50 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.

[0054] The drain and gate of the fifth transistor T5 and the drain of the seventh transistor T7 are connected to a high voltage source; the gate of the sixth transistor T6 and the gate of the eighth transistor T8 are connected to a pull-up control node Qn; the gate of the sixth transistor T6 and the gate of the eighth transistor T8 are connected to a low voltage source VSS; the source of the fifth transistor T5 is connected to the drain of the sixth transistor T6 and the gate of the seventh transistor T7; the source of the seventh transistor T7 and the drain of the eighth transistor T8 are connected to a pull-down control node Kn.

[0055] The pull-down reinforcement module 60 includes a second capacitor C2;

[0056] The first end of the second capacitor C2 is connected to the pull-down control node Kn; the second end of the second capacitor C2 serves as the pull-down enhancement signal input terminal of the pull-down enhancement module to receive the pull-down enhancement signal CLKm-1.

[0057] The reset module 70 includes a tenth transistor T10 and an eleventh transistor T11;

[0058] The gates of the tenth transistor T10 and the eleventh transistor T11 are connected and together form the reset signal terminal of the reset module 70 to receive the reset signal RESET; the sources of the tenth transistor T10 and the eleventh transistor T11 are connected to a low voltage source; the drain of the tenth transistor T10 is connected to the pull-up control node Qn, and the drain of the eleventh transistor T11 is connected to the output terminal of the GOA drive circuit.

[0059] The pull-down module 30 includes a ninth transistor T9.

[0060] The drain of the ninth transistor T9 is connected to the pull-up control node Qn; the drain of the ninth transistor T9 is connected to the low voltage source VSS; the gate of the ninth transistor T9 is connected to the second input signal terminal to receive the second input signal Gn+k.

[0061] It should be noted that all of the above transistors can be NMOS transistors.

[0062] The following combination Figure 3 right Figure 4 The working principle shown will be further explained as follows:

[0063] Before stage A, the pull-down enhancement signal CLKm-1 is a square wave, and the reset signal RESET, clock signal CLK, first input signal Gn-k, and second input signal Gn+k are all at low levels. The ninth transistor T9 is turned off based on the low-level second input signal Gn+k. The gate of the fifth transistor T5 is connected to the high-level signal output from the high-voltage source VGH, and the drain of the fifth transistor T5 transmits the high-level signal output from the high-voltage source VGH to the source of the fifth transistor T5. The gate of the first transistor T1 is connected to the low-level first input signal Gn-k, and the first transistor T1 is turned off. The pull-up control node Qn is... When the voltage level is low, transistors T6 and T8 are turned off, transistor T7 is turned on, and transistor T7 outputs the high-level signal (pull-down control signal) from the high-voltage source VGH to the pull-down control node Kn. At the same time, capacitor C2 strengthens the pull-down control signal according to the pull-down enhancement signal. The pull-down control node Kn switches between high and ultra-high levels. Transistors T10 and T11 are turned off according to the low-level reset signal RESET, so transistors T3 and T4 are turned on, so that the pull-up control node Qn is connected to the output terminal of the low-voltage source VSS GOA driver circuit to output a low-level output signal Gn.

[0064] During phases A to B, the pull-down enhancement signal CLKm-1 is a square wave; the first input signal Gn-k is high, while the reset signal RESET, the first clock signal CLK, and the second input signal Gn+k are all low; the ninth transistor T9 is turned off according to the low-level second input signal Gn+k; the gate of the fifth transistor T5 is connected to the high-level signal output from the high-voltage source VGH, and the drain of the fifth transistor T5 transmits the high-level signal output from the high-voltage source VGH to the source of the fifth transistor T5; the seventh transistor T7 changes from off to on; the gate of the first transistor T1 is connected to the high-level first input signal Gn-k, and the drain of the first transistor T1 transmits the high-level first input signal Gn-k to the source of the first transistor T1, pulling up... When control node Qn is high (first voltage) and charges bootstrap capacitor C1, the sixth transistor T6 and the eighth transistor T8 turn on, pulling down control node Kn to a low level. Since the second capacitor C2 is only used to increase the voltage of the enhanced high-level pull-down control signal, the pull-down control node Kn is low. At the same time, the tenth transistor T10 and the eleventh transistor T11 turn off according to the low-level reset signal RESET, so the third transistor T3 and the fourth transistor T4 are in the off state. The second transistor T2 turns on according to the high-level pull-up control node Qn signal and transmits the low-level clock signal CLK to the output of the GOA driver circuit. The output of the GOA driver circuit outputs a low-level output signal Gn.

[0065] During stages B to C, the clock signal CLK is high, while the pull-down adjustment signal Gn-m, the first input signal Gn-k, the reset signal RESET, and the second input signal Gn+k are all low. The pull-down enhancement signal CLKm-1 is a square wave. The ninth transistor T9 is turned off based on the low-level second input signal Gn+k. The drain of the fifth transistor T5 transmits the high-level signal output from the high-voltage source VGH to the source of the fifth transistor T5, and the seventh transistor T7 is turned off. The gate of the first transistor T1 is connected to the low-level first input signal Gn-k, and the first transistor T1 is turned off. Since the bootstrap capacitor C1 was charged and stored energy in the previous stage, the pull-up control node Qn is high. Therefore, the sixth transistor T6 and the eighth transistor T8 are turned on to control the pull-down. When node Kn is pulled down to a low level, the second capacitor C2, which is only used to increase the voltage of the enhanced pull-down control signal, keeps the pull-down control node Kn at a low level. At the same time, the tenth transistor T10 and the eleventh transistor T11 are turned off according to the low-level reset signal RESET, thereby turning off the third transistor T3 and the fourth transistor T4. The second transistor T2 is turned on according to the high-level pull-up control node Qn signal and transmits the high-level first clock signal CLK to the output of the GOA driver circuit. Due to the bootstrap effect of the bootstrap capacitor C1, the pull-up control node Qn is raised to the high level of the second voltage, which is greater than the first voltage. The output of the GOA driver circuit outputs a high-level output signal Gn.

[0066] During stages C to D, the clock signal CLK, the first input signal Gn-k, the reset signal RESET, and the second input signal Gn+k are all at low levels; the pull-down enhancement signal CLKm-1 is a square wave; the 28th transistor T28 is turned off according to the low-level second input signal Gn+k; the drain of the fifth transistor T5 transmits the high-level signal output from the high-voltage source VGH to the source of the fifth transistor T5; the ninth transistor T9 is turned off; the seventh transistor T7 is turned on; the gate of the first transistor T1 is connected to the low-level first input signal Gn-k, and the first transistor T1 is turned off. Due to the energy stored in the bootstrap capacitor C1 in the previous stage, the pull-up control node Qn is at a high level, therefore the sixth transistor T6 and the eighth transistor T8... When the pull-down control node Kn is pulled down to a low level, the second capacitor C2, which is only used to increase the voltage of the enhanced high-level pull-down control signal, keeps the pull-down control node Kn at a low level. At the same time, the tenth transistor T10 and the eleventh transistor T11 are turned off according to the low-level reset signal RESET, thereby turning off the third transistor T3 and the fourth transistor T4. The second transistor T2 is turned on according to the high-level pull-up control node Qn signal and transmits the low-level first clock signal CLK to the output of the GOA driver circuit. Since the bootstrap capacitor C1 is no longer bootstrapping at this time, the pull-up control node Qn is at the high level of the first voltage, and the output of the GOA driver circuit outputs a low-level output signal Gn.

[0067] During stages D to E, the second input signal Gn+k is high, while the pull-down adjustment signal Gn-m, reset signal RESET, clock signal CLK, and first input signal Gn-k are all low; the pull-down enhancement signal CLKm-1 is a square wave; the drain of the fifth transistor T5 transmits the high-level signal output from the high-voltage source VGH to the source of the fifth transistor T5, the gate of the first transistor T1 is connected to the low-level first input signal Gn-k, the first transistor T1 is turned off, the ninth transistor T9 is turned on according to the high-level second input signal Gn+k, and pulls the pull-up control node Qn down to a low level, therefore the sixth transistor T... Transistors 6 and 8 are turned off, transistor 7 is turned on, and transistor 7 outputs a high-level signal from the high-voltage source VGH to the pull-down control node Kn. The second capacitor C2 strengthens the pull-down control signal according to the pull-down enhancement signal. The pull-down control node Kn switches between high level and ultra-high level. Transistors 10 and 11 are turned off according to the low-level reset signal RESET, so that transistors 3 and 4 are turned on, so that the pull-up control node Qn is connected to the low-voltage source VSS. The output terminal of the GOA drive circuit outputs a low-level output signal Gn.

[0068] In stages E to F, the working principle of the GOA drive circuit is the same as in the stages before A, and will not be repeated here.

[0069] During stages F to G, the reset signal RESET is high, while the clock signal CLK, the first input signal Gn-k, and the second input signal Gn+k are low; the pull-down enhancement signal CLKm-1 is a square wave; the ninth transistor T9 is turned off according to the low-level second input signal Gn+k; the drain of the fifth transistor T5 transmits the high-level signal output from the high-voltage source VGH to the source of the fifth transistor T5; the gate of the first transistor T1 is connected to the low-level first input signal Gn-k, so the first transistor T1 is turned off; the pull-up control node Qn is low, therefore the sixth transistor T6 and the eighth transistor T8 are turned off, and the seventh transistor T7 is turned on. Furthermore, the seventh transistor T7 outputs the high-level signal from the high-voltage source VGH to the pull-down control node Kn. The second capacitor C2 strengthens the pull-down control signal according to the pull-down enhancement signal. The pull-down control node Kn switches between high level and ultra-high level. The tenth transistor T10 and the eleventh transistor T11 are turned on according to the high-level reset signal RESET, so that the third transistor T3 and the fourth transistor T4 are in the turned-on state, so that the pull-up control node Qn is connected to the low-voltage source VSS. The pull-up control node Qn and the output terminal of the GOA drive circuit are effectively reset, and the output terminal of the GOA drive circuit outputs a low-level output signal Gn.

[0070] It should be noted that in this application, the pull-up module 10 also outputs the same stage transmission signal STn as the output signal Gn. The output signals of each stage of the GOA drive circuit can be replaced with the stage transmission signals of each stage of the GOA drive circuit.

[0071] This utility model embodiment also provides a display device, which includes the above-described GOA driving circuit.

[0072] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0073] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A GOA driving circuit, characterized in that, It includes a pull-up module, an input module, a pull-down module, a pull-down sustain module, an inverter module, and a pull-down enhancement module; The input module is connected to the first input signal terminal and the pull-up control node; The pull-up module is connected to the clock signal terminal, the pull-up control node, and the output terminal of the GOA driver circuit. The inverter module is connected to the pull-up control node and the pull-down control node, and is used to invert the voltage of the pull-up control node to output a pull-down control signal to the pull-down control node. The pull-down enhancement module is connected to the pull-down control node and the pull-down enhancement signal terminal, and is used to enhance the pull-down control signal according to the pull-down enhancement signal; wherein, the voltage of the high level of the enhanced pull-down control signal is increased; The pull-down sustaining module is connected to the output terminal of the pull-down control node, the pull-up control node, and the GOA drive circuit, and is used to maintain the output terminals of the pull-up control node and the GOA drive circuit at a low level according to the enhanced pull-down control signal. The pull-down module is connected to the pull-up control node and the second input signal terminal.

2. The GOA driving circuit as described in claim 1, characterized in that, The input module is used to receive a first input signal and transmit the first input signal to the pull-up control node; The input module includes a first transistor; The drain and gate of the first transistor are connected to the first input signal terminal; The source of the first transistor is connected to the pull-up control node.

3. The GOA driving circuit as described in claim 1, characterized in that, The pull-up module is used to receive a clock signal, and in response to a high-level clock signal and a high-level pull-up control node signal, it outputs a high-level output signal from the output terminal of the GOA driver circuit. The pull-up module includes a second transistor and a bootstrap capacitor; The gate of the second transistor and the first terminal of the bootstrap capacitor are both connected to the pull-up control node; The source of the second transistor and the second terminal of the bootstrap capacitor are both connected to the output terminal of the GOA driving circuit; The drain of the second transistor is connected to the clock signal terminal to receive the clock signal.

4. The GOA driving circuit as described in claim 1, characterized in that, The pull-down sustaining module includes a third transistor and a fourth transistor; The drain of the third transistor is connected to the output terminal of the GOA driving circuit, the drain of the fourth transistor is connected to the pull-up control node, the gates of the third transistor and the fourth transistor are connected to the pull-down control node, and the sources of the third transistor and the fourth transistor are connected to a low voltage source.

5. The GOA driving circuit as described in claim 1, characterized in that, The inverter module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; The drain of the fifth transistor, the gate of the fifth transistor, and the drain of the seventh transistor are all connected to a high voltage source. The gate of the sixth transistor and the gate of the eighth transistor are both connected to the pull-up control node; The gate of the sixth transistor and the gate of the eighth transistor are connected to a low voltage source. The source of the fifth transistor is connected to the drain of the sixth transistor and the gate of the seventh transistor. The source of the seventh transistor and the drain of the eighth transistor are both connected to the pull-down control node.

6. The GOA driving circuit as described in claim 1, characterized in that, The pull-down reinforcement module includes a second capacitor; The first terminal of the second capacitor is connected to the pull-down control node; The second terminal of the second capacitor serves as the input terminal of the pull-down enhancement signal of the pull-down enhancement module, so as to receive the pull-down enhancement signal.

7. The GOA driving circuit as described in claim 1, characterized in that, The pull-down module is used to receive a second input signal, and in response to a high-level second input signal, it pulls the pull-up control node down to a low level; The pull-down module includes a ninth transistor; The drain of the ninth transistor is connected to the pull-up control node; The drain of the ninth transistor is connected to a low-voltage source; The gate of the ninth transistor is connected to the second input signal terminal to receive the second input signal.

8. The GOA driving circuit as described in any one of claims 1 to 7, characterized in that, Also includes: The reset module connects the reset signal terminal and the pull-up control node, and is used to receive the reset signal and pull the pull-up control node down to a low level according to the reset signal.

9. The GOA driving circuit as described in any one of claims 1 to 7, characterized in that, The pull-down enhancement signal is the clock signal of the GOA driver circuit of the upper row 1; the first input signal is the output signal of the GOA driver circuit of the upper k rows; the second input signal is the output signal of the GOA driver circuit of the lower k rows, where k is a positive integer and m is a positive integer less than 2k.

10. A display device, characterized in that, The display device includes the GOA driving circuit as described in any one of claims 1 to 9.

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