A panel level radio frequency packaging system
By using a panel-level RF packaging system, the RF chip and wiring layers are isolated by a dielectric layer, avoiding parasitic capacitance. This solves the problems of space occupation and signal quality in RF chip packaging, and achieves smaller and more efficient signal transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHENGDU SHIDAI SUXIN TECH CO LTD
- Filing Date
- 2025-05-29
- Publication Date
- 2026-06-05
Smart Images
Figure CN224329899U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of chip packaging, and in particular to a panel-level radio frequency packaging system. Background Technology
[0002] With the development of 5G (5th Generation Mobile Communication Technology), IoT, and millimeter-wave technology, communication devices are becoming increasingly multifunctional, significantly increasing the complexity of radio frequency (RF) front-end systems. This necessitates the integration of RF chips with multiple functions, typically achieved through traditional substrate-level assembly. When packaging RF chips, wafer-level packaging is commonly used. The pads (pins) on the RF chip are connected to the package pins on the substrate via gold wire bonding. Pins of different RF chips are then interconnected via transmission lines on the substrate. However, gold wire bonding introduces insertion loss into the RF circuit, affecting the transmission efficiency of the RF signal. Furthermore, due to the arc height of the gold wire, it occupies significant horizontal and vertical space. Additionally, the short distance between the GND (ground) layer of the RF chip and the substrate during wafer-level packaging means that if the transmission line on the substrate is directly below the RF chip, parasitic capacitance will form between the transmission line and the GND layer, resulting in additional capacitive loading on the transmission line. This attenuation of high-frequency components on the transmission line affects the quality of the transmitted signal. Utility Model Content
[0003] The purpose of this invention is to provide a panel-level RF packaging system that encapsulates at least one RF chip using injection molding epoxy resin. Multiple stacked dielectric layers are placed between the RF chip and a first wiring layer containing metal traces to isolate the RF chip and the first wiring layer. This avoids the generation of parasitic capacitance between the metal traces and the RF chip in the vertically downward projection area of the RF chip on the first wiring layer. Since the packaged RF chip contacts the top layer of the dielectric layer via flip-chip packaging, each pin of the RF chip is directly connected to the metal traces of the lower first wiring layer through metal vias in the dielectric layer and connected to the corresponding BGA solder balls. Furthermore, because the metal traces on the first wiring layer are located within the vertically downward projection area of the RF chip, the space occupied in both the horizontal and vertical directions is reduced, thus decreasing the size of the packaging system.
[0004] To address the aforementioned technical problems, this utility model provides a panel-level radio frequency packaging system, comprising:
[0005] At least one radio frequency chip is encapsulated using injection molding epoxy molding compound;
[0006] A multi-layered dielectric substrate is located below each of the radio frequency (RF) chips, with the pin surfaces of the RF chips facing the dielectric substrate and in direct contact with the top layer of the dielectric substrate; each dielectric substrate has a metal via that penetrates the dielectric substrate vertically.
[0007] The first wiring layer is located at the bottom layer of the multilayer dielectric substrate, and its surface is provided with metal traces arranged according to a first preset wiring rule; the metal traces on the first wiring layer are located in the vertically downward orthogonal projection area of the RF chip.
[0008] Multiple BGA solder balls are distributed on the bottom surface of the first rewiring layer according to a preset distribution rule;
[0009] The pins of the RF chip are connected to the metal traces of the first redistribution layer sequentially downwards through the metal vias of each dielectric layer, and are connected to the BGA solder balls through the metal traces.
[0010] Preferably, it further includes:
[0011] The second wiring layer is located above the radio frequency chip, and its surface is provided with metal traces arranged according to the second preset wiring rule;
[0012] At least one copper pillar is distributed around the radio frequency chip;
[0013] The second redistribution layer, the copper pillars, and the RF chip are encapsulated using injection molding epoxy molding compound;
[0014] The metal traces on the second rewiring layer are connected to the metal traces on the first rewiring layer through the metal copper pillars, and are connected to the pins of the RF chip and / or the BGA solder balls through the metal traces on the first rewiring layer.
[0015] Preferably, it further includes:
[0016] Several radio frequency front-end modules are encapsulated using injection molding epoxy molding compound;
[0017] The third wiring layer is located below the RF front-end module, and its surface is provided with metal traces arranged according to a third preset wiring rule; the pin surface of the RF front-end module faces the third wiring layer.
[0018] The third routing layer and the second routing layer are connected via SMT;
[0019] The pins of the RF front-end module are connected to the metal traces on the third wiring layer, and are also connected to the metal traces on the second wiring layer through the metal traces on the third wiring layer.
[0020] Preferably, the radio frequency front-end module includes one or more of the following: a power supply chip, a capacitor, an inductor, and a power amplifier chip.
[0021] Preferably, it further includes:
[0022] Several antenna modules are individually packaged using glass substrates;
[0023] The fourth wiring layer is located below the antenna module, and its surface is provided with metal traces arranged according to the fourth preset wiring rule; the feed surface of the antenna module faces the fourth wiring layer.
[0024] The fourth routing layer and the second routing layer are connected via SMT;
[0025] The feed terminal of the antenna module is connected to the metal trace on the fourth wiring layer, and is also connected to the metal trace on the second wiring layer through the metal trace on the fourth wiring layer.
[0026] Preferably, the position of the metal via on the uppermost dielectric layer corresponds perpendicularly to the position of the pin of the RF chip.
[0027] Preferably, the dielectric layer is made of deposited polyimide or Ajinomoto stacked film ABF.
[0028] Preferably, it further includes:
[0029] The under-bump metallization layer (UBM) is distributed below the first redistribution layer according to the preset distribution rules and is soldered to each of the BGA solder balls.
[0030] Preferably, the BGA solder balls are high-lead solder balls.
[0031] Preferably, the total thickness of each of the dielectric layers is not less than a preset thickness.
[0032] This application provides a panel-level RF packaging system that encapsulates at least one RF chip using injection molding epoxy molding compound. Multiple stacked dielectric layers are spaced between the RF chip and a first wiring layer containing metal traces to isolate the RF chip and the first wiring layer. This avoids the generation of parasitic capacitance between the metal traces and the RF chip in the vertically downward projection area of the RF chip on the first wiring layer. Since the packaged RF chip contacts the top layer of the dielectric layer via flip-chip packaging, each pin of the RF chip is directly connected to the metal traces of the lower first wiring layer through metal vias in the dielectric layer and connected to the corresponding BGA solder balls. Furthermore, because the metal traces on the first wiring layer are located within the vertically downward projection area of the RF chip, the space occupied in both the horizontal and vertical directions is reduced, thus decreasing the size of the packaging system. Attached Figure Description
[0033] To more clearly illustrate the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 A schematic diagram of a panel-level radio frequency packaging system provided by this utility model;
[0035] Figure 2 A schematic diagram of the structure of the second panel-level radio frequency packaging system provided by this utility model;
[0036] Figure 3 A schematic diagram of the third panel-level radio frequency packaging system provided by this utility model;
[0037] Figure 4 A schematic diagram of the routing on a rewiring layer provided by this utility model;
[0038] Figure 5 This is a schematic diagram of a fan-in package wiring provided by this utility model. Detailed Implementation
[0039] The core of this invention is to provide a panel-level RF packaging system. At least one RF chip is packaged using injection molding epoxy resin. Multiple stacked dielectric layers are placed between the RF chip and a first wiring layer containing metal traces to isolate the RF chip and the first wiring layer. This avoids the generation of parasitic capacitance between the metal traces and the RF chip in the vertically downward projection area of the RF chip on the first wiring layer. Since the packaged RF chip contacts the top layer of the dielectric layer via flip-chip packaging, each pin of the RF chip is directly connected to the metal traces of the lower first wiring layer through metal vias in the dielectric layer and connected to the corresponding BGA solder balls. Furthermore, because the metal traces on the first wiring layer are located within the vertically downward projection area of the RF chip, the space occupied in both the horizontal and vertical directions is reduced, thus decreasing the size of the packaging system.
[0040] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0041] Please refer to Figure 1 , Figure 1 A schematic diagram of a panel-level radio frequency packaging system provided by this utility model includes:
[0042] At least one radio frequency chip 1 is encapsulated using injection molding epoxy molding compound;
[0043] The multi-layered dielectric layer 2 is located below each radio frequency chip 1, with the pin surface of the radio frequency chip 1 facing the dielectric layer 2 and in direct contact with the top layer of the dielectric layer 2; each dielectric layer 2 has a metal via, which penetrates the dielectric layer 2 vertically.
[0044] The first wiring layer 3 is located at the bottom layer of the multilayer dielectric substrate 2, and its surface is provided with metal traces arranged according to the first preset wiring rules; the metal traces on the first wiring layer 3 are located in the vertical downward projection area of the RF chip 1.
[0045] Multiple BGA solder balls 4 are distributed on the bottom surface of the first rewiring layer 3 according to a preset distribution rule;
[0046] The pins of the RF chip 1 are connected to the metal traces of the first redistribution layer 3 through the metal vias of each dielectric layer 2, and are connected to the BGA solder balls 4 through the metal traces.
[0047] In existing technologies, the most common method for packaging RF chips 1 is to lay several RF chips 1 flat on a substrate, such as a PCB (Printed Circuit Board). The pins of the RF chips 1 are connected to transmission lines on the substrate via gold wire bonding. The individual RF chips 1 are then interconnected via these transmission lines. The gold wires extend from the pins of the RF chips 1 outwards onto the substrate with a certain arc height. Therefore, this packaging structure requires significantly more space in both the horizontal and vertical directions compared to the RF chips 1. Based on this, existing technologies can also employ fan-out packaging, where the pins of the RF chips 1 directly contact the substrate, and then extend outwards to the corresponding pin positions on the substrate via an RDL (Redistribution Layer). This saves space in the vertical direction, but still requires a significant amount of horizontal space. Therefore, existing technologies can also employ fan-in packaging, which involves fanning the pins directly below the RF chip 1 through the RDL redistribution layer on the substrate. Compared to the thickness of the RF chip 1 and the substrate, the entire packaged system does not occupy additional space in the horizontal and vertical directions. However, the pins of the RF chip 1 are typically GSG (Ground, Signal, Ground) structures, and the RF chip 1 has an internal GND metal layer. The GND metal layer is only 10µm away from the pin layer of the RF chip 1, while the wafer-level packaging medium is typically a wet-film polyimide dielectric layer with a single layer thickness of only 10µm. If the RF chip 1 is a flip-chip package, the transmission lines on the substrate, with a height difference of only about 20µm from the GND metal layer of the RF chip 1, generate very large capacitive parasitics. The RF transmission lines on the substrate cannot achieve 50 ohms routing, and the RF insertion loss is also relatively large, affecting the transmission quality of the RF signal.
[0048] To solve the above-mentioned technical problems, this application can encapsulate one or more radio frequency (RF) chips 1 in the same packaging system. However, each RF chip 1 is encapsulated separately by injection molding epoxy molding compound. Specifically, firstly, wafer thinning and dicing are required, and the diced RF chip 1 is mounted on a temporary glass substrate. Then, EMC (Epoxy Molding Compound) material is injected, and the RF chip 1 is wrapped by the EMC material. After the EMC is cured, the RF chip 1 is debonded to the glass substrate, and the EMC material is thinned to the target thickness. At this time, the lead side of the RF chip 1, that is, the side with the leads, is exposed.
[0049] Based on this, the RF chip 1 with exposed pins can be flipped onto a multilayer dielectric substrate 2, and each dielectric substrate 2 has metal vias (i.e., metallized vias). The pins of the RF chip 1 can be directly connected to the first ground layer 3 through the metal vias on the dielectric substrate 2. Compared to the prior art where the RF chip 1 is placed on the substrate with its pins facing upwards and connected to the substrate by gold wire bonding, where the gold wire needs to fan out in an arc to the area outside the RF chip 1 on the substrate, requiring clearance above and below the gold wire, and consequently requiring clearance above and below the pins of the packaged RF chip 1 to ensure no metal is present in the clearance area, resulting in a package size much larger than the RF chip 1, this application flips the EMC-packaged RF chip 1 onto the dielectric layer, eliminating the need for additional horizontal space outside the RF chip 1 and reducing the package size. It should be noted that the pin side is the side of the RF chip 1 with pins.
[0050] Furthermore, since the metal traces on the first wiring layer 3 are all located within the vertically downward projection area of the RF chip 1, and multiple dielectric layers 2 separate the first wiring layer 3 and the RF chip 1, parasitic capacitance between the metal traces on the first wiring layer 3 and the GND metal layer of the RF chip 1 can be effectively avoided, thereby reducing the capacitance loading on the transmission line and ensuring the accuracy of the transmitted data. When the pins of the RF chip 1 are connected to the first wiring layer 3 through the metal vias of the dielectric layer 2, they can be connected using 50-ohm transmission lines. In addition, the fan-in package of the RF chip 1 ensures that the horizontal area of the RF packaging system is consistent with the surface area of the RF chip 1, reducing the space occupied by the RF packaging system. It should be noted that the metal traces on the first wiring layer 3 are all located within the vertically downward projection area of the RF chip 1; that is, this embodiment is also a fan-in package. If the packaging system includes multiple RF chips 1, the metal traces between the pins of different RF chips 1 can be located at positions corresponding to the areas on the first wiring layer 3 and between the RF chips 1.
[0051] Based on this, compared to fan-out packaging, the RF pins are fanned into the RF chip, making the package size consistent with the RF chip size, thus achieving miniaturization of the package and facilitating integration.
[0052] Furthermore, by distributing multiple BGA solder balls 4 at the bottom of the first wiring layer 3, when the package system is put into use, the pins of the RF chip 1 can be connected to the BGA solder balls 4 through the metal vias of the dielectric layer 2 and the metal traces on the first wiring layer 3, and then connected to the contacts of the target circuit.
[0053] The material of dielectric layer 2 can be a deposited polyimide dielectric layer or ABF (Anisotropic Conductive Layer). When the RF chip 1 is packaged using wafer-level packaging, the thickness of its dielectric layer 2 is only 10µm. Therefore, the layout and wiring are significantly limited when implementing complex pins, making it insufficient to isolate the RF chip 1 from the first secondary wiring layer 3. However, in this application, by using panel-level packaging, the dielectric thickness of the dielectric layer 2 can be increased for dry film PI (Polyimide Film) materials such as ABF and WMF. For example, the thickness of each dielectric layer 2 can be no less than 30µm. If three dielectric layers 2 are stacked, the distance between the RF chip 1 and the first secondary wiring layer 3 is no less than 90µm. The metal vias on the dielectric layer 2 lead the pads of the RF chip 1 to the first secondary wiring layer 3. The RDL layer pattern is photolithographically patterned on the first secondary wiring layer 3 according to the first preset wiring rules, and a copper plating process is used to deposit a 10-20µm thick copper layer on the RDL layer pattern to achieve the arrangement of metal traces on the first secondary wiring layer 3. It should be noted that... The multilayer dielectric substrate 2 may only include metal vias without metal traces, meaning there are no transmission lines on the dielectric substrate 2. If multiple RF chips 1 are packaged in the same packaging system, the RF chips 1 can be interconnected through the metal traces on the first redistribution layer 3. In addition, to further ensure the distance between the RF chip 1 and the first redistribution layer 3, an additional redistribution layer can be set between the two dielectric substrates 2 to ensure that the distance between the first redistribution layer 3 and the surface of the RF chip 1 is at least ≥100um. This greatly reduces the capacitive parasitics between the metal traces connected to the BGA solder balls 4 on the first redistribution layer 3 and the internal ground of the RF chip 1. Of course, a small number of metal traces can also be appropriately set on the redistribution layer between the dielectric substrates 2, such as power supply transmission lines or other DC signal transmission lines, to avoid the parasitic effects of the metal traces on the surface of the RF chip 1 while reducing the trace pressure on the first redistribution layer 3. Finally, a UBM (Underground Bus) can be fabricated under the first redistribution layer 3 through another dielectric substrate 2. Bump Metal (under-bump metallization layer) and BGA balling are then performed. Considering that multiple packaging systems can be packaged simultaneously, a final dicing process is required to make each packaging system an independent single-chip RF packaging system. Compared with existing traditional packaging architectures, such as ceramic packaged wirebond technology, the flip-chip design of RF chip 1 in this application reduces the insertion loss of the bonding wires, and the reduction in insertion loss at high frequencies is up to about 0.5dB, avoiding uncertainties during debugging. The actual test performance is close to the simulation performance. In addition, the routing accuracy in this application can achieve a linewidth of about 30um, which far exceeds the routing accuracy of traditional packages such as ceramic or PCB, and the layout and routing are more flexible.Based on this, the packaging system in this application has a packaging size close to that of the RF chip 1. After RF simulation, it can achieve excellent performance of 0~40GHz RF signal transmission, S11≤-25dB, and insertion loss≤0.3dB. Compared with the traditional gold wire bonding packaging method, it can reduce the insertion loss by about 0.5dB and save more than 25% of the packaging area.
[0054] Furthermore, in wafer-level packaging, the packaging is arranged according to the wafer, while in panel-level packaging, the packaging system structure is rectangular. Based on this, the utilization rate of the packaging system in panel-level packaging is higher, and the utilization rate is over 80%.
[0055] In addition, it should be noted that the radio frequency chip 1 may include, but is not limited to, a low-noise amplifier and an amplitude-phase multifunction chip. The low-noise amplifier is used to amplify each received radio frequency signal, and the amplitude-phase multifunction chip is used to adjust the amplitude and phase of each received radio frequency signal and to perform beamforming.
[0056] In summary, this application not only isolates the RF chip 1 and the first rewiring layer 3 through a multilayer dielectric layer 2 to avoid the generation of parasitic capacitance, but also reduces the horizontal space occupation and the size of the packaging system through vertical downward routing.
[0057] Based on the above embodiments:
[0058] As a preferred embodiment, it also includes:
[0059] The second wiring layer 5 is located above the RF chip 1, and its surface is provided with metal traces arranged according to the second preset wiring rules.
[0060] At least one copper pillar 6 is distributed around the radio frequency chip 1;
[0061] The second wiring layer 5, the copper pillars 6 and the RF chip 1 are encapsulated using injection molding epoxy molding compound.
[0062] The metal traces on the second wiring layer 5 are connected to the metal traces on the first wiring layer 3 via the metal copper pillars 6, and are connected to the pins and / or BGA solder balls 4 of the RF chip 1 via the metal traces on the first wiring layer 3.
[0063] Please refer to Figure 2 , Figure 2This is a schematic diagram of the structure of the second panel-level radio frequency packaging system provided by this utility model. In this embodiment, before packaging only the radio frequency chip 1, a metal layer can be buried above the radio frequency chip 1, that is, a second redistribution layer 5 is placed above the radio frequency chip 1, and at least one metal copper pillar 6 is placed around the radio frequency chip 1. The diameter of the metal copper pillar 6 is about 100~500um. During EMC injection molding, the radio frequency chip 1, the second redistribution layer 5 and the metal copper pillar 6 are injection molded together. On the second wiring layer 5, an RDL pattern can be created according to the second preset routing rules using a developing and etching method, that is, the arrangement of metal traces is drawn. The metal traces on the second wiring layer 5 are connected to the first wiring layer 3 below the RF chip 1 through the metal copper pillars 6, and then connected to the pad of the RF chip 1 through the metal traces on the first wiring layer 3. Therefore, the metal traces on the second wiring layer 5 can also serve as pins for connecting the RF packaging system to external circuits. Thus, the RF packaging system in this embodiment is a panel-level packaging system with double-sided RDL pin distribution. That is, the external circuit can be connected to the RF chip 1 not only through the BGA solder balls 4 on the first wiring layer 3, but also through the metal traces on the second wiring layer 5, improving the flexibility of the RF packaging system application scenarios. The overall size of the RF packaging system in this application is only increased by the diameter of the metal copper pillars 6 compared to the size of the RF chip 1 itself. Since the diameter of the metal copper pillars 6 is small, the volume of the RF packaging system is still small.
[0064] It should be noted that different RF packaging systems can be connected through the first wiring layer 3 and the second wiring layer 5. For example, if the first and second RF packaging systems have the same packaging structure, and you want to connect them so that the RF chip 1 in the first RF packaging system is connected to the RF chip 1 in the second RF packaging system, then the first RF packaging system can be placed on top of the second RF packaging system. This means the BGA solder balls 4 at the bottom of the first wiring layer 3 of the first RF packaging system are connected to the metal traces on the second wiring layer 5 of the second RF packaging system. The RF chip 1 in the first RF packaging system is connected through the first wiring layer 3 and the second wiring layer 5. In one RF packaging system, a metal via on the dielectric layer 2 is connected to a metal trace on the first rewiring layer 3 of the first RF packaging system. The metal trace is then connected to the corresponding BGA solder ball 4 via a metal trace distributed according to a first preset routing rule. The trace is then connected to the second rewiring layer 5 of the second RF packaging system. The metal trace is then connected to the corresponding copper pillar 6 via a metal trace arranged according to a second preset routing rule. The copper pillar 6 is then connected to the metal trace on the first rewiring layer 3 of the second RF packaging system. Finally, the trace is connected to the corresponding pad of the RF chip 1 in the second RF packaging system via a metal via on the dielectric layer 2 of the second RF packaging system, thereby achieving the connection between the RF chips 1 in different RF packaging systems.
[0065] Based on this, compared with the traditional single-layer plastic RF packaging structure, the RF packaging system in this application can use TMV (metal pillar) and metal layers to form a double-sided redistribution layer structure. That is, double-sided pins can be brought out through the lower first redistribution layer and the upper second redistribution layer. The above-mentioned RF packaging system can be surface mounted with various types of RF packaging systems using SMT (Surface Mount Technology) to complete the top and bottom interconnection and form a more complex 2.5D RF heterogeneous integrated microsystem architecture.
[0066] In addition, it should be noted that since the RF chip 1 is a flip-chip package, the distance between the GND metal layer and the bottom layer of the RF chip 1 is relatively large. Therefore, the distance between the GND metal layer and the second wiring layer 5, which is attached to the bottom layer of the RF chip 1, is also relatively large. Furthermore, since there are no metal traces between the GND metal layer and the second wiring layer 5, no capacitance parasitic will be generated between the GND metal layer and the second wiring layer 5.
[0067] It should be emphasized that in the prior art, the RF chip 1 is placed upright on the substrate. Therefore, the layer with pins of the RF chip 1 is the upper layer, and the layer opposite to the pin layer is the lower layer. However, in this application, the RF chip 1 is flip-chip packaged. Therefore, the pin layer of the RF chip 1 is in contact with the uppermost layer of the dielectric layer 2 below, and the lower layer of the RF chip 1 opposite to the pin layer is in contact with the second wiring layer 5 above.
[0068] As a preferred embodiment, it also includes:
[0069] Several radio frequency front-end modules 7 are encapsulated using injection molding epoxy molding compound;
[0070] The third wiring layer 8 is located below the RF front-end module 7, and its surface is provided with metal traces arranged according to the third preset wiring rule; the pin surface of the RF front-end module 7 faces the third wiring layer 8.
[0071] The third routing layer 8 and the second routing layer 5 are connected by SMT;
[0072] The pins of the RF front-end module 7 are connected to the metal traces on the third wiring layer 8, and are also connected to the metal traces on the second wiring layer 5 through the metal traces on the third wiring layer 8.
[0073] Please refer to Figure 2 In this embodiment, several RF front-end modules 7 can be encapsulated using injection molding epoxy molding compound. After encapsulation, each RF front-end module 7 is connected to the second wiring layer 5 via SMT through the third wiring layer 8. The metal traces on the third wiring layer 8 can be connected to the metal traces on the second wiring layer 5. Thus, the RF front-end module 7 can be connected to the RF chip 1 through the first wiring layer 3, the second wiring layer 5, and the third wiring layer 8, as described above for the connection method between the first RF packaging system and the second RF packaging system. This embodiment will not be elaborated further here.
[0074] In addition, the RF front-end module 7 can also be packaged using a 2P2M or 3P3M packaging architecture. Depending on the actual application, it can package devices that are less affected by interference and capacitive loading, such as inductors, capacitors, power chips, power amplifier chips, filters, and RF switches. It can use RDL and TMV for top and bottom interconnection. The second wiring layer 5 and the third wiring layer 8 can adopt the traditional SMT surface mount method to realize the multi-layer RF packaging system and the SMT surface mount stacking between the RF packaging system and the RF front-end module 7, thereby realizing a more complex RF microsystem architecture and a more flexible connection form.
[0075] Based on this, the RF front-end module 7 includes one or more combinations of inductors, capacitors, power chips, power amplifier chips, filters, and RF switches.
[0076] As a preferred embodiment, it also includes:
[0077] Several antenna modules 9 are each encapsulated using a glass substrate;
[0078] The fourth wiring layer 10 is located below the antenna module 9, and its surface is provided with metal traces arranged according to the fourth preset wiring rule; the feeding surface of the antenna module 9 faces the fourth wiring layer 10.
[0079] The fourth routing layer 10 and the second routing layer 5 are connected via SMT.
[0080] The feed terminal of antenna module 9 is connected to the metal trace on the fourth wiring layer 10, and is connected to the metal trace on the second wiring layer 5 through the metal trace on the fourth wiring layer 10.
[0081] In addition, please refer to Figure 3 , Figure 3 This is a schematic diagram of the third panel-level RF packaging system provided by this utility model. The RF packaging system on top of the above-mentioned dual-layer RF packaging system architecture can be replaced with an antenna module 9 made using a glass substrate. The antenna module 9 can be an AOP antenna. The glass substrate is also mounted on top of the second wiring layer 5 using SMT surface mount technology. The transmission signal of the RF chip 1, such as the RF power amplifier chip, is connected to the feed terminal of the antenna module 9 through the metal vias in the dielectric layer 2, the metal traces on the first wiring layer 3, the metal copper pillars 6, the metal traces on the second wiring layer 5, and the metallized vias TGV on the glass substrate. Based on this, the feed line length between the RF chip 1 and the antenna module 9 can be shortened, the insertion loss can be reduced, and the RF packaging system can be highly miniaturized and integrated.
[0082] In a preferred embodiment, the position of the metal via on the uppermost dielectric layer 2 corresponds perpendicularly to the position of the pins of the RF chip 1.
[0083] In this embodiment, the position of the metal via on the top dielectric layer 2 can be perpendicularly aligned with the position of the pins of the RF chip 1, so as to avoid increasing the design difficulty of the dielectric layer 2 due to routing on the top dielectric layer 2, thereby reducing the cost.
[0084] It should be noted that if there are some metal traces on the dielectric layer 2 of other layers, the position of the metal vias on the dielectric layer 2 other than the top dielectric layer 2 can be adjusted according to the requirements and the position of the metal traces, so that the pad of the RF chip 1 can be connected to the first rewiring layer 3.
[0085] As a preferred embodiment, the BGA solder ball position uses high-lead solder balls.
[0086] The BGA solder balls in this application may be, but are not limited to, high-lead solder balls, wherein the melting point temperature of high-lead solder balls is as high as 235°C, and the stability of high-lead solder balls is relatively high.
[0087] In a preferred embodiment, the total thickness of each dielectric layer 2 is not less than a preset thickness.
[0088] In this embodiment, the total thickness of each dielectric layer 2 is not less than the preset thickness to ensure that the distance between the first redistribution layer 3 and the RF chip 1 is large enough. This can be achieved by selecting the number of dielectric layers 2. The preset thickness can be 100um, but this application does not limit it.
[0089] In summary, compared to the existing technology of bonding the pad of the RF chip 1 to the PCB board by gold wire bonding, this application flips the RF chip 1 onto the dielectric layer board 2 and uses a fan-in packaging method to make the horizontal area of the packaging system consistent with the horizontal area of the RF chip 1. In addition, even if additional copper pillars are added, the horizontal direction is only increased by the diameter of one or two copper pillars, and the diameter of the copper pillars is only 100um~500um, so the overall volume of the packaging system will not increase too much.
[0090] Please refer to Figure 4 and Figure 5 , Figure 4 This invention provides a schematic diagram of the routing on a redistribution layer. Figure 5 This utility model provides a schematic diagram of the wiring for a fan-in package, wherein... Figure 4 The square area at the top center is the pad for the RF chip 1. The pad is connected to the bottom first routing layer 3 through a circular metal via on the multilayer dielectric substrate 2. It is then connected to the reserved position for soldering BGA solder balls through the metal traces on the first routing layer 3. The larger circular area below is the area for soldering BGA solder balls. Figure 5 As can be seen, the pads of the RF chip 1 are connected to the bottommost first routing layer 3 through the metal vias on the multilayer dielectric substrate 2, and then fan-in through the metal traces on the first routing layer 3 to the area directly below the RF chip 1. The BGA solder balls 4 are also soldered directly below the RF chip 1. Based on this, not only is space saved, but since the first routing layer 3 and the RF chip 1 are separated by the multilayer dielectric substrate 2, no capacitive parasitics will be generated between the first routing layer 3 and the GND metal layer of the RF chip 1.
[0091] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0092] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A panel-level radio frequency packaging system, characterized in that, include: At least one radio frequency chip is encapsulated using injection molding epoxy molding compound; A multi-layered dielectric substrate is located below each of the radio frequency (RF) chips, with the pin surfaces of the RF chips facing the dielectric substrate and in direct contact with the top layer of the dielectric substrate; each dielectric substrate has a metal via that penetrates the dielectric substrate vertically. The first wiring layer is located at the bottom layer of the multilayer dielectric substrate, and its surface is provided with metal traces arranged according to a first preset wiring rule; the metal traces on the first wiring layer are located in the vertically downward orthogonal projection area of the RF chip. Multiple BGA solder balls are distributed on the bottom surface of the first rewiring layer according to a preset distribution rule; The pins of the RF chip are connected to the metal traces of the first redistribution layer sequentially downwards through the metal vias of each dielectric layer, and are connected to the BGA solder balls through the metal traces.
2. The panel-level RF packaging system as described in claim 1, characterized in that, Also includes: The second wiring layer is located above the radio frequency chip, and its surface is provided with metal traces arranged according to the second preset wiring rule; At least one copper pillar is distributed around the radio frequency chip; The second redistribution layer, the copper pillars, and the RF chip are encapsulated using injection molding epoxy molding compound; The metal traces on the second rewiring layer are connected to the metal traces on the first rewiring layer through the metal copper pillars, and are connected to the pins of the RF chip and / or the BGA solder balls through the metal traces on the first rewiring layer.
3. The panel-level RF packaging system as described in claim 2, characterized in that, Also includes: Several radio frequency front-end modules are encapsulated using injection molding epoxy molding compound; The third wiring layer is located below the RF front-end module, and its surface is provided with metal traces arranged according to a third preset wiring rule; the pin surface of the RF front-end module faces the third wiring layer. The third routing layer and the second routing layer are connected via SMT; The pins of the RF front-end module are connected to the metal traces on the third wiring layer, and are also connected to the metal traces on the second wiring layer through the metal traces on the third wiring layer.
4. The panel-level RF packaging system as described in claim 3, characterized in that, The radio frequency front-end module includes one or more of the following: power supply chip, capacitor, inductor, and power amplifier chip.
5. The panel-level RF packaging system as described in claim 2, characterized in that, Also includes: Several antenna modules are individually packaged using glass substrates; The fourth wiring layer is located below the antenna module, and its surface is provided with metal traces arranged according to the fourth preset wiring rule; the feed surface of the antenna module faces the fourth wiring layer. The fourth routing layer and the second routing layer are connected via SMT; The feed terminal of the antenna module is connected to the metal trace on the fourth wiring layer, and is also connected to the metal trace on the second wiring layer through the metal trace on the fourth wiring layer.
6. The panel-level RF packaging system as described in claim 1, characterized in that, The position of the metal via on the topmost dielectric layer corresponds perpendicularly to the position of the pins of the RF chip.
7. The panel-level RF packaging system as described in claim 1, characterized in that, The dielectric layer is made of deposited polyimide or Ajinomoto stacked film ABF.
8. The panel-level RF packaging system as described in claim 1, characterized in that, Also includes: The under-bump metallization layer (UBM) is distributed below the first redistribution layer according to the preset distribution rules and is soldered to each of the BGA solder balls.
9. The panel-level RF packaging system as described in claim 1, characterized in that, The BGA solder balls are high-lead solder balls.
10. The panel-level RF packaging system according to any one of claims 1-9, characterized in that, The total thickness of each of the dielectric layers is not less than the preset thickness.