Communication device for an ethernet isolated network

Abstract

The utility model discloses a kind of communication equipment of ethernet isolated network, including multi-machine communication circuit, FPGA transmission data circuit, fan control circuit and power-on delay circuit.Multiple machine communication circuit realizes and communicates with external multiple equipment;FPGA transmission data circuit is shaped to transmission data and is handled;Fan control circuit connects cooling fan, and it is controlled to start and stop;Power-on delay circuit is connected between each functional circuit and external power supply, and power supply output electric energy is delayed and then supplied to each circuit, and the utility model realizes the orderly start of each functional module by power-on delay circuit, avoid the surge current generated by simultaneous power-on to cause damage to circuit, improve equipment stability.

Description

Technical Field

[0001] This utility model relates to a communication device, and more specifically to a communication device for an Ethernet isolated network. Background Technology

[0002] In the operation of communication equipment in Ethernet isolated networks, the stability of the power supply at the moment of power-on has always been a key factor affecting the reliability and lifespan of the equipment. Because the power supply system often generates problems such as voltage overshoot, surge current, and voltage instability during startup, these adverse factors can cause great impact on core electronic components such as chips, and in severe cases, even cause permanent damage to the chips, thereby affecting the normal operation of the entire electronic device. Utility Model Content

[0003] In view of the shortcomings of the existing technology, the purpose of this utility model is to provide a communication device for an Ethernet isolation network that avoids damage to the chip caused by voltage instability when the power is first turned on.

[0004] To achieve the above objectives, this utility model provides the following technical solution: a communication device for an Ethernet isolated network, comprising:

[0005] Multi-machine communication circuit, used for multi-machine communication with multiple external communication devices;

[0006] FPGA data transmission circuitry is used to shape the transmitted data.

[0007] The fan control circuit is connected to the cooling fan inside the communication equipment to control the fan's start and stop.

[0008] The power-on delay circuit is connected between the multi-machine communication circuit, the FPGA data transmission circuit, the fan control circuit, and the external power supply to delay the power output before using it as the power output.

[0009] As a further improvement of this utility model, the power-on delay circuit includes:

[0010] The switching transistor 7FB1 has a first terminal, a second terminal and a control terminal. The first terminal of the switching transistor 7FB1 is connected to an external power supply, and the second terminal is used to provide power output.

[0011] A delay circuit is connected to the control terminal of the switching transistor 7FB1 to control the switching between the first and second terminals of the switching transistor 7FB1.

[0012] As a further improvement of this utility model, the delay circuit includes:

[0013] The transistor 7Q1 has its base connected to ground via resistor R139 and also connected to an external power supply. Its collector is grounded, and its emitter is connected to external power supply via resistor 7R134 and then resistor 7R131.

[0014] Transistor 7Q2 has its collector connected to resistor 7R135 and then to the control terminal of switching transistor 7FB1. The other end of resistor 7R135 is connected to resistor 7R130 and then to an external power supply. The emitter of transistor 7Q2 is grounded, and its base is connected to Zener diode 7D1, then to charging capacitor 7EC10 and then to ground. The node between charging capacitor 7EC10 and Zener diode 7D1 is also connected to resistor 7R134.

[0015] As a further improvement of this utility model, a capacitor 7EC9 and a Zener diode 7D2 are connected in parallel at the other end of the resistor 7R131 relative to the emitter of the transistor 7Q1.

[0016] As a further improvement of this utility model, the fan control circuit includes:

[0017] The transistor 4Q1 has a collector connected to a diode 4D11 and then to a power supply, and a resistor 4FB1 connected to the power supply. The node between the diode 4D11 and the collector of the transistor 4Q1 is connected to an external fan. The emitter of the transistor 4Q1 is grounded, and the base is connected to a resistor 4R55 and then to an MCU control chip.

[0018] The beneficial effects of this utility model are:

[0019] By incorporating a power-on delay circuit, a delayed power-on is achieved during the initial startup phase, ensuring a more stable power supply to the chip. This reduces the impact of voltage overshoot and surge current on core electronic components, extends the lifespan of chips and other components, and improves equipment reliability. Simultaneously, the fan control circuit precisely controls the starting and stopping of the cooling fan, ensuring adequate heat dissipation during equipment operation and further guaranteeing stable operation. Overall, this invention addresses the shortcomings of traditional Ethernet isolated network communication equipment in terms of power stability and heat dissipation control, improving equipment reliability and stability, and providing strong support for long-term stable operation. Attached Figure Description

[0020] Figure 1 The circuit diagram for the power-on delay circuit;

[0021] Figure 2 This is a circuit diagram of the fan control circuit;

[0022] Figure 3 Circuit diagram for FPGA data transmission circuit;

[0023] Figure 4 This is a circuit diagram of a multi-machine communication circuit. Detailed Implementation

[0024] The present invention will now be described in further detail with reference to the embodiments shown in the accompanying drawings.

[0025] Reference Figures 1 to 4 As shown, the communication device of the Ethernet isolated network in this embodiment includes a multi-machine communication circuit, an FPGA data transmission circuit, a fan control circuit, and a power-on delay circuit. The multi-machine communication circuit is used to communicate with multiple external devices. The FPGA data transmission circuit shapes the transmitted data. The fan control circuit connects to the cooling fan to control its start and stop. The power-on delay circuit connects each circuit to the external power supply, delaying the output of power. In this embodiment, a microcontroller (MCU) chip is used to achieve coordinated control of multiple circuits, ensuring that the voltage and current are stabilized before inputting to the chip. This circuit can achieve the power-on delay function, avoiding damage to the chip caused by voltage instability at the moment of power-on, obtaining a stable and reliable 12V power supply, and controlling the power-on sequence of different boards. This solves the problem of equipment damage caused by unstable power supply at the moment of power-on in the background technology, improving equipment reliability. Figure 4 As shown, the multi-machine communication circuit in this embodiment uses operational amplifiers 4U4A and 4U4B, along with pull-up resistors 4R3, 4R6, and 4R4, to amplify the level signal and prevent abnormal transmitted level signals. Figure 3 As shown, the FPGA data transmission circuit in this embodiment is mainly implemented by combining the FPGA digital chip and its peripheral circuits. The chip reshapes the transmitted data, which can not only restore the original waveform of the lost level signal received during long-distance transmission, but also effectively prevent the FPGA chip from being burned out by accidental excessive voltage.

[0026] Furthermore, refer to Figure 1 As shown, the power-on delay circuit includes a switching transistor 7FB1 and a delay circuit. The first terminal of the switching transistor 7FB1 is connected to an external power supply, and the second terminal outputs power. The delay circuit is connected to its control terminal to control its on / off state. The delay circuit includes transistors 7Q1 and 7Q2. The base of transistor 7Q1 is grounded via resistor R139 and connected to the external power supply, its collector is grounded, and its emitter is connected to the external power supply via resistors 7R134 and 7R131. The collector of transistor 7Q2 is connected to the control terminal of switching transistor 7FB1 via resistor 7R135, its emitter is grounded, and its base is grounded via Zener diode 7D1 and charging capacitor 7EC10, with the junction connected to resistor 7R134. Specifically, when the voltage reaches a certain value, transistor 7Q1 turns off, causing the subsequent current to increase and accelerating the energy storage of capacitor 7EC10. When the voltage reaches a certain value, the current flows through Zener diode 7D1, causing 7Q2 to conduct, allowing current to flow through MOSFET 7FB1, ultimately achieving the function of delayed power-on.

[0027] Furthermore, a capacitor 7EC9 and a Zener diode 7D2 are connected in parallel at the other end of the resistor 7R131. The capacitor 7EC9 filters and stabilizes the voltage, while the Zener diode 7D2 limits the voltage amplitude to prevent overvoltage damage to components, further improving the stability and anti-interference capability of the delay circuit and ensuring reliable power-on during the delay.

[0028] Furthermore, refer to Figure 2 As shown, the fan control circuit includes a transistor 4Q1. Its collector is connected to the power supply via a diode 4D11 and a resistor 4FB1, its node is connected to the external fan, its emitter is grounded, and its base is connected to the MCU control chip via a resistor 4R55. The MCU control chip outputs high and low level signals. When the signal is high, transistor 4Q1 conducts, and the fan runs; when the signal is low, the fan stops. This design adjusts the fan's start and stop in real time according to the equipment's operating temperature, achieving intelligent heat dissipation and avoiding energy waste and noise problems caused by continuous operation.

[0029] In summary, this solution constructs a highly reliable Ethernet isolated communication device by employing a resistive-capacitive delay design in the power-on delay circuit, intelligent start-stop control in the fan control circuit, and combining multi-machine communication and FPGA data shaping functions. Compared to the background technology, 1) delayed power-on effectively suppresses voltage overshoot and surge current, protecting core components; 2) intelligent fan control improves heat dissipation efficiency and reduces energy consumption; and 3) multi-machine communication and data shaping ensure stable network communication. This device solves the problems of poor power-on stability and low heat dissipation efficiency of traditional devices, and has advantages such as reliable power protection, intelligent heat dissipation, and stable communication, making it suitable for Ethernet isolated network scenarios with high reliability requirements.

[0030] The above description is merely a preferred embodiment of this utility model. The protection scope of this utility model is not limited to the above embodiments. All technical solutions falling within the scope of this utility model's concept are protected. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principle of this utility model should also be considered within the protection scope of this utility model.

Claims

1. A communication device for an Ethernet isolated network, characterized by: include: Multi-machine communication circuit, used for multi-machine communication with multiple external communication devices; FPGA data transmission circuitry is used to shape the transmitted data. The fan control circuit is connected to the cooling fan inside the communication equipment to control the fan's start and stop. The power-on delay circuit is connected between the multi-machine communication circuit, the FPGA data transmission circuit, the fan control circuit, and the external power supply to delay the power output before using it as the power output.

2. The communication device of the Ethernet isolated network according to claim 1, characterized in that: The power-on delay circuit includes: The switching transistor 7FB1 has a first terminal, a second terminal and a control terminal. The first terminal of the switching transistor 7FB1 is connected to an external power supply, and the second terminal is used to provide power output. A delay circuit is connected to the control terminal of the switching transistor 7FB1 to control the switching between the first and second terminals of the switching transistor 7FB1.

3. The communication device of the Ethernet isolated network according to claim 2, characterized in that: The delay circuit includes: The transistor 7Q1 has its base connected to ground via resistor R139 and also connected to an external power supply. Its collector is grounded, and its emitter is connected to external power supply via resistor 7R134 and then resistor 7R131. Transistor 7Q2 has its collector connected to resistor 7R135 and then to the control terminal of switching transistor 7FB1. The other end of resistor 7R135 is connected to resistor 7R130 and then to an external power supply. The emitter of transistor 7Q2 is grounded, and its base is connected to Zener diode 7D1, then to charging capacitor 7EC10 and then to ground. The node between charging capacitor 7EC10 and Zener diode 7D1 is also connected to resistor 7R134.

4. The communication device of the Ethernet isolated network according to claim 3, characterized in that: The resistor 7R131 is connected in parallel with a capacitor 7EC9 and a Zener diode 7D2 at the other end opposite the emitter of the transistor 7Q1.

5. The communication device of the Ethernet isolated network according to any one of claims 1 to 4, characterized in that: The fan control circuit includes: The transistor 4Q1 has a collector connected to a diode 4D11 and then to a power supply, and a resistor 4FB1 connected to the power supply. The node between the diode 4D11 and the collector of the transistor 4Q1 is connected to an external fan. The emitter of the transistor 4Q1 is grounded, and the base is connected to a resistor 4R55 and then to an MCU control chip.

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