A large chip bottom heat dissipation and anti-warping device

Abstract

The utility model relates to chip packaging technical field discloses a big chip bottom heat dissipation and anti warping device. This big chip bottom heat dissipation and anti warping device includes chip and the PCB encapsulated in the lower chip, and the silicon carbide substrate is encapsulated between chip and PCB, and a plurality of array type distribution's through -hole is seted up on the silicon carbide substrate, is equipped with metal layer on the inner wall of through -hole, and chip and PCB respectively through the tin ball with metal layer carry out electric connection. This structure effectively solved when the chip operating temperature violent change (power cycle), and the risk that the solder joint fatigue cracking, chip warping even breakage because of the large difference of thermal expansion coefficient between PCB and semiconductor chip.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging technology, specifically a heat dissipation and anti-warping device for the bottom of a large chip. Background Technology

[0002] BGA (Ball Grid Array) is an advanced integrated circuit packaging technology that uses ball-shaped solder joints (usually solder balls) instead of the pins of traditional packages to connect to the PCB (Printed Circuit Board). BGA packaging technology is mainly used for high-density chips that require high-speed signal transmission and high heat dissipation performance, and is widely used in computers, communications, consumer electronics and other fields.

[0003] As chip integration and power continue to increase, chip area also increases, leading to a sharp increase in heat generated during operation. If heat cannot be dissipated in time, the chip's temperature will continue to rise, affecting its performance and stability. Although external fans or liquid cooling devices are used to dissipate heat, PCBs are mainly made of resin, which has low thermal conductivity and heat dissipation. The junction temperature between the chip and the PCB cannot be dissipated in time. Especially in applications such as electric vehicles and industrial drives that require frequent start-stop and drastic power fluctuations, the chip's temperature changes rapidly. The resulting high temperature leads to a large coefficient of thermal expansion. Since the coefficients of thermal expansion of the PCB and the semiconductor chip differ significantly, this can lead to the risk of solder joint fatigue cracking, chip warping, or even breakage.

[0004] Therefore, there is an urgent need for a large chip bottom heat dissipation and anti-warping device to solve the above problems. Utility Model Content

[0005] Based on the above, the purpose of this utility model is to provide a heat dissipation and anti-warping device for the bottom of a large chip, so as to solve the problem that the semiconductor chip is prone to high temperature between the chip and the PCB under high frequency and high power operation, and the large difference in the coefficient of thermal expansion between the PCB and the semiconductor chip will lead to increased stress, which will cause fatigue cracking of the solder joint, chip warping or even breakage.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0007] This utility model provides a bottom heat dissipation and anti-warping device for large chips, including a chip and a PCB packaged under the chip.

[0008] A silicon carbide substrate is packaged between the chip and the PCB. The silicon carbide substrate has a plurality of through holes arranged in an array, and a metal layer is provided on the inner wall of the through holes.

[0009] The chip and PCB are electrically connected to the metal layer via solder balls.

[0010] As an optional technical solution for heat dissipation and anti-warping devices at the bottom of large chips, the area of ​​the silicon carbide substrate is larger than the area of ​​the chip; the diameter of the through hole is smaller than the diameter of the solder ball.

[0011] As an optional technical solution for heat dissipation and anti-warping devices at the bottom of large chips, the port circumference of the through hole is provided with an annular recess.

[0012] As an optional technical solution for heat dissipation and anti-warping devices at the bottom of large chips, the annular platform is provided with a metal layer.

[0013] As an optional technical solution for heat dissipation and anti-warping devices at the bottom of large chips, the metal layer is a copper layer with a thickness of 1~20um.

[0014] As an optional technical solution for heat dissipation and anti-warping devices at the bottom of large chips, the thickness of the silicon carbide substrate is 0.5~3mm.

[0015] The beneficial effects of this utility model are as follows:

[0016] This utility model provides a large chip bottom heat dissipation and anti-warping device, which includes a chip and a PCB packaged below the chip. A silicon carbide substrate is packaged between the chip and the PCB. The silicon carbide substrate has several through holes arranged in an array, and a metal layer is provided on the inner wall of the through holes. In this structure, the contacts on the chip and the PCB are electrically connected to the metal layer by solder balls, ensuring good electrical and communication signal transmission between the chip and the PCB. The structure of the silicon carbide substrate and the chip can effectively dissipate heat from the bottom of the chip. At the same time, the thermal expansion coefficients of silicon carbide and semiconductor chip materials are more closely matched, which greatly reduces the thermal stress between the silicon carbide substrate and the chip when the chip operating temperature changes drastically (power cycling). This effectively solves the risk of solder joint fatigue cracking, chip warping, or even breakage caused by the large difference in thermal expansion coefficients between the PCB and the semiconductor chip at high temperatures. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall structure of the heat dissipation and anti-warping device at the bottom of the large chip in this embodiment of the present invention;

[0018] Figure 2 This is an exploded view of the heat dissipation and anti-warping device at the bottom of the large chip in this embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of the silicon carbide substrate in an embodiment of the present invention;

[0020] Figure 4 for Figure 3 Enlarged diagram of point A in the middle.

[0021] In the picture:

[0022] 1. Chip; 2. Solder ball; 3. Silicon carbide substrate; 30. Through hole; 31. Copper layer; 32. Circular recess; 4. PCB. Detailed Implementation

[0023] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, not the entire structure.

[0024] In the description of this utility model, unless otherwise explicitly specified and limited, the terms "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0025] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0026] In the description of this embodiment, terms such as "upper," "lower," "left," and "right" are based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of description and simplification of operation, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0027] In the description of this utility model, unless otherwise stated, "a plurality of" means two or more. Furthermore, the terms "first" and "second" are used merely for descriptive distinction and have no specific meaning.

[0028] like Figure 1-4 As shown, this utility model provides a large chip bottom heat dissipation and anti-warping device, which includes a chip 1 and a PCB4 packaged below the chip 1. A silicon carbide substrate 3 is packaged between the chip 1 and the PCB4. A plurality of through holes 30 distributed in an array are opened on the silicon carbide substrate 3, and a metal layer is provided on the inner wall of the through holes 30. The chip 1 and the PCB4 are electrically connected to the metal layer through solder balls 2 respectively.

[0029] This utility model provides a large chip bottom heat dissipation and anti-warping device. By encapsulating a silicon carbide substrate 3 between the chip 1 and PCB 4, and electrically connecting the contacts on the chip 1 and PCB 4 to the metal layer through solder balls 2, good electrical and communication signal transmission between the chip 1 and PCB 4 is ensured. The structure of the silicon carbide substrate 3 and the chip 1 can effectively dissipate heat from the bottom of the chip 1. At the same time, the thermal expansion coefficients of silicon carbide and semiconductor chip materials are more closely matched, which greatly reduces the thermal stress between the silicon carbide substrate 3 and the chip 1 when the operating temperature of the chip 1 changes drastically (power cycling). This effectively solves the risk of solder joint fatigue cracking, chip 1 warping or even breakage caused by the large difference in thermal expansion coefficients between PCB 4 and semiconductor chip 1 and the high temperature.

[0030] Specifically, such as Figure 2 As shown, the area of ​​the silicon carbide substrate 3 is equal to or greater than the area of ​​the chip 1. In this embodiment, the area of ​​the silicon carbide substrate 3 is greater than the area of ​​the chip 1. Therefore, when the chip 1 generates a high temperature under high power operation, the larger area of ​​the silicon carbide substrate 3 helps to dissipate the heat generated by the chip 1 to a certain extent, thereby reducing the junction temperature of the chip 1, preventing the junction temperature of the chip 1 from being too high and affecting its performance, and improving the stability and service life of the chip 1.

[0031] Furthermore, the vias 30 are arranged in an array, and the solder balls 2 are distributed in two layers, one between the chip 1 and the silicon carbide substrate 3, and the other between the PCB 4 and the silicon carbide substrate 3. Each via 30 has one solder ball 2 connected to its upper and lower ends, and the solder balls 2 are soldered to the metal layers at the via 30 ends to ensure electrical and communication signal transmission between the chip 1 and the PCB 4. It should be noted that the metal layer is a metal material with good conductivity; in this embodiment, the metal layer is a copper layer 31. The thickness of the copper layer 31 can be selected between 1 and 20 μm, depending on the actual processing and... As observed during testing, when the thickness of copper layer 31 is greater than 0.8um, no voids will appear between copper layer 31 and the inner wall of via 30. Therefore, the thickness of copper layer 31 can be selected from 1 to 20um, specifically 1um, 5um, 8um, 10um, 15um, or 20um. This ensures that copper layer 31 can fully cover the inner wall of via 30 without voids, while also ensuring that solder balls 2 are stably soldered onto copper layer 31 and maintaining stable resistivity. This provides a stable electrical and communication signal connection and transmission between chip 1 and PCB4.

[0032] In this embodiment, as Figure 3 and Figure 4 As shown, annular recesses 32 are provided on the circumference of the upper and lower ports of the through-hole 30. A copper layer 31 is provided on the annular recesses 32. In this structure, the annular recesses 32 not only provide precise positioning for chip 1 during packaging, but also provide a more robust structure for solder balls 2 when soldered to the copper layer 31. Therefore, even when chip 1 is exposed to high temperatures, the stability between solder balls 2 and copper layer 31 can be ensured, effectively preventing solder joint detachment and improving the physical structural stability between chip 1, PCB 4, and silicon carbide substrate 3. It should be noted that the thickness of the silicon carbide substrate 3 provided in this embodiment is 0.5~3mm. This thickness range ensures the mechanical stability of the entire chip packaging assembly and also provides effective temperature uniformity and heat dissipation performance for chip 1.

[0033] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the present utility model without departing from the scope of the present utility model shall fall within the scope of the present utility model.

Claims

1. A heat dissipation and anti-warping device for the bottom of a large chip, comprising a chip and a PCB packaged beneath the chip, characterized in that, A silicon carbide substrate is packaged between the chip and the PCB. The silicon carbide substrate has a plurality of through holes arranged in an array, and a metal layer is provided on the inner wall of the through holes. The chip and PCB are electrically connected to the metal layer via solder balls.

2. The heat dissipation and anti-warping device for the bottom of a large chip according to claim 1, characterized in that, The area of ​​the silicon carbide substrate is larger than the area of ​​the chip; the diameter of the through hole is smaller than the diameter of the solder ball.

3. The large chip bottom heat dissipation and anti-warping device according to claim 2, characterized in that, The through hole has an annular recessed platform on its port circumference.

4. The heat dissipation and anti-warping device for the bottom of a large chip according to claim 3, characterized in that, The annular platform is provided with a metal layer.

5. A large chip bottom heat dissipation and anti-warping device according to claim 1 or 4, characterized in that, The metal layer is a copper layer with a thickness of 1~20um.

6. The heat dissipation and anti-warping device for the bottom of a large chip according to claim 1, characterized in that, The thickness of the silicon carbide substrate is 0.5~3mm.

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