Power module and electronic device

Abstract

The application relates to a power module and electronic equipment. The power module comprises a half-bridge circuit, a first back plate and a second back plate arranged independently; semiconductor devices of an upper bridge arm of the half-bridge circuit are arranged on the first back plate through a plurality of special-shaped frames, and semiconductor devices of a lower bridge arm of the half-bridge circuit are arranged on the second back plate through a plurality of special-shaped frames; the plurality of special-shaped frames on the first back plate and the plurality of special-shaped frames on the second back plate are respectively used for realizing interlacing between an output loop and an input loop of direct current, so that the parasitic inductance is reduced, and the technical problem that the parasitic inductance of the power module in the prior art is large is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a power module and an electronic device. Background Technology

[0002] EconoDUAL TM The 3 package is a medium-to-high power module packaging platform that achieves a leap in power density with a compact size (standard industrial package). Since its introduction in 2010, it has become a benchmark product in the field of power electronics through continuous technological iteration and application expansion. Current models mainly include FFR900R12ME7 and FFR600R12ME4.

[0003] EconoDUAL is currently available. TM The internal substrate layout of the 3-package generally exhibits a high parasitic inductance value (greater than 20nH). This high parasitic inductance, combined with the current change rate, generates a spike much higher than the DC bus voltage at the moment of device turn-off, leading to overvoltage failure and severely limiting the module's usability. At the same time, the parasitic inductance, together with the module's internal capacitance (such as the junction capacitance of an IGBT), forms an LC resonant circuit, which excites high-frequency oscillations at the moment of switching, worsening electromagnetic interference, severely affecting the normal waveform output, and increasing the difficulty and cost of shielding design.

[0004] To reduce voltage stress exceeding the rated value, the common practice is to add additional absorption circuits, such as Snubber buffer circuits. However, this increases device losses, leading to increased junction temperature and affecting lifespan, and also increases system cost and size.

[0005] There is currently no effective solution to the problem of high parasitic inductance in power modules. Utility Model Content

[0006] This application provides a power module and an electronic device to solve the technical problem of large parasitic inductance in power modules in the prior art.

[0007] According to one aspect of the embodiments of this application, this application provides a power module, including: a half-bridge circuit, a first substrate and a second substrate arranged independently of each other; the semiconductor devices of the upper arm of the half-bridge circuit are arranged on the first substrate through multiple irregularly shaped frames, and the semiconductor devices of the lower arm of the half-bridge circuit are arranged on the second substrate through multiple irregularly shaped frames; the multiple irregularly shaped frames on the first substrate and the multiple irregularly shaped frames on the second substrate are used to realize the interleaving between the output circuit and the input circuit of DC current, thereby reducing parasitic inductance.

[0008] Optionally, the plurality of irregularly shaped frames on the first liner include E-shaped frames and Π-shaped frames, wherein the E-shaped frames and the Π-shaped frames are nested within each other.

[0009] Optionally, the Π-shaped frame is used to carry the semiconductor device of the upper bridge arm of the half-bridge circuit, and the Π-shaped frame is connected to the E-shaped frame via bonding wires.

[0010] Optionally, the semiconductor device of the upper arm of the half-bridge circuit is a SiC MOS transistor, which is soldered to the first substrate using soldering or other soldering processes.

[0011] Optionally, the plurality of irregular frames on the second liner include a first C-shaped frame, a second C-shaped frame, and a square frame, wherein the first C-shaped frame encloses the second C-shaped frame, and the second C-shaped frame encloses the square frame.

[0012] Optionally, the U-shaped frame is used to carry the semiconductor device of the lower bridge arm of the half-bridge circuit, and the U-shaped frame is connected to the second C-shaped frame via bonding wires.

[0013] Optionally, the plurality of irregular frames on the second liner include a first C-shaped frame, a second C-shaped frame, and a Hundred-shaped frame, wherein the first C-shaped frame encloses the second C-shaped frame, and the second C-shaped frame encloses the Hundred-shaped frame.

[0014] Optionally, the Hundred-shaped frame is used to carry the semiconductor device of the lower bridge arm of the half-bridge circuit, and the Hundred-shaped frame is connected to the second C-shaped frame via bonding wires.

[0015] Optionally, the semiconductor device of the lower arm of the half-bridge circuit is a SiC MOS transistor, which is soldered to the second substrate using soldering or other soldering processes.

[0016] According to another aspect of the embodiments of this application, this application provides an electronic device including the power module described above.

[0017] Compared with related technologies, the technical solutions provided in this application have the following advantages:

[0018] This application provides a power module including a half-bridge circuit, a first substrate and a second substrate arranged independently of each other; the semiconductor devices of the upper arm of the half-bridge circuit are arranged on the first substrate through multiple irregularly shaped frames, and the semiconductor devices of the lower arm of the half-bridge circuit are arranged on the second substrate through multiple irregularly shaped frames; the multiple irregularly shaped frames on the first substrate and the multiple irregularly shaped frames on the second substrate are respectively used to realize the interleaving between the output circuit and the input circuit of DC current, thereby reducing parasitic inductance and solving the technical problem of large parasitic inductance of power modules in the prior art. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a power module in related technologies;

[0022] Figure 2 This is a schematic diagram of a power module provided according to an embodiment of this application;

[0023] Figure 3 This is a schematic diagram of a power module provided according to an embodiment of this application;

[0024] Figure 4 This is a schematic diagram of a power module provided according to an embodiment of this application;

[0025] Figure 5 This is a circuit topology diagram of a power module according to an embodiment of this application;

[0026] Figure 6 This is a schematic diagram of a power module provided according to an embodiment of this application;

[0027] Figure 7 This is a schematic diagram of a power module provided according to an embodiment of this application;

[0028] Figure 8 This is a schematic diagram of a power module provided according to an embodiment of this application;

[0029] Figure 9 This is a schematic diagram of a power module provided according to an embodiment of this application;

[0030] Figure 10 This is a schematic diagram of a power module provided according to an embodiment of this application. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0032] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0033] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0034] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0035] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0036] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0037] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0038] like Figure 1 As shown, EconoDUAL TM 3 package ( Figure 1 The pin numbers 1-11 in the middle conform to the standard of this package. It was originally designed for IGBT modules, and the application scenarios involved did not have high requirements for operating frequency. Therefore, the harm caused by this parasitic inductance value in actual application was not obvious. However, with the development of high frequency and miniaturization of application end devices, silicon carbide-based chips have gradually replaced silicon-based chips due to their obvious advantages (high bandgap and high thermal conductivity; low on-resistance and switching loss; high switching speed and low reverse recovery loss; high voltage and high temperature resistance; excellent heat dissipation and reliability). Therefore, higher requirements are placed on the parasitic inductance of the package.

[0039] The existing substrate layout is not specifically designed for silicon carbide devices and no longer meets the application requirements of silicon carbide devices. Specifically, it is limited by EconoDUAL. TM 3. Insufficient package space prevents the implementation of a stacked busbar design on the DC side in the electrode section, which is the main reason for the high parasitic inductance.

[0040] To reduce the parasitic inductance of the power module and avoid the aforementioned hazards, this application is based on EconoDUAL. TM The 3-packaging design features a low parasitic inductance substrate layout. By optimizing the internal circuit loops of the substrate and implementing a stacked busbar design, the parasitic inductance of the substrate is reduced to below 10nH, and the overall parasitic inductance is reduced to below 15nH. This further reduces voltage spikes and switching losses, thereby improving module performance.

[0041] refer to Figure 2 or Figure 7 This application provides an embodiment of a power module:

[0042] The power module includes a half-bridge circuit (including an upper bridge arm SiC MOS24 and a lower bridge arm SiC MOS22), a first substrate 6 (or upper bridge arm substrate) and a second substrate 11 (lower bridge arm substrate) that are set independently of each other.

[0043] The semiconductor devices of the upper arm of the half-bridge circuit are arranged on the first substrate through multiple irregularly shaped frames, and the semiconductor devices of the lower arm of the half-bridge circuit are arranged on the second substrate through multiple irregularly shaped frames; the multiple irregularly shaped frames on the first substrate and the multiple irregularly shaped frames on the second substrate are used to realize the interleaving between the output circuit and the input circuit of DC current, thereby reducing parasitic inductance.

[0044] In one embodiment, on the first liner, the plurality of irregular frames include E-shaped frames and Π-shaped frames, the Π-shaped frames being used to carry the semiconductor devices of the upper bridge arm of the half-bridge circuit, the Π-shaped frames being connected to the E-shaped frames via bonding wires, and the E-shaped frames and the Π-shaped frames being nested within each other.

[0045] The aforementioned E-type frame is E-shaped, and the Π-type frame is Π-shaped. The Π-type frame carries the upper bridge arm SiC MOS of the half-bridge circuit and is connected to the E-type frame via bonding wires, forming the upper part of the half-bridge circuit structure. From the perspective of the voltage spike generation mechanism, it is generated when the half-bridge is turned on and off. Because the E-type and Π-type frames are nested, the current transmission direction alternates when the upper bridge arm is turned on. (See [reference needed]). Figure 2 The current direction of the Π-type frame is from right to left, while that of the E-type frame is from right to left on both sides and then from left to right in the middle. The magnetic flux cancellation effect of the reverse current can be used to reduce parasitic inductance.

[0046] In another embodiment, the plurality of irregularly shaped frames on the second liner include two schemes:

[0047] Option 1: The multiple irregular frames on the second substrate include a first C-shaped frame, a second C-shaped frame, and a U-shaped frame. The U-shaped frame is used to carry the semiconductor device of the lower bridge arm of the half-bridge circuit. The U-shaped frame is connected to the second C-shaped frame via bonding wires. The first C-shaped frame encloses the second C-shaped frame, and the second C-shaped frame encloses the U-shaped frame.

[0048] Option 2: The multiple irregular frames on the second liner include a first C-shaped frame, a second C-shaped frame, and a Hundred-shaped frame. The Hundred-shaped frame is used to carry the semiconductor device of the lower bridge arm of the half-bridge circuit. The Hundred-shaped frame is connected to the second C-shaped frame via bonding wires. The first C-shaped frame encloses the second C-shaped frame, and the second C-shaped frame encloses the Hundred-shaped frame.

[0049] The semiconductor device of the upper arm of the above-mentioned half-bridge circuit is a SiC MOS transistor, which is soldered to the first substrate using soldering or other soldering processes; the semiconductor device of the lower arm of the above-mentioned half-bridge circuit is a SiC MOS transistor, which is soldered to the second substrate using soldering or other soldering processes.

[0050] The aforementioned C-shaped frame is C-shaped, and the U-shaped frame is U-shaped. The U-shaped frame carries the lower bridge arm SiC MOS of the half-bridge circuit and is connected to the C-shaped frame 02 (i.e., the second C-shaped frame) via bonding wires, forming the lower part of the half-bridge circuit structure. Because the U-shaped frame is enveloped by the C-shaped frame, the current transmission direction alternates when the lower bridge arm is turned on. See [link to relevant documentation]. Figure 2 The current direction of C-frame 01 is from right to left, the current direction of C-frame 02 is from left to right, and the current direction of the square frame is from left to right and they converge. Similarly, the parasitic inductance is reduced by using the magnetic flux cancellation effect of reverse current. The principle is similar when using scheme two.

[0051] In the technical solution of this application, based on EconoDUAL TM The 3-packaging design features a low parasitic inductance substrate layout. By optimizing the internal circuit loops of the substrate, a stacked busbar design is implemented on the substrate. Specifically, irregularly shaped frames such as E-type, Π-type, □-type, and C-type frames are nested and enveloped to cancel out magnetic field changes, reducing the parasitic inductance of the substrate to below 10nH and the overall parasitic inductance to below 15nH. This further reduces voltage spikes and switching losses, and improves module performance.

[0052] As an optional embodiment, the technical solution of this application is further described in detail below with reference to specific implementation methods.

[0053] The power module of this application includes two substrates. The substrates have a three-layer structure: the top and bottom layers are copper-clad layers, and the middle layer is a ceramic layer. Either an AMB (Active Metal Brazing) ceramic substrate or a DBC (Direct Bond Copper) ceramic substrate can be used. The substrates are divided into multiple irregular base islands, serving as carriers for the power chips and internal wiring of the module.

[0054] like Figures 2 to 6 The diagram shown is an illustrative internal structure diagram of a product using the technical solution of this application (Solution 1).

[0055] See Figures 2 to 4 The numbers represent the identifiers of each component, where:

[0056] 1 represents AC terminal electrode 01, 2 represents AC terminal electrode 02, 3 represents crimping ring, 4 represents housing, 5 represents upper bridge arm drain signal pin, 6 represents upper bridge arm bushing, 7 represents E-type frame, 8 represents Π-type frame, 9 represents upper bridge arm source signal pin, 10 represents upper bridge arm gate signal pin, 11 represents lower bridge arm bushing, 11_1 represents stacked base island, 12 represents C-type frame 01, 13 represents C-type frame 02, and 14 represents U-shaped frame (reference). Figure 2 , and Figure 3 and Figure 4 In the diagram, 14_1 represents the U-shaped frame, 15 represents NTC signal pin 01, 16 represents NTC signal pin 02, 17 represents the temperature sensing resistor NTC, 18 represents the positive terminal of DC, 19 represents the negative terminal of DC, 20 represents the source signal pin of the lower bridge arm, 21 represents the gate signal pin of the lower bridge arm, 22 represents the lower bridge arm SiC MOS (Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor), 23 represents the bonding wire, 23_1 represents the stacked bonding wire, 24 represents the upper bridge arm SiC MOS, and 25 represents the substrate.

[0057] See Figure 5 and Figure 6 The numbers represent the identifiers of each pin, where:

[0058] 1 represents the lower bridge arm gate signal pin, 2 represents the lower bridge arm source signal pin, 3 represents the DC terminal negative terminal, 4 represents the DC terminal positive terminal, 5 represents the NTC signal pin 02, 6 represents the NTC signal pin 01, 7 represents the upper bridge arm gate signal pin, 8 represents the upper bridge arm source signal pin, 9 represents the upper bridge arm drain signal pin, 10 represents the AC terminal electrode 02, and 11 represents the AC terminal electrode 01.

[0059] like Figures 7 to 10 The diagram shown is an illustrative internal structure diagram of another product using the technical solution of this application (Solution 2).

[0060] See Figures 7 to 9 The numbers represent the identifiers of each component, where:

[0061] 1 represents AC terminal electrode 01, 2 represents AC terminal electrode 02, 3 represents crimping ring, 4 represents housing, 5 represents upper bridge arm drain signal pin, 6 represents upper bridge arm liner, 7 represents E-type frame, 8 represents Π-type frame, 9 represents upper bridge arm source signal pin, 10 represents upper bridge arm gate signal pin, 11 represents lower bridge arm liner, 11_1 represents stacked base island, 12 represents C-type frame 01, 13 represents C-type frame 02, 14_2 represents 100-shaped frame, 15 represents NTC signal pin 01, 16 represents NTC signal pin 02, 17 represents temperature sensing resistor NTC, 18 represents DC terminal positive, 19 represents DC terminal negative, 20 represents lower bridge arm source signal pin, 21 represents lower bridge arm gate signal pin, 22 represents lower bridge arm SiC MOS (Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor), 23 represents bonding wire, 23_1 represents stacked bonding wire, 24 represents upper bridge arm SiC MOS, 25 indicates the substrate.

[0062] See Figure 10 The numbers represent the identifiers of each pin, where:

[0063] 1 represents the lower bridge arm gate signal pin, 2 represents the lower bridge arm source signal pin, 3 represents the DC terminal negative terminal, 4 represents the DC terminal positive terminal, 5 represents the NTC signal pin 02, 6 represents the NTC signal pin 01, 7 represents the upper bridge arm gate signal pin, 8 represents the upper bridge arm source signal pin, 9 represents the upper bridge arm drain signal pin, 10 represents the AC terminal electrode 02, and 11 represents the AC terminal electrode 01.

[0064] like Figure 2 and Figure 7 As shown: Scheme 2 is more complex than Scheme 1 in terms of the heterogeneous pattern of the liner. For example, Scheme 1 uses a square frame, while Scheme 2 uses a 100-shaped frame. The loop overlap area is larger, which means more magnetic field cancellation and can bring lower parasitic inductance.

[0065] The left upper bridge arm bushing 6 mainly includes an E-type frame 7, a Π-type frame 8, and an upper bridge arm SiC MOS 24. The E-type frame and the Π-type frame are nested together, making the circuit layout more compact, thereby reducing parasitic inductance. The upper bridge arm SiC MOS is soldered to the bushing using soldering or other soldering processes.

[0066] The right lower bridge arm bushing 11 mainly includes a C-shaped frame 01 (i.e., the first C-shaped frame 12), a C-shaped frame 02 (i.e., the second C-shaped frame 13), a square frame 14 (or a 10-shaped frame in the second scheme), a lower bridge arm SiC MOS 22, a multilayer base island 11_1, and a multilayer bonding wire 23_1. The C-shaped frame 01 encloses the C-shaped frame 02, and the C-shaped frame 02 encloses the square frame, making the circuit layout more compact, thereby reducing parasitic inductance. The lower bridge arm SiC MOS is soldered to the bushing using soldering or other soldering processes. The C-shaped frame 01 is connected to the positive terminal of the DC terminal, and the multilayer base island is connected to the negative terminal of the DC terminal and the multilayer bonding wire. By interleaving the DC terminal output circuit and input circuit in the bushing, a multilayer busbar design is achieved, thereby reducing parasitic inductance. The bonding process is used to connect the chip to the copper layer on the substrate, and between the copper layer on the substrate and the pins, using bonding wires according to the pin number and the defined circuit topology. After the bonding process is completed, the module is potted to isolate moisture and improve the reliability of the module.

[0067] The technical solution adopted in this application has the following technical advantages:

[0068] 1) Generally, multilayer busbars are structurally designed by alternating layers of conductors and insulating layers. Utilizing the magnetic flux cancellation effect of reverse current and a compact circuit layout, from the perspective of power semiconductor modules, the multilayer busbar tightly stacks the DC positive (P), negative (N), and intermediate point layers. This causes the forward current (e.g., P flowing to the load when the device is turned on) and the return current circuit (N flowing to the power supply) to highly overlap spatially. According to Ampere's circuital law, the magnetic fields generated by the reverse current are in opposite directions and cancel each other out. The reduction in magnetic flux directly reduces the inductance. However, this is limited by the EconoDUAL... TM 3. Insufficient package space prevents the implementation of a stacked busbar design in the electrode section of the DC terminal, which is the main reason for the high parasitic inductance. Therefore, this application implements a stacked busbar design by interleaving the DC terminal output circuit and input circuit in the substrate, thereby reducing the parasitic inductance.

[0069] 2) By designing E-type, Π-type, □-type, and C-type frames in the liner, where the E-type and Π-type frames are nested together and the □-type frame is enveloped by the C-type frame, the circuit layout becomes more compact, thereby reducing parasitic inductance.

[0070] According to another aspect of the embodiments of this application, an electronic device is also provided, including the power module described above. The electronic device can be a household appliance, a new energy vehicle, an industrial power supply, an industrial motor, or other equipment.

[0071] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

[0072] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A power module, characterized by include: Half-bridge circuit, and independently configured first and second substrates; The semiconductor devices of the upper arm of the half-bridge circuit are arranged on the first substrate through multiple irregularly shaped frames, and the semiconductor devices of the lower arm of the half-bridge circuit are arranged on the second substrate through multiple irregularly shaped frames. The multiple irregularly shaped frames on the first liner and the multiple irregularly shaped frames on the second liner are used to achieve interleaving between the output circuit and the input circuit of DC current, thereby reducing parasitic inductance.

2. The power module of claim 1, wherein, The first liner has multiple irregularly shaped frames, including E-shaped frames and Π-shaped frames, which are nested within each other.

3. The power module of claim 2, wherein, The Π-shaped frame is used to carry the semiconductor device of the upper bridge arm of the half-bridge circuit, and the Π-shaped frame is connected to the E-shaped frame via bonding wires.

4. The power module of claim 3, wherein, The semiconductor device of the upper arm of the half-bridge circuit is a SiC MOS transistor, which is soldered to the first substrate using soldering or other soldering processes.

5. The power module of claim 1, wherein, The second liner has multiple irregularly shaped frames, including a first C-shaped frame, a second C-shaped frame, and a square frame. The first C-shaped frame encloses the second C-shaped frame, and the second C-shaped frame encloses the square frame.

6. The power module of claim 5, wherein, The U-shaped frame is used to carry the semiconductor device of the lower bridge arm of the half-bridge circuit, and the U-shaped frame is connected to the second C-shaped frame via bonding wires.

7. The power module of claim 1, wherein, The multiple irregular frames on the second liner include a first C-shaped frame, a second C-shaped frame, and a Hundred-shaped frame. The first C-shaped frame encloses the second C-shaped frame, and the second C-shaped frame encloses the Hundred-shaped frame.

8. The power module according to claim 7, characterized in that, The 100-shaped frame is used to carry the semiconductor device of the lower bridge arm of the half-bridge circuit, and the 100-shaped frame is connected to the second C-shaped frame via bonding wires.

9. The power module according to claim 6 or 7, characterized in that, The semiconductor device of the lower arm of the half-bridge circuit is a SiC MOS transistor, which is soldered to the second substrate using soldering or other soldering processes.

10. An electronic device, characterized in that, Includes the power module as described in any one of claims 1 to 9.

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