Sensor chip, sensor, and device

Abstract

A sensor chip, a sensor and a device, the sensor chip comprises a substrate layer, a buried oxygen layer and a device layer which are sequentially stacked, part of the substrate layer is exposed from the buried oxygen layer and the device layer, and the exposed part of the substrate layer is used to connect an external power supply to make the substrate layer conduct electricity. The application utilizes the characteristics of the device substrate layer for temperature control, does not need additional elements, does not need to increase the volume of the device, and controls the cost.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to sensor chips, sensors, and devices. Background Technology

[0002] In related technologies, the heating element of the sensor chip needs to be fabricated separately on the substrate surface, which greatly increases the size and cost of the device. Summary of the Invention

[0003] The sensor chip, sensor, and device provided in the embodiments of this application are intended to at least partially solve the above-mentioned problems. The first aspect of this application provides a sensor chip, which includes a substrate layer, a buried oxide layer, and a device layer stacked sequentially. A portion of the substrate layer is exposed from the buried oxide layer and the device layer. The exposed portion of the substrate layer is used to connect an external power supply to enable the substrate layer to be energized.

[0004] Optionally, the exposed portion of the substrate layer is provided with an energized electrode, which is in electrical contact with the substrate layer to generate heat by energizing the substrate layer.

[0005] Optionally, the buried oxide layer and the device layer are exposed at both ends of the substrate layer, and energized electrodes are respectively provided at the exposed ends of the substrate layer to generate heat by energizing the substrate layer.

[0006] Optionally, the buried oxide layer and the device layer are provided with vias, the substrate layer is exposed through the vias to expose the buried oxide layer and the device layer, and the energized electrode is in electrical contact with the substrate layer through the vias.

[0007] Optionally, a functional device is disposed on the device layer, and the energized electrode is disposed on the periphery of the functional device.

[0008] Optionally, the functional device is provided with energized electrodes on both sides, and the energized electrodes are in electrical contact with the substrate layer on both sides of the functional device.

[0009] Optionally, the vias in the buried oxide layer and the vias in the device layer are aligned vertically.

[0010] Optionally, the vias in the buried oxide layer and the vias in the device layer are staggered, and a conductive connector is provided between the buried oxide layer and the device layer. A portion of the energized electrodes in the vias of the buried oxide layer and a portion of the energized electrodes in the vias of the device layer are electrically connected through the conductive connector.

[0011] Optionally, a protective layer is provided on the device layer, and notches are provided at both ends of the protective layer so that the energized electrode is led out from the substrate layer.

[0012] Optionally, the functional device includes a lead-out electrode, and the protective layer is provided with an electrode through-hole so that the lead-out electrode is led out from the electrode through-hole.

[0013] Optionally, the functional device is a piezoresistive resistor strip and stress diaphragm of a piezoresistive pressure sensor; or, the functional device is a variable capacitor electrode and stress diaphragm of a capacitive pressure sensor; or, the functional device is a micro heater and gas-sensitive membrane layer of a gas sensor; or, the functional device is a mass block, cantilever beam, and capacitive electrode of an accelerometer; or, the functional device is a drive beam, detection beam, and capacitive electrode of a gyroscope; or, the functional device is a thermistor strip and cantilever structure of a thermal sensor.

[0014] A sensor comprising a sensor chip as described in any of the preceding claims.

[0015] An apparatus comprising a sensor chip as described in any of the preceding claims, or comprising a sensor as described above.

[0016] This application utilizes the characteristics of the device substrate to conduct electricity, thereby controlling the temperature of the device. It eliminates the need for additional component fabrication, avoids increasing the device size, and controls costs.

[0017] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0020] Figure 1 This is a cross-sectional schematic diagram of a sensor chip provided in an exemplary embodiment of this disclosure;

[0021] Figure 2 This is a planar schematic diagram of a sensor chip provided in an exemplary embodiment of this disclosure;

[0022] Figure 3 This is a schematic diagram of a sensor chip being powered on according to an exemplary embodiment of this disclosure;

[0023] Figure 4This is a schematic diagram of the energized electrodes of a sensor chip provided in an exemplary embodiment of this disclosure;

[0024] Figure 5 This is a schematic diagram of the energized electrodes of another sensor chip provided in an exemplary embodiment of this disclosure;

[0025] Figure 6 This is a schematic diagram of the operation of a sensor chip provided in an exemplary embodiment of this disclosure;

[0026] Figure 7 This is a cross-sectional schematic diagram (a) of another sensor chip provided in an exemplary embodiment of this disclosure.

[0027] Figure 8 This is a cross-sectional schematic diagram (II) of another sensor chip provided in an exemplary embodiment of this disclosure. Detailed Implementation

[0028] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0029] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, features defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0030] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0031] This application provides a sensor chip, such as... Figure 1 As shown, the sensor chip includes a substrate layer 103, a buried oxide layer 102, and a device layer 101 stacked sequentially. A portion of the substrate layer 103 is exposed from the buried oxide layer 102 and the device layer 101. This exposed portion of the substrate layer 103 is used to connect an external power supply, allowing the substrate layer 103 to generate heat when energized. The substrate layer 103 can be made of low-resistivity single-crystal silicon material with a thickness of 50–500 μm and a bulk resistivity range of 1–100 Ω·cm, ensuring stable thermal power generation (typically 10–500 mW) at a low drive voltage of 3–5 V. The buried oxide layer 102 is a silicon dioxide layer with a thickness of 1–3 μm. The device layer 101 is the top silicon layer in the SOI structure with a thickness of 0.1–100 μm, on which piezoresistive, capacitive, or other types of functional devices are integrated. Part of the substrate layer 103 exposed from the buried oxide layer 102 and the device layer 101 can be directly exposed to connect electrodes, or indirectly exposed after electrode connection; both should be included within the scope of protection of this application. Furthermore, the exposed portion of the substrate layer 103 is located in the scribe line region at the chip edge, preserving a bare silicon area through wafer-level processing. This area is not covered with any metal or passivation layer, ensuring that the external power supply can directly form ohmic contact with the silicon substrate. Since the heating source (substrate layer 103) and the sensing area (device layer 101) are separated only by an ultra-thin buried oxide layer 102, the heat conduction path length is less than 3 μm, the thermal response time is negligible, and the temperature gradient can be controlled within ±0.1°C, achieving uniform heating. By combining a PID control circuit, the voltage applied to the substrate 103 is dynamically adjusted based on the real-time feedback of temperature changes through the resistance of the Wheatstone bridge in the functional device. This stabilizes the temperature of the device layer 101 at a set value (e.g., 100°C ± 0.5°C), thereby eliminating the influence of ambient temperature drift on output signals such as pressure and acceleration, and improving the long-term stability and accuracy of the sensor. This structure achieves a temperature compensation accuracy better than ±0.3°C within an operating temperature range of -40°C to 125°C, and reduces sensor output drift by more than 95%. In some embodiments, the substrate 103 can also be a silicon-based PN junction structure substrate. By energizing it, a Peltier effect is generated, achieving energized cooling of the substrate 103, thereby realizing temperature control of the device.

[0032] In some embodiments, Figure 1The diagram shows a cross-sectional view of a self-heating piezoresistive pressure sensor based on an SOI structure. The overall structure consists of SOI layers (101, 102, 103) and a glass cover plate 104. The SOI structure includes a device layer 101, a buried oxide layer 102, and a substrate layer 103. The SOI device layer 101 is mainly used to fabricate a Wheatstone bridge structure, and its thickness can be selected from 0.1 to 100 μm. In the diagram, the piezoresistor 105 is fabricated on the device layer by etching. That is, a specific area of ​​the SOI device layer 101 is etched through until the SOI buried oxide layer 102 stops, leaving a narrow line structure as the piezoresistor 105. The remaining structure is a silicon wire 106, used to connect the piezoresistors 105 and introduce and extract electrical signals. Optionally, the piezoresistor 105 can also be fabricated by ion implantation, by doping a specific area on the SOI device layer 101 to form a heavily doped piezoresistive region. The SOI buried oxide layer 102 is a uniformly fabricated layer of silicon oxide between the device layer 101 and the substrate layer 103, with a thickness of 1~3 μm, used for electrical isolation between the device layer 101 and the substrate layer 103. The thickness of the SOI substrate layer 103 can be selected from 50~500 μm, and a cavity is formed in its central region to form a pressure-sensitive film 107. The cavity can be fabricated by dry etching or wet etching. Under external pressure, the pressure-sensitive film 107 will bend upward, thereby generating stress on the surface of the film proportional to the pressure to be measured. The piezoresistor 105 generates a resistance change under this stress, which is converted into a pressure output through a Wheatstone bridge, thereby realizing pressure measurement.

[0033] In some embodiments, in order to protect the varistor 105 and enable it to be better used in harsh environments and to provide a vacuum reference for pressure measurement, a cover plate needs to be bonded to the top of the SOI. The cover plate can be made of glass or silicon. Figure 1 The image shows a glass cover plate 104. A vacuum reference cavity 108 is formed in the central area of ​​the glass cover plate 104. Its depth can be selected from 5 to 50 μm, and its side length is the same as that of the pressure-sensitive membrane 107. It can be fabricated using methods such as HF etching, etching, and sandblasting. The vacuum reference cavity 108 provides vacuum protection for the varistor 105, protecting it from external moisture, impurities, and charges. Electrode through-holes are also formed on the glass cover plate 104 to lead out electrical signals. These electrode through-holes are divided into internal electrode through-holes 109 and external electrode through-holes (i.e., through-holes for the energized electrodes 111) 110. Electrode pads (i.e., pads for the energized electrodes) 111 are formed inside the through-holes, and can be single-layer or multi-layer metals such as Al, Ti / Pt / Au. The internal electrode via 109 is fabricated on the SOI device layer 101 and connected to the Wheatstone bridge, while the external electrode via 110 is fabricated on the SOI substrate layer 103 through the SOI buried oxide layer 102 and is directly connected to the substrate layer. Figure 2The diagram shows the front view of the sensor. There are four internal electrode vias 109, which are located at the center of the chip, and two external electrode vias 110, which are located at the edge of the chip.

[0034] Figure 6 The diagram shows the temperature detection method of a Wheatstone bridge. The four bridge arm resistors, 501, are connected end-to-end to form the Wheatstone bridge structure. The bridge arm resistors 501 are... Figure 1The device shown is a layered varistor 105, with all four resistors having the same initial resistance. Under external pressure, the resistance of two opposite bridge arms increases, while the resistance of the other two bridge arms decreases. If a supply voltage 503 is applied to the two terminals of the bridge, an output voltage proportional to the change in resistance of the bridge arms will be generated at the other two terminals, thus achieving pressure measurement. Ideally, the absolute values ​​of the resistance changes of the four resistors are equal; therefore, the total resistance of the two resistors in the left and right bridge arms connected in series remains constant, and the total resistance of the Wheatstone bridge is essentially unaffected by pressure. However, when the temperature changes, the resistance changes of the four bridge arm resistors 501 are the same. For example, when the temperature rises, the resistance of all bridge arm resistors 501 increases, thus increasing the total resistance of the Wheatstone bridge. Therefore, by connecting a fixed resistor 502 in series outside the Wheatstone bridge, under the action of the supply voltage 503, the voltage 504 across the Wheatstone bridge will change with temperature, unaffected by pressure. By measuring this voltage, the temperature value of the bridge arm resistance 501, i.e., the piezoresistive resistor 505 on the device layer, can be determined. A PID circuit is used to control the sensor temperature. The voltage 504 across the bridge serves as the input signal to the PID circuit, while the voltage signal applied to the lead electrode 201, sidewall electrode 301, or exposed electrode 401 is the output signal. The control method may include: Step 601: System startup, chip power-on, sensor starts working; Step 602: Chip substrate layer begins heating, which may last from tens of milliseconds to several seconds; Step 603: The PID circuit checks whether the voltage 504 across the bridge is greater than the set threshold voltage. In conventional piezoresistive pressure sensor designs (p-type silicon, high doping concentration), the resistance of the Wheatstone bridge will increase with increasing temperature, therefore the voltage 504 across the bridge will also increase accordingly. When the temperature rises to the set temperature, the voltage 504 across the bridge will also reach a certain threshold (this threshold needs to be calibrated in advance). If the PID circuit detects that the current voltage is lower than the threshold voltage, it returns to step 602 and continues heating the chip's substrate. If the current voltage is higher than the threshold voltage, it proceeds to step 604; Step 604: Stop applying voltage to the chip's substrate, and heating stops. Then, it returns to step 603 to continue the judgment. Through the control of the PID circuit, the following functions can be achieved: heating is performed when the required temperature is lower than the set value, and heating is stopped when the required temperature is higher than the set value, thereby stabilizing the temperature at the set value. Optionally, the voltage can also be applied to the SOI substrate 103 in the form of a square wave, and heating is controlled by the duty cycle. When the temperature is lower than the set value, the duty cycle is high, and when the temperature is higher than the set value, the duty cycle is low; the voltage can also be controlled by slow changes rather than instantaneous switching, for example, it can start to decrease at the set temperature of −5℃ and drop to 0V at the set temperature of +5℃.In some embodiments, an energized electrode is provided on the exposed portion of the substrate 103, and the energized electrode is in electrical contact with the substrate 103 to energize and heat the substrate 103. The energized electrode 111 may be... Figure 1 The electrode pad 111 described herein can employ a titanium / platinum / gold (Ti / Pt / Au) multilayer structure, directly deposited on the exposed area of ​​the substrate layer 103 via magnetron sputtering and lift-off processes. The titanium layer is 50 nm thick to enhance adhesion to silicon, the platinum layer is 200 nm thick to provide stable ohmic contact, and the gold layer is 1 μm thick to reduce contact resistance and improve conductivity. This electrode pad forms a low-impedance interface with the substrate layer 103, with a contact resistance of less than 10 mΩ, ensuring uniform current injection. During chip packaging, the energized electrode 111 is connected to the external driving circuit via gold wire bonding, avoiding the use of lead frames or BGA solder balls to directly press against the silicon substrate and preventing mechanical stress from being introduced into the sensing area. This structure ensures that the heating current path is entirely within the chip, eliminating the need for external heating elements and achieving "self-heating without additional components," significantly reducing chip area footprint and making it suitable for miniaturized packaging requirements such as LGA-8 and WLCSP.

[0035] In some embodiments, see Figure 5 The substrate layer 103 exposes the buried oxide layer 102 and the device layer 101 at both ends. Current-carrying electrodes 111 are respectively provided at the exposed ends of the substrate layer 103 to generate heat. In this preferred embodiment, a 100–200 μm wide exposed area is reserved at each end of the substrate layer 103 along the long axis of the chip, and independent current-carrying electrodes 111 are provided thereon, forming a symmetrical current injection structure. Current flows in from one electrode, is laterally conducted through the substrate layer 103, and flows out from the other electrode, forming a uniform lateral heat flow field. This structure ensures that the heating area of ​​the substrate layer 103 covers the entire area directly below the device layer 101, avoiding temperature gradients caused by single-point heating. In pressure sensor applications, the stress diaphragm is located in the central region of the device layer 101, directly below the heating area of ​​the substrate layer 103, with a centrally symmetrical temperature distribution. This ensures that the thermal environment of the four piezoresistive resistors in the Wheatstone bridge is completely consistent, eliminating zero-point drift caused by local temperature differences. This structure is particularly suitable for high-precision differential output sensors, such as those used in automotive tire pressure monitoring systems (TPMS) where temperature stability requirements are ±0.1%FS.

[0036] In some embodiments, vias are provided in the buried oxide layer 102 and the device layer 101, and the substrate layer 103 is exposed through the vias. The energized electrode 111 is electrically contacted with the substrate layer 103 through the vias. The vias are formed using a deep reactive ion etching (DRIE) process, penetrating through the buried oxide layer 102 and the device layer 101, with a diameter of 5–200 μm and a depth equal to the sum of the thicknesses of the buried oxide layer 102 and the device layer 101. The inner walls of the vias are plasma-treated and then deposited with TiN as a barrier layer to prevent metal diffusion into the silicon, followed by filling with tungsten (W) or copper (Cu) as conductive channels. The energized electrode 111 directly contacts the substrate layer 103 through the bottom of the via, achieving vertical interconnection. This structure allows the energized electrode 111 to be placed in a non-sensitive area above the device layer 101, avoiding electrical interference between the electrode metal layer and the piezoresistive resistor strip or capacitive electrode. In capacitive pressure sensors, the energized electrode 111 can be placed around the sensitive electrode to ensure that the electric field between the electrodes is not affected by the heating current. The through-hole density is designed according to the heating power requirements, typically 2–5 through-holes per square millimeter, ensuring that the current density is below 5 × 10⁻⁶. 5 A / cm², to prevent electromigration failure.

[0037] In some embodiments, a functional device is disposed on the device layer 101, and an energized electrode 111 is disposed on the periphery of the functional device. See also Figure 2 The functional components can be a stress diaphragm and four piezoresistive resistor strips of a piezoresistive pressure sensor, arranged in a cross shape at the center of device layer 101. The energized electrodes 111 are located on the outer sides of the four corners of the stress diaphragm, at a distance ≥30 μm from the diaphragm edge, ensuring that the heating current path does not pass through the sensitive stress area and avoiding mechanical stress interference caused by current injection. The energized electrodes 111 are strip-shaped, extending along the chip edge, forming a "ring-like" arrangement with the functional components, so that the heating area of ​​substrate layer 103 completely covers the functional components directly below, creating a "thermal cage" effect. During temperature control, because the heating source and sensing area share the same heat conduction path, the temperature feedback response speed is improved by more than 40%, and the PID control loop bandwidth can reach 10 Hz, meeting the rapid temperature compensation requirements in dynamic pressure measurement (such as engine knock detection).

[0038] In some embodiments, see Figures 3 to 5The functional device has energized electrodes 111 on both sides, which are electrically connected to the substrate layers 103 on both sides of the functional device. In this embodiment, the functional device is a mass block and a detection beam of a long strip cantilever beam accelerometer, arranged along the length of the chip. A pair of energized electrodes 111 are respectively provided on the outer sides of both ends of the mass block, connected to the two ends of the substrate layer 103. The current flows laterally along the substrate layer 103, and the heating area covers the entire area under the cantilever beam, so that the beam temperature rises uniformly and avoids zero-bias drift caused by uneven thermal expansion. This structure is particularly suitable for high-g impact environments (such as automotive airbag trigger sensors). Within the operating temperature range of -40°C to 125°C, the change in the thermal expansion coefficient of the cantilever beam is compensated by constant temperature control, and the output sensitivity fluctuation is less than ±0.3%. The energized electrodes 111 adopt a segmented design, and the voltage of the two electrodes can be independently controlled to achieve local heating compensation, such as applying a slightly higher voltage to the beam end in a low-temperature environment to counteract the edge heat dissipation effect.

[0039] In some embodiments, see Figure 3 , Figure 4 The vias in the buried oxide layer 102 and the device layer 101 are vertically aligned. This vertical alignment simplifies the manufacturing process, requiring only one DRIE etching to penetrate both layers without alignment error compensation. The metal (such as tungsten) filling the vias forms continuous vertical conductive pillars, through which the energized electrode 111 achieves a low-resistance connection with the substrate layer 103, with a stable contact resistance of 5–8 mΩ. This structure facilitates direct probe contact with the top electrode of the via during wafer-level testing, enabling online screening of heating functions and improving yield. After packaging, this structure can withstand 1000 thermal cycles (-40°C to 150°C) while maintaining a contact resistance change rate of less than 2%, meeting the automotive-grade AEC-Q100 standard.

[0040] In some embodiments, the vias of the buried oxide layer 102 and the vias of the device layer 101 are offset, and a conductive connector is provided between the buried oxide layer 102 and the device layer 101. A portion of the conductive electrodes 111 in the vias of the buried oxide layer 102 and a portion of the conductive electrodes 111 in the vias of the device layer 101 are electrically connected through the conductive connector. In this embodiment, the vias of the buried oxide layer 102 are located at an offset position of 5–15 μm from the vias of the device layer 101, forming a zigzag current path. The vias of the buried oxide layer 102 are filled with copper, and the vias of the device layer 101 are filled with aluminum. Electrical connection is achieved between the two through a sputtered titanium-tungsten alloy (TiW) conductive connector, which has a thickness of 100 nm and a width of 3 μm, forming a low-resistance bridging structure. This offset design avoids the formation of a metal shadow above the device layer 101 by the vias, preventing the obstruction of the pattern definition of functional devices (such as capacitor electrodes) during photolithography or metal deposition. In gas sensor applications, the gas-sensitive film layer is located at the center of device layer 101. The staggered layout of the vias allows the heating current path to bypass the gas-sensitive area, preventing metal ion diffusion and contamination of the sensitive film, thus improving sensor lifespan. When operating at high temperatures (>150°C), the thermal expansion coefficient of the conductive connectors matches that of silicon, eliminating the risk of delamination.

[0041] In some embodiments, a protective layer 104 is provided on the device layer 101, with notches at both ends to allow the energized electrode 111 to be led out from the substrate layer 103. The protective layer 104 can be a composite passivation layer of silicon dioxide and silicon nitride (SiO2 / Si3N4), with a total thickness of 0.5–1.5 μm, used to isolate environmental moisture and contaminants. See also Figure 5 A rectangular notch, 50–100 μm wide and penetrating to the substrate layer 103, is formed along the chip edge at both ends of the protective layer, directly exposing the energized electrode 111 to the package interface without requiring an additional metal wiring layer. This structure avoids adding metal traces above the device layer 101, saving wiring space and reducing parasitic capacitance. In MEMS microphone applications, this structure positions the energized electrode 111 outside the acoustic cavity, ensuring that sound waves do not affect the entry of the diaphragm and maintaining sensitivity. The notch edges are passivated to prevent edge electric field concentration from causing breakdown. See also Figure 1 , Figure 3 , Figure 5 In some embodiments, the protective layer 104 can be a glass cover plate, and through-holes can be formed in the cover plate, the device layer, and the buried oxide layer. The conductive electrodes connect to the substrate layer through these through-holes. Specifically, the conductive electrodes can be electrode pads with conductive leads, or they can be... Figure 4 The metal sidewall electrodes or metal perforations shown are not specifically limited herein, but should all be included within the scope of protection of this application.

[0042] In some embodiments, the functional device includes lead-out electrodes, and electrode vias 109 are provided on the protective layer 104 to allow the lead-out electrodes to be led out from the electrode vias 109. The functional device is four piezoresistive resistor strips of a piezoresistive pressure sensor, with their two ends connected to aluminum lead-out electrodes respectively. The lead-out electrodes are located on the surface of the device layer 101 and are formed by photolithography and etching. Electrode vias 109 with a diameter of 20–40 μm are formed on the protective layer 104 corresponding to each lead-out electrode position. The vias are filled with tungsten or gold to form vertical interconnect channels. The lead-out electrodes are connected to external pads through these channels to achieve signal output. This structure is independent of the heating electrode of the substrate layer 103, avoiding the signal line and heating current sharing the same path and eliminating crosstalk. In high dynamic pressure measurement (such as transient monitoring of hydraulic systems), the signal bandwidth can reach 10 kHz, and the signal-to-noise ratio is higher than 60 dB, thanks to the physical isolation between heating and signal paths.

[0043] In some embodiments, Figure 3 The diagram illustrates the principle of self-heating operation of the SOI substrate. Lead electrodes (i.e., leads of the energized electrodes) 201 are bonded to the electrode pads 110 located on the substrate 103. The substrate 103 is silicon with a certain doping concentration to ensure its conductivity. 10 ~10 20 The voltage can be between cm⁻³. A voltage is applied to the substrate through the lead electrode 201, causing a current 202 to flow through the pressure-sensitive membrane 107 in the substrate. This substrate current 202 directly heats the pressure-sensitive membrane 107. By controlling the applied voltage or switching it on and off, the heating temperature can be controlled to a certain value. To completely isolate the SOI substrate 103 from the outside environment, an additional silicon oxide layer needs to be fabricated on the lower part of the substrate 103. As shown in the figure, the heated area is mainly the pressure-sensitive membrane 107, separated from the temperature-controlled varistor 105 by only a few micrometers of SOI buried oxide layer 102. Therefore, it can be considered that there is essentially no temperature gradient between the heat source and the target area, maximizing the heating efficiency. Furthermore, when measuring gas pressure, the pressure-sensitive membrane 107 and the varistor 105 are above a vacuum chamber 108, and the gas medium to be measured is below. The heating area is a suspended structure, greatly limiting heat dissipation to the upper and lower areas, thereby further improving the heating efficiency. Alternatively, the methods of outputting electrical signals are not limited to... Figure 3 The lead shown leads to one type, Figure 4The diagram illustrates the method for extracting electrical signals through sidewall metallization. Metal electrodes are fabricated on the sidewalls of the electrode via 109 using sputtering, thereby extracting electrical signals from the SOI device layer 101 and the SOI substrate layer 103. If silicon is used as the cover material, the entire cover needs to be thermally oxidized before sputtering the sidewall electrodes 301 to create a uniform layer of silicon oxide for insulation. After sputtering the sidewall electrodes 301, the electrodes connected to the SOI substrate layer 103 will inevitably connect to the SOI device layer 101. Therefore, to prevent short circuits between the SOI device layer 101 and the SOI substrate layer 103, an isolation trench 302 needs to be etched around the device layer silicon connected to the substrate layer electrodes to physically isolate this small ring of device layer silicon from the rest of the device layer silicon. Figure 5 The diagram shows a signal extraction method using exposed electrodes. The cover plate 104 has a smaller area than the SOI substrate, with gaps left at the left and right edges for signal extraction.

[0044] In some embodiments, see Figure 7 , Figure 8The functional components can be piezoresistive resistor strips and stress diaphragms of a piezoresistive pressure sensor; or, variable capacitor electrodes and stress diaphragms of a capacitive pressure sensor; or, micro heaters and gas-sensitive membranes of a gas sensor; or, mass blocks, cantilever beams, and capacitive electrodes of an accelerometer; or, drive beams, detection beams, and capacitive electrodes of a gyroscope; or, thermistor strips and cantilever structures of a thermal sensor. In a piezoresistive pressure sensor, the stress diaphragm is square with a side length of 1.5 mm. The piezoresistive resistor strips are arranged along the

[110] crystal orientation, and its temperature coefficient of resistance is +2.5×10⁻³ / °C. The temperature of the diaphragm is stabilized by constant temperature control of the substrate layer 103, eliminating zero-point and sensitivity drift caused by temperature drift. In a capacitive pressure sensor, the variable capacitor consists of fixed electrodes and diaphragm electrodes. The diaphragm thickness is 3 μm. Heating of the substrate layer 103 compensates for the thermal expansion of the diaphragm. The capacitance change is only caused by pressure, and the temperature drift suppression rate is over 95%. In gas sensors, a gas-sensitive film (such as SnO2) is deposited on the surface of device layer 101. Heating the substrate layer 103 maintains the film temperature at 300°C (typical operating temperature), achieving high sensitivity and rapid recovery. Heating power consumption is reduced by 60% compared to traditional independent microheaters. In accelerometers, the cantilever beam is 200 μm long, and the mass block is 50 × 50 μm². Heating the substrate layer 103 ensures uniform thermal stress in the beam, resulting in zero-point stability better than ±0.1 mg. In gyroscopes, the drive beam and detection beam have a comb-like structure. Heating the substrate layer 103 reduces the temperature coefficient of the resonant frequency from ±50 ppm / °C to ±2 ppm / °C, improving angular velocity measurement accuracy. In thermal sensors, the thermistor strip is made of polycrystalline silicon. The cantilever structure enhances thermal coupling between the thermally sensitive area and the substrate layer 103, shortening the response time to 20 ms, suitable for rapid temperature gradient detection.

[0045] This application also provides a sensor, which includes the sensor chip as described in any of the foregoing embodiments. This sensor is an integrated MEMS multi-parameter sensing module, comprising the aforementioned sensor chip, a temperature-compensated PID control circuit, a signal conditioning circuit, and a digital interface. The chip is packaged on a ceramic substrate, using an airtight vacuum chamber with an internal pressure below 1 Pa to reduce convective heat transfer interference. An external drive circuit connects the energized electrode 111 to the signal lead electrode via gold wires to achieve constant temperature control and signal output. This sensor is applied to the thermal management system of new energy vehicle batteries, real-time monitoring of individual cell temperature and pressure, with a temperature control accuracy of ±0.3°C and a pressure measurement accuracy of ±0.1%FS, meeting the ISO 26262 functional safety level ASIL-B requirements. Under extreme environments (-40°C to 125°C), after 10,000 hours of continuous operation, the output drift is less than 0.5%, significantly better than traditional discrete heating + sensing solutions. In addition, the SOI-based substrate heating method is also suitable for other types of sensors, such as gas, accelerometer, gyroscope, and optical sensors. Figure 7 The diagram shows a gas sensor structure based on substrate heating. Electrode 704 heats the silicon substrate 701 through a via in silicon dioxide 702. The resistance of the gas-sensitive material 703 changes with the concentration of the gas to be detected, thus enabling gas detection. It should be noted that the gas sensor can have part or all of the SOI device layer removed, but this does not affect the protection of this patent. Figure 8 The diagram shows an accelerometer structure based on substrate heating. The electrodes are also heated by the silicon substrate to keep the entire chip at a constant temperature. The mass block 801 deforms with acceleration, thereby causing a change in the resistance of the doped resistor 802.

[0046] This application also provides a device that includes a sensor chip as described in any of the foregoing embodiments, or includes the sensors described in the foregoing embodiments. This device is an environmental perception unit in an intelligent driving domain controller, integrating multiple of the aforementioned sensor chips for monitoring cabin pressure changes, battery pack thermal distribution, air humidity, and gas composition. The sensor chips are directly mounted on the PCB board, eliminating the need for external heating elements, reducing overall power consumption by 35% and size by 40%. In L3+ autonomous driving systems, this device achieves multi-sensor data fusion, eliminating interference from ambient temperature on the lidar-assisted pressure sensor and infrared gas sensor through constant temperature compensation, thus improving perception reliability. In industrial robot joints, the sensor chip is embedded in the motor housing to monitor internal temperature and pressure changes in real time, enabling predictive maintenance. The device outputs compensated data via a CAN FD bus, meeting functional safety and EMC requirements, and has passed AEC-Q100 Grade 1 certification.

[0047] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0048] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A sensor chip, characterized in that, The sensor chip includes a substrate layer, a buried oxide layer, and a device layer stacked sequentially. A portion of the substrate layer is exposed from the buried oxide layer and the device layer. The exposed portion of the substrate layer is used to connect an external power source to enable the substrate layer to be energized.

2. The sensor chip according to claim 1, characterized in that, The exposed portion of the substrate is provided with an energized electrode, which is in electrical contact with the substrate to generate heat by energizing the substrate.

3. The sensor chip according to claim 1, characterized in that, The substrate layer is configured to expose the buried oxide layer and the device layer at both ends, and the exposed ends of the substrate layer are respectively provided with energized electrodes to generate heat by energizing the substrate layer.

4. The sensor chip according to claim 2, characterized in that, The buried oxide layer and the device layer are provided with vias, the substrate layer is exposed to the buried oxide layer and the device layer through the vias, and the energized electrode is in electrical contact with the substrate layer through the vias.

5. The sensor chip according to claim 3 or 4, characterized in that, Functional devices are disposed on the device layer, and the energized electrodes are disposed on the periphery of the functional devices.

6. The sensor chip according to claim 5, characterized in that, The functional device is provided with energized electrodes on both sides, and the energized electrodes are in electrical contact with the substrate layer on both sides of the functional device.

7. The sensor chip according to claim 4, characterized in that, The through-holes in the buried oxide layer and the through-holes in the device layer are aligned vertically.

8. The sensor chip according to claim 4, characterized in that, The through-holes in the buried oxide layer and the through-holes in the device layer are staggered. A conductive connector is provided between the buried oxide layer and the device layer. A portion of the energized electrodes in the through-holes of the buried oxide layer and a portion of the energized electrodes in the through-holes of the device layer are electrically connected through the conductive connector.

9. The sensor chip according to claim 5, characterized in that, A protective layer is provided on the device layer, and notches are provided at both ends of the protective layer so that the energized electrode can be led out from the substrate layer.

10. The sensor chip according to claim 9, characterized in that, The functional device includes a lead-out electrode, and the protective layer is provided with an electrode through hole so that the lead-out electrode is led out from the electrode through hole.

11. The sensor chip according to claim 5, characterized in that, The functional device is a piezoresistive resistor strip and stress diaphragm of a piezoresistive pressure sensor; or, the functional device is a variable capacitor electrode and stress diaphragm of a capacitive pressure sensor; or, the functional device is a micro heater and gas-sensitive membrane layer of a gas sensor; or, the functional device is a mass block, cantilever beam, and capacitive electrode of an accelerometer; or, the functional device is a drive beam, detection beam, and capacitive electrode of a gyroscope; or, the functional device is a thermistor strip and cantilever structure of a thermal sensor.

12. A sensor, characterized in that, The sensor includes the sensor chip as described in any one of claims 1 to 11.

13. A device, characterized in that, The device includes a sensor chip as described in any one of claims 1 to 11, or includes a sensor as described in claim 12.

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