Circuit protection device with PTC thermistor layer and fuse element

Abstract

Circuit protection device (160, 170), comprising; a ceramic positive temperature coefficient (“CPTC”) thermistor layer (130); a locking element (162, 172) supported by the CPTC thermistor layer (130), wherein the fuse element (162, 172) has a lower resistance than the CPTC thermistor layer (130); and first and second cables (164, 166) are electrically connected in parallel to the fuse element (162, 172) and the CPTC thermistor layer (130), so that current (i) initially flows through the fuse element (162, 172) and the CPTC thermistor layer (130) under normal operation and (ii) after opening the safety element (162, 172) under normal operation flows through the CPTC thermistor layer (130).

Description

background

[0001] The present invention relates generally to an electrical circuit protection system and in particular to an overcurrent protection system.

[0002] Application layer fuses for printed circuit boards (PCBs) often feature resettable fuse types. This is because PCBs are frequently densely populated, making it impossible to assemble a complete PCB after a blown non-resettable fuse. Replacing a blown non-resettable fuse is also impossible. The PCB may be concealed within a machine, automobile, computer, etc., in such a way that it is virtually inaccessible. Even if accessible, the PCB may be located within a device, such as an individual's computer, mobile phone, or handheld device, making maintenance difficult and / or prohibitively expensive.

[0003] A well-known resettable fuse suitable for PCB applications is called a positive temperature coefficient (PTC) device. PTC materials are based on a physical property common to many conductive materials: their resistance increases with temperature. Crystalline polymers made electrically conductive by dispersing conductive fillers exhibit PTC behavior. These polymers generally include polyolefins such as polyethylene, polypropylene, and ethylene / propylene copolymers. Certain doped ceramics, such as barium titanate, also exhibit PTC behavior.

[0004] The conductive fillers cause the resistance of the PTC thermistor material to increase as its temperature rises. Below a certain temperature, the PTC thermistor material exhibits a relatively low, constant resistance. However, if the temperature of the PTC thermistor material rises above this point, the resistance increases sharply with even a small temperature increase.

[0005] If the load protected by a PTC thermistor material is short-circuited, the current flowing through the thermistor material increases and the temperature of the PTC thermistor material rises (due to the aforementioned heating i). 2The temperature (R) rises rapidly to a critical temperature. At this critical temperature, a large amount of current is dissipated by the PTC thermistor material, resulting in a rate at which the material generates heat exceeding its rate of heat dissipation to the environment. This heat dissipation can only occur for a short period (e.g., a fraction of a second). However, the increased current dissipation raises the temperature and resistance of the PTC thermistor material, limiting the current in the circuit to a relatively low value. The PTC thermistor material thus acts as a kind of fuse.

[0006] When the current in the circuit is switched off or the condition responsible for the short circuit is removed, the PTC thermistor material cools down to its normal operating, low resistance state below its critical temperature. This results in a resettable circuit protection or fuse for overcurrent.

[0007] Although PTC thermistor materials operate at lower resistances under normal conditions, their typical operating resistances are higher than those of other fuse types, such as non-resettable metallic fuses. This higher operating resistance results in a greater voltage drop across the PTC thermistor material than for similarly designed non-resettable metallic fuses. This voltage drop and power dissipation are becoming increasingly important for circuit designers seeking to maximize both the driving performance of a given circuit and battery life.

[0008] Patent documents JP H10-94 158 A and JP 2002-369 372 A disclose the use of non-resettable fuses and PTC thermistors in parallel.

[0009] The inventor is also known for the word mark Polyfuse®, which is classified in Nice Classification 09.

[0010] Therefore, there is a need for an improved circuit protection device at the PCB level. Summary

[0011] The present invention relates to a circuit protection device as described in the independent claim. Advantageous embodiments are described in the dependent claims.

[0012] The circuit protection device according to the invention comprises a ceramic positive temperature coefficient (“CPTC”) thermistor layer, a fuse element which is carried by the CPTC thermistor layer, wherein the fuse element has a lower resistance than the CPTC thermistor layer, and first and second cables which are electrically connected in parallel to the fuse element and the CPTC thermistor layer, so that current initially flows through the fuse element and the CPTC thermistor layer under normal operation and, after opening the fuse element, flows through the CPTC thermistor layer under normal operation.

[0013] It is preferred that the locking element is a surface-mounted locking element applied to the CPTC thermistor layer.

[0014] Furthermore, it is preferred that the locking element is a wire element attached to electrodes that are applied to the CPTC thermistor layer. Description of the characters Fig. Figure 1 shows a top view of an embodiment of an integrated resettable and non-resettable overcurrent protection device of the present disclosure. Fig. Figure 2A shows a side-section view of the integrated resettable and non-resettable overcurrent protection device along line AA of Fig. Figure 1 shows the connections extending along the side of the device. Fig. 2B shows a side-section view of the integrated resettable and non-resettable overcurrent protection device along line BB of Fig. Figure 1 shows the connections that do not extend along the side of the device on the section. Fig. Figure 3 shows a view of the integrated resettable and non-resettable overcurrent protection device of Fig. 1 from the bottom. Fig. Figure 4 presents a schematic electrical diagram showing an exemplary equivalent resistance for the parallel resettable and non-resettable components of the device of Fig. 1 shows. Fig. Figure 5 represents a time-current curve obtained during testing of a sample of the integrated resettable and non-resettable overcurrent protection device of Fig. 1 was received. Fig. Figure 6 represents a voltage drop compared to a graphical representation of a current that occurred during testing of various samples of the integrated resettable and non-resettable overcurrent protection device of Fig. 1 was received. Fig. Figure 7 shows a side-section view of an alternative integrated resettable and non-resettable overcurrent protection device of the present disclosure. Fig. Figure 8 shows a side-cut view of an embodiment of an integrated resettable and non-resettable overcurrent protection device of the present disclosure, which uses a ceramic resettable overcurrent protection material. Fig. Figure 9 shows a side-cut view of another embodiment of an integrated resettable and non-resettable overcurrent protection device of the present disclosure, which uses a ceramic resettable overcurrent protection material. Fig. Figure 10 shows a side-cut view of another embodiment of an integrated resettable and non-resettable overcurrent protection device of the present disclosure, which uses a ceramic resettable overcurrent protection material. Fig. Figure 11 shows a side-cut view of yet another embodiment of an integrated resettable and non-resettable overcurrent protection device of the present disclosure, which uses a ceramic resettable overcurrent protection material. Fig. Figure 12 shows a side view of any embodiment herein, showing a configuration mounted on a surface. Fig. Figure 13 presents a schematic electrical view of a telecommunications circuit that uses a pair of integrated resettable overcurrent protection devices of the present disclosure. Fig. Figure 14 presents a schematic electrical view of a data bus that uses an integrated resettable overcurrent protection device of the present disclosure. Fig. Figure 15 presents a schematic electrical view of a battery pack circuit that uses an integrated resettable overcurrent protection device of the present disclosure. Detailed description

[0015] In the drawings and especially in Fig. 1, Fig. 2A, Fig. 2B and Fig. Section 3 now presents Device 10 as an embodiment of an integrated resettable and non-resettable circuit safeguard device and the associated method of the present disclosure. Device 10 comprises an upper insulating substrate 12 and a lower insulating substrate 14 (here collectively referred to as insulating substrates 12, or generally individually as insulating substrates). In one embodiment, the insulating substrates 12 are made of the same material, such as an FR-4 material or a polyimide. Substrate 12 can, for example, be provided with a copper coating on both surfaces of the FR-4 material. In one embodiment, the copper is then etched away using standard photolithographic processes to form various electrode patterns.The copper plating can, for example, be etched away to form an upper copper layer 20a, which forms a base layer of terminals 36a and 36b.

[0016] As in Fig. 2A and Fig. As shown in Figure 2B, the copper layer 16 is etched away from the insulating substrate 12 along the right side of device 10. In this way, electrode 16 is not in direct contact with a terminal formed on the right side of device 10. A similar third copper layer, or electrode 18, is etched onto the upper surface of the insulating substrate 14. Here, electrode 18 is in contact with a terminal formed on the right side of device 10, but is not in direct electrical contact with a similar terminal formed on the left side of device 10. A fourth copper layer 20b is photo-etched from the lower side of the insulating substrate 14 using standard photolithographic processes. As shown in the bottom view in Figure 2B, the copper layer 16 is photo-etched from the lower side of the insulating substrate 14 using standard photolithographic processes. Fig. As shown in Figure 3 of device 10, the copper layer 20b is etched into a specific shape to form the metallic locking element of the device 10. The lower copper layer 20b also extends to form a bottom-side base layer of terminals 36a and 36b.

[0017] The insulating substrates 12 and 14, which have etched copper layers 16, 18 and 20a and 20b respectively, are inserted over a positive temperature coefficient (“PTC”) layer 30. A suitable PTC thermistor material for a PTC thermistor layer is provided in a Polyfuse® LF1206L device, which is marketed by the ultimate signatory of this disclosure. This material is polymer-based. Ceramic configurations are described below.

[0018] In one embodiment, the PTC thermistor layer 30 is initially laminated between two large insulating substrates. The electrodes 16, 18, 20a, and 20b are pre-formed on the large insulating substrates prior to their arrangement, enabling the formation of numerous devices 10 from a single arrangement. The device 10 is then separated from the arrangement of insulating substrates and attached to a PTC thermistor layer using known separation or singulation techniques.

[0019] Fig. Figure 3 shows that in one embodiment, the metallic locking element 24 is formed on a lower surface of the insulating substrate 14. The copper layer 20b is photo-etched into a specific shape to form the locking element. The etched copper layer 20b comprises field areas 22a and 22b, which extend to element 24. The field areas 22a and 22b also extend to more extensive terminal areas 26a and 26b of the copper layer 20b, which is finally plated along the upper copper layer 20a to form the terminals 36a and 36b. The base metal for the locking element 24 is therefore copper in one embodiment.

[0020] While the device 10 is generally described as having photo-etched copper electrodes, it should be clear that the electrodes 16, 18, 20a, and 20b can be made of alternative metals and applied by a different process, such as electroplating, sputtering, printing, or laminating. The insulating substrates 12 can be made of a polyimide such as FR-4 material. In any case, the electrodes 16, 18, 20a, and 20b can consist of one or more metals, such as silver, copper, nickel, tin, and alloys thereof, applied to the surface of the polyimide by any of the aforementioned methods.

[0021] Element 24 has a height h, a length l, and a width dimensioned by x to create a desirable opening characteristic of the locking element 24. For example, the height h of element 24 can be thinner than the height of fields 22a and 22b and the connection areas 26a and 26b. In one embodiment, the thinned height h of element 24 is formed by a peeling or additional etching process. Fig. The element 24 shown in Figure 3 is depicted as having a general straight length l. It should be clear that element 24 can alternatively be jagged or curved, for example, coiled or serpentine, in order to increase the distance l as required to create a desirable opening property for element 24.

[0022] Furthermore, one or more dissimilar metallic points 28, often referred to as a Metcalf point, can be applied to an area of ​​element 24 that is desirable to be open to the element, for example, in the center of the element. The dissimilar metallic point 28 can be any one or more of nickel, indium, silver, and tin. The dissimilar metallic point 28 has a lower melting point than that of the base metal of the locking element 24, for example, copper. The lower melting point of the point 28 melts and diffuses more quickly into the base metal of element 24.The base and dissimilar metals are chosen so that diffusion from one to the other results in an intermetallic phase with a lower melting temperature and a higher resistance than the base metal, forcing the element to melt at low overcurrent levels and preventing overheating of the device.

[0023] A protective coating 32 is applied to the fuse element 24 and an area of ​​the fuse fields 22a and 22b, as shown in Fig. 2 and Fig. 3 shown, applied. In one embodiment, the protective coating 32 is an electrically insulating epoxy which is printed, sprayed or otherwise applied to the underside of the insulating substrate and the copper layer 20b, thereby forming the locking element 24, field areas 22a and 22b and the connection areas 26a and 26b.

[0024] In one embodiment, the device 10 is configured such that the locking element 24 is positioned facing the circuit board (“PCB”). The protective coating 32 and the downward-facing configuration tend to limit the energy released from an opening in the locking element 24. It should be clear that the device 10 can alternatively operate with the locking element 24 positioned facing either towards or away from the PCB.

[0025] Fig. Figure 1 represents an upper surface of device 10. Here, the release notice 34 specifies a design and manufacturer's information for the device 10. In one embodiment, the release notice 34 is applied to an upper surface of an upper insulating substrate 12, for example by printing.

[0026] The device 10 can be provided in various standard sizes, such as a 1206 pack measuring 0.120 in by 0.06 in (3.2 mm) by (1.6 mm). Alternatively, the device 10 can be provided in an 1812 pack measuring approximately 0.179 in by 0.127 in (4.5 mm) by (3.24 mm). However, it should be clear that the device 10 can be made larger or smaller as required, and a device with a desirable design can be manufactured.

[0027] In the illustrated embodiment, terminals 36a and 36b are formed on the upper and lower surfaces of the device 10 using standardized plating techniques. Terminals 36a and 36b can consist of multiple layers of metal, such as electrolytic copper, electrolytic tin, silver, nickel, or other metal or alloy, as desired. Terminals 36a and 36b are dimensioned and configured to allow device 10 to be mounted on a PCB in a surface-mounted manner.

[0028] Fig. 2A represents a section AA of Fig. 1 represents the point that passes through the center of device 10. Consequently, element 24 and the dissimilar metal point 28 are in Fig. 2A. A pair of openings 46 and 48 are produced in the insulating materials 12 and 14, for example, before the device 10 is separated from the device assembly. The cladding of the terminals 36a and 36b covers the sides of openings 46 and 48. Accordingly, as shown in Fig. Figure 2A shows the connections along the sides of the device 10 at the surfaces of openings 46 and 48. If the device 10 is separated, then the connections 36a and 36b do not extend along the straight sides of the device, but extend, for example, as shown in Fig. 2B shown, not along the straight sides of the device at section BB of Fig. 1.

[0029] Fig. Figure 4 represents an equivalent circuit for device 10, which has been explained above. The in Fig. The four resistors shown are included for illustrative purposes only and are in no way intended to limit the scope of the claims included herein. However, the resistors represent realistic values ​​for the present device. Consequently, PTC thermistor layer 30 (or the combination of several PTC thermistor layers 30) is shown, for example, to have a resistance of 0.07 ohms. The fuse element 24 has a lower resistance of 0.031 ohms. As shown in Fig. 4 shown and how from Fig. As should be clear, the PTC thermistor layer 30 and the fuse element 24 are arranged electrically in parallel. According to the resistance equation for parallel devices, the equivalent resistance for device 10 E is equal to q the PTC resistor R at multiplied by the fuse resistor R f , which leads to a product that is divided by the sum of R at plus Rf The equation is divided. In this example, this equation yields an equivalent resistance, R. eq of 0.022 ohms. The equivalent resistance is even lower than the resistance of the metallic fuse element 24. The device 10 thus exhibits an initially low resistance operation. The device 10 also has the ability to reset itself via the PTC thermistor layer 30.

[0030] According to the equivalent circuit or substitute circuit of Fig. 4. Initially, the current will flow through the fuse element 24 and the PTC thermistor layer 30 until an overcurrent condition occurs, after which the current path through element 24 is opened and the current is then switched in parallel through the PTC thermistor layer under normal operation. It is assumed that overcurrent events will be relatively rare, especially for certain applications using device 10, which means that in numerous cases, device 10 will operate without experiencing an overcurrent condition over the entire lifetime of the PCB. This means that numerous devices 10 will operate under conditions of low resistance and low voltage drop throughout the lifetime of the PCB. However, if an overcurrent event does occur, device 10 will maintain its functionality, and the PCB on which it is mounted will not require rework or replacement.The original advantage of low resistance and voltage drop is lost, but overall functionality is retained.

[0031] In Fig. Figure 5 presents the results of a test of the opening time of a device 10 under current. Three current-time curves are shown: one for a metallic fuse element 24 rated for two amps, one for the PTC thermistor layer 30 rated for two amps, and one showing the current-time curve for the two parallel overcurrent components (combo). The combination curve tends to follow that of the PTC thermistor layer 30 and exhibits a longer response time than either the fuse element 24 or the PTC layer 30.

[0032] The illustrated device 10 uses the designed fuse element 24 and the PTC thermistor layer 30. Alternatively, the device 10 can use a fuse element 24 and a PTC thermistor layer 30 with different ratings. The PTC thermistor layer 30 could, for example, have a lower rating, such as 1.5 amps, than the two amps of the fuse element 24. The resulting device 10 would, for example, have a faster response time for a data bus application described in detail below. The telecommunications and battery applications described below might require a slower-acting overall device 10.

[0033] In Fig. Section 6 now presents results for four parts, which were subjected to voltage drop versus current tests in accordance with the principles of the apparatus 10. The graph shows that the voltage drop for the four parts was relatively repeatable, particularly at approximately two amps. After this point, the parts began to exhibit a slight variance. The equivalent resistance of the apparatus 10 also remained relatively constant over the current range shown. Furthermore, the voltage drop across the apparatus 10 was kept below 100 millivolts for all four tested parts, even at three amps.

[0034] In Fig. Figure 7 now presents an alternative multilayer PTC device 50. The device 50 comprises several of the same components described above, such as the locking element 24 (and associated fields 22a and 22b and connection areas 26a and 26b). The device 50 also comprises a protective coating 32 which, as shown above, covers the locking element 24 and a portion of the locking element's coatings. In one embodiment, the device 50 is configured to be mounted such that the locking element 24 faces the PCB. Alternatively, the device 50 could be mounted in the opposite orientation. The device 50 also comprises the upper insulating substrate 12, which, as described above, has, for example, etched electrodes 20a and 16. In one embodiment, the marking text 34 is arranged on an upper surface of the upper insulating substrate 12.The device 50 further comprises the lower insulating substrate 14, which, for example, has etched upper and lower copper electrodes 18 and 20b. The inner electrodes 16 and 18 extend, as shown above, at least halfway over their associated substrates 12 and 14 to create a desired opening characteristic of the adjacent PTC thermistor layers 30a and 30b (here collectively referred to as PTC thermistor layers 30 or generally individually as PTC thermistor layer 30).

[0035] The device 50 comprises three PTC thermistor layers 30a, 30b, and 30c (collectively 30). The device 50 further comprises two additional inner insulating substrates 52 and 54, which, for example, have upper and lower electrodes 38, 40, 42, and 44, respectively, extending the main part of the path over their corresponding insulated substrates 52, 52, 54, and 54, similar to electrodes 16 and 18. Each of the electrodes 16, 18, 20a, 30b, 38, 40, 42, and 44 can be etched or otherwise formed onto a corresponding FR-4 or polyimide insulating substrate 12 as described herein. The PTC thermistor layers 30 are inserted between corresponding electrode-bearing insulating substrates by any of the methods described above. Device 50, like device 10, can be manufactured as an arrangement of devices 50 which are separated into individual devices.

[0036] The PTC thermistor layers 30a to 30c each operate in the same manner as the PTC thermistor layer 30 of device 10; namely, the layers are conductive under normal operating current loads. Upon an overload condition that opens the fuse element 24, the PTC thermistor layers 30 heat up, causing their temperatures and resistances to rise to a threshold point where they increase exponentially, resulting in a high-resistance electrical path, similar to an open circuit of the fuse element 24. The additional PTC thermistor layers for a given packing size enhance the design of the PTC component of device 50. Thus, while three PTC thermistor layers 30 are shown with device 50, two layers, or four or more layers, could be provided as required to create a device 50 with a desired design.The overall design of PTC thermistor layers 30 can be the same or slightly different, for example less than that of the metallic element 24.

[0037] In Fig. Figure 8 now presents device 110 as an alternative integrated metallic / PTC thermistor device. Unlike the polyimide material of the Polyfuse® LF1206L device, the PTC thermistor layer 130 is ceramic-based. A suitable ceramic-based thermistor material is disclosed in US 6,218,928 B1, entitled "PTC Thermistor Material," which is attributed on the front of which to the TDK Corporation (Tokyo, JP).

[0038] The device 110 comprises an insulating substrate 112, which can be, for example, a ceramic material or glass. The upper and lower base electrodes 120a and 120b are formed on the upper and lower surfaces of the substrate 112, respectively, by thick-film stencil printing or sputtering. The electrodes 120a and 120b can again be formed from one or more metals, such as silver, copper, nickel, tin, and alloys thereof, which are applied to the surface of the polyimide by any of the methods mentioned above.

[0039] The base electrode 120b is shaped to form the locking element. The electrode 120b comprises, for example, the field regions 122a and 122b, which extend inwards to element 124 and outwards to the larger terminal regions 126a and 126b, as shown above with electrode 20, field region 22, element 24, and terminal region 26. The terminal regions 126a and 126b are finally plated together with the upper copper layer 120a to form the terminals 136a and 136b. The metallic locking element 124 of the device 110 can have any shape, dimensions, and be made of dissimilar metals, as explained above for element 24 of devices 10 and 50.

[0040] A ceramic PTC (“CPTC”) thermistor layer 130 is located on one side of an insulating base 112, for example, via thick-film stencil printing or spin coating. As shown, the CPTC thermistor layer 130 is in contact with areas of the electrodes 120a. A top cover layer 132a (for example, fired glass) is applied to the CPTC thermistor layer 130 and to exposed areas of the electrodes 120a. Although not shown, markings (explained above) can be provided on the top surface of the CPTC thermistor layer 130 and be visible through the top cover layer 132a.

[0041] A lower cover layer 132b (for example, fired glass) is applied to the lower electrode 120b and exposed areas of substrate 112. Terminals 136a and 136b are formed at the side edges of substrate 112, the electrodes 120a and 120b, and the cover layers 132a and 132b. Terminals 136a and 136b also cover areas of the upper and lower surfaces, for example, glass, of cover layers 132a and 132b, respectively. As explained and shown above, terminals 136a and 136b can comprise multiple metallizations. Furthermore, multiple CPTC thermistor layers 130 can be sandwiched between multiple insulating layers 112 in a manner similar to that of the polymeric device of Fig. 7 is to be applied.

[0042] During operation, the current flows, for example, from terminal 136a in parallel through the upper and lower electrodes 120a and 120b, and through both the CPTC thermistor layer 130 and the metallic fuse element to terminal 136b until the fuse element opens. Upon opening the fuse element, the CPTC thermistor layer 130 becomes highly resistive and restricts the current flow from terminal 136a to terminal 136b. Once the current surge has been discharged, the CPTC thermistor layer 130 becomes conductive, allowing the current to flow through the device 110.

[0043] In Fig. Figure 9 now presents an alternative integrated metallic / CPTC thermistor device. Here, unlike the polymeric material of the Polyfuse® LF1206L device, the CPTC thermistor layer 130 is again based on ceramic. In device 150, the CPTC thermistor layer 130 is doubled as the base substrate, thus utilizing the relatively rigid nature of the ceramic-based material.

[0044] The upper and lower base electrodes 120a and 120b are formed on the upper and lower surfaces of the CPTC thermistor layer 130, respectively, by thick-film stencil printing or sputtering. The electrodes 120a and 120b can be made of one or more metals, such as silver, copper, nickel, tin, and alloys thereof, which are applied to the surface of the CPTC thermistor layer 130 by any of the methods mentioned above.

[0045] In device 150, the lower base electrode 120b does not form a metallic locking element, but instead acts with the CPTC thermistor layer 130, the upper base electrode 120a and the terminals 136a and 136b to allow current to flow through the CPTC thermistor layer 130 under normal operating conditions.

[0046] A thin insulating layer 112, for example glass, is applied over the lower base electrode 120b and an arbitrarily exposed area of ​​the lower surface of the CPTC thermistor layer 130. A third electrode, the fuse element electrode 152, is formed on the substrate 112 to create the fuse element. The electrode 152 can, for example, include the same field regions 122a and 122b, extending inwards towards element 124 and outwards towards the larger terminal regions 126a and 126b (shown above in Figure 1). Fig. (8 shown). The metallic locking element of device 150 can have any of the shapes, dimensions, and non-identical metals described above for element 24 of devices 10 and 50 and element 124 of device 8.

[0047] An upper cover layer 132a (for example, glass) is applied to the upper base electrode 120a and exposed areas of the CPTC thermistor layer 130. Although not shown, markings (explained above) can be provided on the upper surface of the upper base electrode 120a and be visible through the upper cover layer 132a.

[0048] A lower cover layer 132b (e.g., glass) is applied to the fuse element electrode 152 and exposed areas of substrate 112. Terminals 136a and 136b are formed at the side edges of the CPTC thermistor layer 130, substrate 112, electrodes 120a, 120b, and 152, and cover layers 132a and 132b. Terminals 136a and 136b also cover areas of the upper and lower surfaces, for example, glass, of cover layers 132a and 132b, respectively. As explained and shown above, terminals 136a and 136b can comprise multiple metallizations.

[0049] During operation of device 150, the current flows, for example, from terminal 136a through the upper electrodes 120a, the CPTC thermistor layer 130, the electrode 120b, and the metallic fuse element layer 150 to terminal 136b until the fuse element opens. Upon opening of the fuse element, the CPTC thermistor layer 130 becomes non-conductive and prevents the current from flowing from terminal 136a to terminal 136b. Once the current waveform has been diverted, the CPTC thermistor layer 130 becomes conductive, allowing the current to flow again through the device 150.

[0050] In Fig. In Figure 10, an alternative CPTC thermistor device 160 is now presented. Advantageously, the CPTC thermistor device 160 uses both upper and lower base electrodes 120a and 120b to make contact with both the CPTC thermistor layer 130 and the locking element 162, which, in the illustrated embodiment, is a thick film, a thin film, or a wire-bonded locking element. The locking element 162, shown generally to be arranged vertically, extends along the edge of the CPTC thermistor layer 130 from one base electrode 120a to the other base electrode 120b. The angle, shape, and number of such locking elements can vary. The base electrodes 120a and 120b are also formed on both sides of the CPTC thermistor layer 130 by any suitable technique and from any suitable one or more of the metals described above.

[0051] In the illustrated embodiment, the device 160 also includes cables 164 and 166, which can be arranged radially or vertically for various mounting configurations. During operation of the device 160, the current flows, for example, from the upper electrode 120a (cable 164) to the lower electrode 120b (cable 166), parallel through the CPTC thermistor layer 130 and the fuse element 162, until the fuse element opens. Upon opening of the fuse element, the CPTC thermistor layer 130 becomes non-conductive and prevents the current from flowing from the upper electrode 120a (cable 164) to the lower electrode 120b (cable 166). Once the current waveform has been diverted, the CPTC thermistor layer 130 becomes conductive, allowing the current to flow again through the device 160.

[0052] In Fig. Figure 11 now shows an alternative CPTC thermistor device 170, which is the same as device 160, except that the CPTC thermistor layer 130 includes or defines a larger diameter hole or opening 138, configured to accommodate a diagonally arranged locking element 172. The locking element 172 is, as shown, soldered or otherwise electrically connected to the base electrodes 120a and 120b, which are located on opposite sides of the opening 138. The element 172 is shown to extend diagonally across the opening. The diagonal extension allows the element 172 to be elongated, which may be advantageous for sizing purposes.

[0053] In the CPTC thermistor device 170, cables 164 and 166 are also arranged on end plates 174 and 176, respectively, which in turn are soldered to the base electrodes 120a and 120b, respectively, or connected to them in some other way. The end plates 174 and 176 cover the opening 138, protect the fuse element 172, and electrically connect the fuse element to the cables 164 and 166. The end plates also allow the terminal or end part to be coated with a protective material, for example, epoxy, which maintains a gap or empty space in the opening 138, thus improving the fusion penetration of the fuse element 172. The cables 164 and 166 shown extend radially from the end plates 174 and 176. Alternatively, the cables 164 and 166 extend, for example, as shown in Fig. 10 shown, from the end plates 174 and 176 in an axial direction.

[0054] The wire-fuse CPTC thermistor devices 160 and 170 operate in the same manner as the thin-film CPTC thermistor devices 110 and 150, which operate at least substantially in the same way as the polymer-based PTC thermistor devices described above. Under normal operation, current flows through both the CPTC thermistor layer 130 and the fuse elements 124, 152, 162, or 172 until an overcurrent event occurs. At such a time, the fuse element opens, the CPTC thermistor layer 130 becomes non-conductive, and the device 110, 150, 160, or 170 prevents the overcurrent from passing through electrical components downstream of the device.When the overcurrent event subsides, the CPTC thermistor layer 130 resets itself to a conductive state, which allows the protected circuit to function even with a larger voltage drop across the device 110, 150, 160 or 170.

[0055] Fig. Figure 12 shows a surface-mounted configuration for either the one in Fig. 10 or Fig. The devices described in Section 11. Here, the PTC or CPTC device comprises end plates 182 and 184, each having a field area 180 configured to be attached to a circuit board via reflow or wave soldering. The illustrated embodiment shows a CPTC disk 130 (locking element present but not visible), wherein end plates 182 and 184 and field areas 180 electrically connect the CPTC disk 130 and the locking element with a trace pattern on the circuit board.

[0056] In Fig. Figure 13 now presents the circuit 60 in a suitable application for devices 10, 50, 110, 150, 160, 170, namely a telecommunications protection application (hereinafter referred to simply as device 10 for simplicity). The telecommunications protection circuit 60 comprises a Digital Subscriber Line (“DSL”) drive 62, which may be an interface card located between downstream telecommunications equipment (not shown) and the devices in Fig. The data lines shown in the 8 diagrams are located at the telecommunications facility. The telecommunications facility may include equipment or facilities for a central switching point, which switches calls from one point to another, for example, digital voice or internet data.

[0057] The DSL drive 62 conditions and regenerates signals intended for a circuit or other component of the telecommunications equipment. The DSL drive 62 is a bidirectional transceiver that conditions signals transmitted in both directions via the connection line 64 and the ring line 66. The converter 68 prevents direct current (DC) present on either side of the converter from being transmitted to the other side. The converter 68 also eliminates any noise or crosstalk from adjacent lines that are coupled and therefore common to both the connection line and the ring line. The converter 68 thus couples different signals.

[0058] The transient voltage reducer 70 comprises a surge protection device, such as a thyristor. The reducer 70 can, for example, use multiple diodes positioned with a thyristor to reduce capacitance along any path, such as from the terminal line 64 to the ring line 66, from the terminal line 64 to ground 72, and from ground 72 to the ring line 66. The diodes and the thyristor are positioned such that each path has at least three capacitance reductions, providing highly biased paths that stepwise reduce the capacitance in series to an extremely low level that does not attenuate or deter the data signals.

[0059] The integrated fuse element / PTC device 10 is positioned in the ring line 64 and the connecting line 66 to protect against an overcurrent condition caused, for example, by a power transmission situation or power crossover situation, in which a telephone line or data line is inductively coupled to a power line, generating a continuous overvoltage condition. Transient voltage inhibitors 70 clamp the overvoltage at a safe level, dissipating a quantity of energy and triggering the overcurrent device 10.

[0060] If only a metallic element is used, the corresponding fuse in circuit 60 must be replaced. If only a PTC element is used, its resistance is significantly higher, which limits how far DSL drive 62 can drive the DSL signals down the connection 64 or the ring line 66. Since current crossing conditions are rare, device 10 provides a resettable device that initially operates at low resistance. If a current crossing condition occurs, the fuse opens, triggering the PTC device, which is then reset so that circuit 60 continues to function, at least for a limited range of data transmission.

[0061] In Fig. Figure 14 now presents circuit 80 as another application for the integrated fuse element / PTC device 10, namely a data bus circuit. The data bus circuit shown uses an IEEE 1394 controller 82, which is used with computers and other equipment, such as video cameras and cable outlets. The 1394 associated connector 84 is small, which is advantageous for the applications mentioned above. Circuit 80 uses two twisted conductors, TPA and TPB, each of which transmits data bidirectionally between controller 82 and connector 84.

[0062] Circuit 80 includes transient voltage suppressors 86, which are arranged across the data line to ground 88. Voltage suppressors 86 suppress or inhibit electrostatic discharge (ESD) events that occur on data lines TPA and TPB. Circuit 80 also includes a varistor 90, which suppresses ESD or other power-on surges that occur on a voltage line V.bus 92 occur, suppressed. V bus For example, a 33 VDC source is used by controller 82 to drive or control the voltage along line 92 in order to power whatever is connected to connector 84, such as a printer or a modem.

[0063] The integrated fuse / PTC device 10 protects associated equipment from any type of overcurrent condition occurring on the ring circuit 92. Again, it is desirable that the device 10 has the lowest possible resistance and that as much energy or current as possible can be supplied from the controller 82 to the connector 84 and associated equipment. The device 10 is therefore well suited for this application, as it is unlikely that circuit 92 will experience or undergo an overcurrent condition.

[0064] Device 10 can be used effectively in Universal Serial Bus (“USB”) data circuits and applications. Furthermore, the devices can be used in an Ethernet-connected circuit. In an Ethernet-powered circuit, two of the four twisted pairs in a Cat3 / 5 cable carry power and can also carry data. The power supply capacity for such a circuit is limited, which makes Device 10 well-suited for this type of application.

[0065] In Fig. In section 15, circuit 100 represents another application for an integrated fuse element / PTC device 10, namely a battery protection circuit. Circuit 100 operates with a charger 94, for example, for a mobile phone 96. The control circuit 102 of a battery pack circuit 100 senses a voltage supplied by the charger 94. If, for example, the polarity of the voltage is incorrect, or the voltage level is incorrect, the controller 102 opens redundant field-effect transistor (“FET”) switches 104 to prevent any current from flowing through circuit 100 to the battery 108. The control circuit 102 can also monitor the temperature to detect thermal runaway. Circuit 102 then cuts off the current flow through circuit 104 to the battery 108.

[0066] The PTC fuse 10 provides a layer of redundant circuit protection. For example, if the control circuit 102 malfunctions or the FET 104 short-circuits, the PTC fuse 10 provides a backup or backup layer of overcurrent protection. The DC voltage of the battery 106 in the battery pack 100 varies, which makes the low resistance of the fuse 10 significant. For example, if an overcurrent protection device in a three-volt DC battery pack has a voltage drop of ¼ volt, then the overcurrent protection device will consume eight percent of the battery's operating time. Battery 108 may have a voltage drop below which the mobile phone will not operate, increasing the percentage of battery life consumed above the battery's lifespan. Consequently, a voltage drop in the millivolt range is not a significant factor for the fuse 10. Fig. 6 is well suited for this application.

[0067] It should be clear that various changes and modifications to the existing preferred embodiments described herein will be obvious to a person skilled in the art. Such changes and modifications can be implemented without deviating from the nature and scope of the present subject matter and without diminishing its intended advantages. It is therefore intended that such changes and modifications are covered by the appended claims.

Claims

[1] Circuit protection device (160, 170) comprising; a ceramic positive temperature coefficient (“CPTC”) thermistor layer (130); a fuse element (162, 172) supported by the CPTC thermistor layer (130), wherein the fuse element (162, 172) has a lower resistance than the CPTC thermistor layer (130); and first and second cables (164, 166) electrically connected in parallel to the fuse element (162, 172) and the CPTC thermistor layer (130) so that current (i) initially flows through the fuse element (162, 172) and the CPTC thermistor layer (130) under normal operation and (ii) flows through the CPTC thermistor layer (130) after opening of the fuse element (162, 172) under normal operation. [2] The circuit protection device (160, 170) of claim 1, wherein the fuse element (162, 172) is a surface mounted fuse element (162, 172) applied to the CPTC thermistor layer (130). [3] The circuit protection device (160, 170) of claim 1 or 2, wherein the fuse element (162, 172) is a wire element attached to electrodes (120a, 120b) deposited on the CPTC thermistor layer (130).

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