Power failure handling using stop commands

Abstract

Data storage device (110) comprising: non-volatile memory circuits (112A-N); a detection circuit (126) configured to detect a voltage of the non-volatile memory circuits (112A-N) and trigger a power failure event based on a threshold for the voltage; and a controller (114) configured to: Determining (202) that the power failure event has occurred; in response to determining that the power failure event has occurred, determining (206) which of the non-volatile memory circuits (112A-N) are executing a first type of memory commands; and Issuing (208) a stop command to the particular non-volatile memory circuits to stop the execution of the first type of memory commands.

Description

Technical FieldThe present description generally relates to data transfer within data storage devices including power failure handling using non-volatile memory device stop commands.BackgroundSolid state memory devices using flash memory offer performance and power consumption advantages over conventional hard disks. In order to further improve performance, many semiconductor memory devices include and use volatile memory such as random access memory (RAM) in addition to flash memory. For example, volatile memory may be used to cache data and / or temporarily store system data used to manage the data stored in flash memory. However, unlike flash memory, the volatile memory requires power to obtain the data stored therein. When the power supply is interrupted, all data stored in the volatile memory may be lost. This loss of data may mean overhead operations in a solid state memory device because lost tables must be reconstructed. Moreover, this loss of data may result in the permanently lost buffered data that has not been stored in the flash memory prior to the power failure.US 2014 / 0 304 454 A1 relates to a storage system and a method for data hardening in the storage system.SummaryAccording to the invention there is provided a data storage device, system and method having the features of the independent claims; dependent claims relate to preferred embodiments.The disclosed subject matter relates to a data storage device that includes a mechanism for a controller to suspend certain flash memory operations when a power failure event occurs. After the occurrence of the power failure event, there is a limited amount of time to obtain the system data and, in some cases, the host data in the non-volatile memory. The controller may be configured to issue certain data retention commands, such as write commands, for storing the system data after a power failure event is determined to have occurred. The controller may be configured to first detect whether any unnecessary memory commands are being executed when the power failure event has been detected. The controller may be configured to issue a stop command to nonvolatile memory circuits (e.g., flash memory) to stop execution of the detected memory commands such that more nonvolatile memory becomes available and instead the data retention commands may be issued.In another aspect, a data storage device includes non-volatile memory circuits and a controller. In one aspect, the controller is configured to determine that a power failure event has occurred. The controller is also configured to determine which of the non-volatile memory circuits executes a first type of memory commands in response to determining that the power failure event has occurred. The controller is also configured to issue a stop command to the particular nonvolatile memory circuits to stop execution of the first type of memory commands.In another aspect, a system includes a plurality of flash memory circuits, a random access memory (RAM), and a controller communicatively coupled to the plurality of flash memory circuits. In one aspect, the controller is configured to determine that a power failure event has occurred. The controller is also configured to determine which of the plurality of flash memory circuits executes an erase command or a program command in response to the determination that the power failure event has occurred. The controller is also configured to stop execution of either the erase command or the program command based on a stop command output to the particular flash memory circuits.In another aspect, a method includes determining that a power failure event has occurred. The method also includes, in response to determining that the power failure event has occurred, determining which flash memory circuits in a data storage device execute an erase command or a program command. The method also includes issuing a stop command to the particular flash memory circuits to end the erase command or to suspend the program command.In another aspect, a system includes means for determining that a power failure event has occurred in flash memory. The system also includes means for determining, in response to determining that the power failure event has occurred, which flash memory circuits in a data storage device execute an erase command or a program command. The system also includes means for issuing a stop command to the particular flash memory circuits to end the erase command or to suspend the program command.It is to be understood that other configurations of the present technology will be readily apparent to those skilled in the art from the following detailed description, in which various configurations of the present technology are shown and described for purposes of illustration. As will be appreciated, the present technology is capable of other and different configurations, and its various details may be modified in numerous other aspects without departing from the scope of the present technology. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.Brief Description of the DrawingsCertain features of the present technology are set forth in the appended claims. However, for purposes of explanation, several implementations of the present technology are set forth in the following figures. FIG. 1 illustrates an example data storage system that may implement a system for power failure handling using stop commands, according to one or more implementations. FIG. 2 illustrates a flowchart of an example process of power failure handling using stop commands, according to one or more implementations. FIG. 3 illustrates example non-volatile memory circuits distributed across different channels in an example data storage device, according to one or more implementations. FIG. 4 illustrates example blocks of non-volatile memory circuits distributed across different channels in an example data storage device, according to one or more implementations.Detailed DescriptionThe detailed description set forth below is intended as a description of various configurations of the present technology and is not intended to represent the only configurations in which the present technology may be practiced. The accompanying drawings are incorporated herein and form a part of the detailed description. The detailed description contains specific details for the purpose of a thorough understanding of the present technology. However, the present technology is not limited to the specific details set forth herein and may be practiced using one or more implementations. In one or more instances, structures and components are shown in block diagram form to avoid obscuring the concepts of the present technology.Handling a power failure event in semiconductor memory devices using flash memory presents a significant challenge when a limited amount of time is available after the event to preserve system data and / or host data stored in the volatile memory. As used herein, the term "system data" refers to, for example, data for managing the data storage device, including, without limitation, an address mapping index from host logic block number (host LBN) to physical block (e.g., NAND block), a second layer index for the address mapping index from host LBN to physical block, boot information, attributes of physical blocks (e.g., deleted, waiting for deletion, completed upon programming, programming), change log information, host table information, listing of available physical blocks, write / erase counts, and garbage collection metrics. As used herein, the term "host data" refers to, for example, data received from and / or sent to a host, including data that is internally moved. The present technology relates to two different scenarios that address this challenge of data preservation after a power failure. A first scenario includes an on-board capacitor or battery source that provides power to end existing memory commands, issue a number of write commands to nonvolatile memory devices, and complete execution of such write commands to obtain system data and / or certain host data after a power failure. In a second scenario, where an on-board capacitor or battery source may not be available, there may be no time to issue write commands to obtain system data stored in volatile memory after a power failure. Rather, the amount of energy remaining after the power failure event allows to prioritize which write commands to be initiated and which write commands to be terminated to put the non-volatile memory in a stable state before the power is completely lost.When a power failure event is treated with an on-board (or internal) power supply circuit such as a capacitor or a battery, system data and certain host data (e.g., host data acknowledged back to the host) stored in a volatile memory such as RAM are ideally preserved before the power supply is completely interrupted. The host data may be data received from the host and acknowledged by the data storage device for storage in a non-volatile memory. The power integrated circuit does not provide an unlimited power supply, so all write commands issued to obtain existing system data and / or host data may need to be completed as soon as possible. A first type of memory instructions, such as erase and program instructions (e.g., unacknowledged host data to be written), contain relatively long execution sequences and therefore require most time to complete them. This first type of instructions is not ideal after a power failure. In this regard, the erase and program commands are not critical and, therefore, are unnecessary to execute when it is necessary to execute write commands directed to storing system data after a power failure. For example, if erase or program instructions are being executed and a power failure event occurs, time may be lost in executing these types of instructions that are likely not to be correctly completed or executed.In handling a power failure event without an on-board (or internal) power supply circuit, the goal shifts to protect the cells of a nonvolatile memory device by placing the cells in a stable state before the power supply is completely lost. Power failure events may occur in various environments. For example, if a data storage device binds (or connects to) a host device (e.g., a computer) and the host device loses power, this power failure event may include a relatively longer period of time for which the supply voltage level falls below an operating voltage of the data storage. In another example, when the data storage device is forcibly detached from the host device, this power failure event may have a relatively shorter time period for which the voltage falls below the operating voltage of the data storage device. The present technology provides that the cells of the nonvolatile memory devices are consistently protected so that the nonvolatile memory device can be consistently recovered in a next boot sequence.In one or more implementations, when a power failure event is handled with an on-board (or internal) power supply circuit, a controller of the data storage device sends a stop command, such as an erase stop command or a program stop command, to a particular non-volatile memory device identified as executing an erase command or a program command, respectively. The nonvolatile memory device receiving the stop command interrupts the execution of the erase or program commands in a relatively short period of time and waits for a new command from the controller. When the first type of instructions (e.g., erase instruction, program instruction) is interrupted, the controller may execute a second type of memory instructions (e.g., write instructions directed to storing system data) on any available nonvolatile memory devices to complete the power failure handling process in a shorter time. Since the power supply integrated circuit does not provide an unlimited power supply when the power supply comes to a stall from the host, the data storage device uses the remaining power for data preservation instead of non-critical storage operations.In one or more implementations, the stop commands are issued by hardware or firmware depending on the implementation. The stopped commands (e.g., erase command, program command) may be re-executed in a next boot sequence. The power fail handling activities for data preservation may include write commands specific to storing system data and / or acknowledged host data in non-volatile memory. These write commands may include a write command for storing (or storing) an index of data associated with the nonvolatile memory device. The write commands may also include a write command for storing an erase count of a given physical block for a non-volatile memory device. The write commands may also include a write command to store characteristics of a given physical block for a non-volatile memory device, such as a number of instances in which the physical block was deleted, has been written, or the like. The write commands may also include a write command for storing host payload data when that data has already been acknowledged to the host by the data storage device. The data stored in response to the issued data obtaining commands may be used for a next recovery startup sequence.When handling a power failure event without an on-board (or internal) power supply circuit, the controller sends a stop command to a particular non-volatile memory device to suspend an executed erase or program command at that device. During the power failure event, the supply voltage drops at a rate that may be unstable or unpredictable, such that the remaining time to store existing system data in a non-volatile memory is unknown. The program command may not be executed properly because an insufficient amount of charge is applied to the cells of the nonvolatile memory device. For example, the voltage levels for each program cycle or erase cycle in a multi-level cell (MLC) or three-level cell (TLC) may not be brought to the proper levels, thereby incompletely charging (for programming) or discharging (for erasing) the cells. The nonvolatile memory device receiving the stop command interrupts any execution of the erase or program commands in a relatively short period of time. In this regard, the stop commands may be completed before the voltage falls below the operating voltage of the nonvolatile memory device, which maintains the cells of the nonvolatile memory device in a stable state.The present technology provides a data storage device including nonvolatile memory circuits and a controller. In one or more implementations, the controller determines that a power failure event has occurred. The controller then determines which of the nonvolatile memory circuits executes a first type of memory commands in response to the determination that the power failure event has occurred. The controller then outputs a stop command to the particular nonvolatile memory circuits to stop execution of the first type of memory commands. The non-volatile memory circuits may continue execution of suspended write (or program) instructions upon receipt of a new command (e.g., a resume command) from the controller, or may begin execution of an erase command on a physical block in a stable state upon receipt of a subsequent erase command from the controller.FIG. 1 illustrates an example data storage system 100 that may implement a system for power failure handling using command suspension, according to one or more implementations. However, not all of the illustrated components may be required and one or more implementations may include additional components not shown in the figure. Variations in the arrangement and type of components may be made without departing from the spirit or scope of the claims as set forth herein. Additional components, other components, or fewer components may be provided.The system 100 includes a data storage device 110 and a host device 130. The data storage device 110 includes a bus 111, one or more flash memory circuits 112A-N, one or more channels 113A-N, a controller 114, a random access memory (RAM) 122, an interface 124, and a sensing circuit 126. The controller 114 includes a power failure circuit 120. The controller 114 may include one or more decoders (not shown) such as an error correction code (ECC) decoder and one or more encoders (not shown) such as ECC encoders. The one or more decoders and / or the one or more encoders may be one or more dedicated circuits of the controller 114, may be implemented via firmware running on the controller 114, and / or may be one or more circuits separate from the controller 114. As used herein, the term "flash memory circuit" may be used interchangeably with the term "non-volatile memory device.".The power failure circuit 120 processes a sense circuit signal from the sense circuit 126 that may indicate whether a power failure event has occurred. In one or more implementations, the power failure circuit 120 determines whether the power failure event has occurred based on the sensing circuit signal. The power failure circuit 120 may issue a stop command to one or more of the flash memory circuits 112A-N in response to the sensing circuit signal. The power failure circuit 120 may issue an erase stop command to end execution of an existing erase command. The power failure circuit 120 may issue a program stop command to either suspend an existing program command resumed at a later time when the power supply is recovered or end an existing program command. In some aspects, the controller 114 includes one or more logic circuits that issue standard read / write commands during runtime (or normal operation). In this regard, these logic circuits may be configured to output the stop command to the one or more of the flash memory circuits 112A-N based on a state of the sensing circuit signal. In one or more aspects, in some implementations, the logic circuitry may process the sense circuit signal from the sense circuit 126, or may receive an indication from one or more processor cores of the controller 114 to trigger the output of the stop command. For example, the one or more logic circuits may issue standard read / write commands during runtime when the sense circuit signal is in a first logic state ("0"), and the stop command during a power failure event issue signal when the sense circuit signal is in a second logic state ("1"). The logic circuits may be separate from the power failure circuit 120 in some implementations or a sub-component of the power failure circuit 120 in other implementations.The interface 124 of the data storage device 110 couples the data storage device 110 to the host device 130. The interface 124 may be a wired interface such as a peripheral component interconnect controller (PCIC) interface, an international association interface for personal computer memory cards (PCMCIA) interface, an AT attach serial interface (SATA) interface, a universal serial bus (USB) interface, or generally any wired interface. Alternatively or additionally, the interface 124 may be a wireless interface such as wireless SATA, Bluetooth, or generally any wireless interface.The sensing circuit 126 is coupled to the interface 124 and to the controller 114. The sensing circuit 126 may be a voltage detector in some implementations or a current detector in other implementations. The sensing circuit 126 measures the power supply levels (e.g., voltage amplitude, current amplitude) from the host device 130 to determine whether a power failure event has occurred. In some aspects, sensing circuit 126 may measure power supply levels from other external power sources (other than host device 130). When the power supply levels from the host device 130 fall below a predetermined threshold (e.g., 10%, 20% fall), the sensing circuit 126 may output a notification (e.g., a sensing circuit signal) to the controller 114 indicating that the power failure event has occurred.In one or more implementations, the system 100 includes an internal power source 128 to provide additional power to the controller 114 and the non-volatile memory devices (e.g., flash memory circuits 112A-N) during a power failure event. The internal power source 128 may be coupled to the sensing circuit 126 and to the controller 114. The internal power source 128 includes a passive electrical circuit (e.g., a capacitor) or a battery in some implementations.Channels 113A-N may be coupled to bus 111, and channels 113A-N may each couple one or more of flash memory circuits 112A-N to controller 114 via bus 111. In several implementations, channels 113A-N may be directly coupled to controller 114, e.g., without bus 111. Channels 113A-N and / or bus 111 may be wired interfaces.In the system 100, the channel 113A is communicatively coupled to the flash memory circuit 112A, the channel 113B is communicatively coupled to the flash memory circuit 112B, the channel 113C is communicatively coupled to the flash memory circuit 112C, and the channel 113N is communicatively coupled to the flash memory circuit 112N. Although channels 113A-N are shown in system 100 as each communicatively coupled to one of flash memory circuits 112A-N, each of channels 113A-N may be communicatively coupled to a plurality of flash memory circuits 112A-N, as discussed further below with reference to FIG. 2. If multiple flash memory circuits 112A-N are coupled to a single one of channels 113A-N, only one of flash memory circuits 112A-N may be able to send or receive data over the channel at a given time.The bus 111 and / or the channels 113A-N may each be associated with a maximum bandwidth and / or a maximum throughput. Similarly, the interface 124 may also be associated with maximum bandwidth and / or throughput. Thus, there may be bandwidth / throughput restrictions on the amount of data that can be transmitted over bus 111 and / or over each of channels 113A-N at any given time. Further, at any given time, each of flash memory circuits 112A-N may only be capable of processing a single command, e.g., a write command or a read command.The controller 114 may be operable to read and write data from and to the flash memory circuits 112A-N via the channels 113A-N and the bus 111. For example, the controller 114 receives data, such as a stream of data, from the host device 130 via the interface 124, from where the data may then be written to one or more of the flash memory circuits 112A-N via the bus 111 and one or more of the channels 113A-N. Flash memory circuits 112A-N may each include one or more physical blocks, such as NAND blocks and / or NOR blocks. The physical blocks may each include one or more physical pages into which data may be written or from which data may be read.The controller 114 may use the RAM 122 to queue system data and / or host data to be stored in the flash memory circuits 112A-N. For example, RAM 122 may be used as a buffer for rate control or otherwise used to store information (e.g., queues, variables, physical block status, logical to physical address mapping tables, persistence / retention data, settings, etc.) used by controller 114 to read / write data to / from flash memory circuits 112A-N. Because the RAM 122 may be volatile memory, the controller 114 may write from the RAM 122 to the flash memory circuits 112A-N to permanently store information in one or more of the flash memory circuits 112A-N. When the data storage device 110 is powered on, the controller 114 may retrieve the information from the one or more flash memory circuits 112A-N and store the information in the RAM 122.Although the physical pages of the physical blocks of flash memory circuits 112A-N may be individually written (e.g., a physical page is a unit for read / write operations), the physical pages of a physical block of flash memory circuits 112A-N may not be individually erased. Instead, a physical page of a physical block may only be deleted and subsequently rewritten by deleting all physical pages of the physical block (e.g., a physical block that is a unit for deletion operations). Thus, if data is moved from a page of a physical block or the data is deleted, the page may be marked invalid and cannot be reused until the entire physical block is deleted.When an erase command is issued to a non-volatile memory device (e.g., one of flash memory circuits 112A-N) and a power failure event occurs, the amount of time until completion of the erase command (e.g., about 10 to 20 milliseconds) may not be sufficient because internal power source 128 (e.g., a buffer battery or capacitor) may not have a sufficient power supply to apply to the non-volatile memory device.In some cases, when a power failure event occurs, a program command executed on a non-volatile memory device (e.g., one of flash memory circuits 112A-N) may be suspended at any step in the program sequence. In this regard, the cells of a page may not be loaded to the desired program levels, causing a subsequent read operation from that page to become invalid because the programming of the page is corrupted after the power failure event.When a non-volatile memory device (e.g., one of flash memory circuits 112A-N) is in a standby state, controller 114 may issue a write command to store system data and / or data from a host that has been acknowledged by controller 114. For example, if a host sends a program command or a write command to the data storage device 100 and the controller 114 has acknowledged the command from the host by sending an acknowledge signal back to the host, then the operation for writing the host data is considered to be completed. In this regard, the host data associated with the confirmed program command (or write command) becomes a higher priority operation that needs to be completed before power is lost in the data storage device. In some cases, the host data sent from the host is temporarily stored in a volatile memory such as a local cache, thereby increasing the importance of writing the host data from the volatile memory to the nonvolatile memory device.To increase the likelihood that writes to the non-volatile memory device will successfully complete for data preservation after a power failure, the present technology provides for issuing a stop command (e.g., suspension of an existing unnecessary (or less important) write or erase command) to the non-volatile memory devices. Issuing the stop commands may enable additional non-volatile memory devices to move existing system data from the volatile memory to the non-volatile memory before the voltage falls below the operating voltage of the non-volatile memory device. In one or more implementations, the stop commands are relatively short, such that they include a relatively low payload or control information overhead, thereby creating a relatively low latency in processing time for transitioning the non-volatile memory device to a suspend state.When a stop command is issued to stop a non-critical programming command in a non-volatile memory device, the cells of a physical page in a physical block may not be fully programmed for the non-volatile memory device. This is because a programming command may include multiple cycles (or a sequence of cycles) to complete the programming of the physical page, and the voltage applied to each individual cell may be increased (or increased) to a certain voltage level with each cycle. In some aspects, the program command may include a duration of a few microseconds to complete. In this regard, a stop command issued to the nonvolatile memory device issues the program command, which results in the cell charge levels not being raised to the desired levels for programming the physical page. The data that can be read from the page affected by the suspended program command would likely be corrupted data (or data with errors) because the cells were not loaded to the correct levels to store the correct data values. In some aspects, when a program command is halted in between (or before completion), the data to be programmed (or written) to the nonvolatile memory device remains in a local cache (or pre-charge registers) of the nonvolatile memory device. If the non-volatile memory device cannot obtain data in a suspend state, the data already stored in the pre-charge registers would be lost, and the stopped (or suspended) program command may not be recoverable. For example, the controller 114 sends a write command to one of the non-volatile memory devices and loads the data with a set of pre-charge registers for the non-volatile memory device. The controller 114 may then initiate a sequence of program cycles to write the data from the set of pre-charge registers to the non-volatile memory device. When the non-volatile memory device receives a stop command from the controller 114, the programming operation may be suspended at any point in the sequence of programming cycles with the cells of a physical page at arbitrary programmed levels. The pre-charge registers may be cleared after a power failure, causing loss of data for a subsequent program operation.Similarly, in an erase operation, the erase command may include multiple cycles to discharge the cells in a physical block. In some aspects, the clear command may include a duration of a few milliseconds to complete. If an erase command is suspended in between (or before completion), a number of cells may still contain some charge. In this connection, when subsequent write operations are performed on the cells that have not been fully discharged during an erase operation, the cells being written to may not be charged to the expected level due to the residual charges in the cells. This may then lead to errors during a read operation.In one or more implementations, when a stop command is issued to a specific non-volatile memory device of a chip or package that includes multiple non-volatile memory devices, the specific non-volatile memory device in that chip or level is quiesced and cannot perform any write operations. Other nonvolatile memory devices belonging to this chip or level are available for use after the stop command issued for the specific nonvolatile memory device is completed. For example, a new command such as a read command or an erase command may be issued to the remaining nonvolatile memory devices. However, a new program command may not be issued to the same chip or level that the program stop command was issued. Instead, the new programming command may be sent to another chip or level to perform write operations that store the system data and / or acknowledged host data in a non-volatile memory.In one or more implementations, programming operations performed in more than one non-volatile memory device may be performed in parallel. In this regard, a stop command would be issued to a specific nonvolatile memory device in which an unnecessary programming operation is performed. In some aspects, a separate stop command is issued to each non-volatile memory device in which an unnecessary program or erase operation occurs. For example, in a nonvolatile memory device package including four nonvolatile memory devices, programming operations may occur simultaneously, in which four individual stop commands are then output individually to each of the four nonvolatile memory devices.In one or more implementations, the format of a stop command issued to suspend an erase operation (or an erase stop command) and the format of a stop command issued to suspend a program operation (or a program stop command) are different. In some aspects, the erase stop command represents a reset command. In this aspect, there is a predetermined prefix in the erase stop command to restart the stopped erase operation. Similarly, there is a predetermined prefix in the program stop instruction to restart the stopped program operation. In this regard, the stop command used to suspend the program command is a special command because suspending the program command using a stop command similar to that of the erase stop command can completely abort the program command without the ability to resume the stopped program command at a later time (or a later startup cycle).In one or more implementations, a program stop command is issued by the controller 114 to a specific non-volatile memory device. The controller 114 performs a status inquiry of a nonvolatile memory device of a chip or a plane after the issuance of the program stop command to the nonvolatile memory device to determine whether the nonvolatile memory device has entered a stop state (or suspend state) for program commands or a termination state for erase commands. When the nonvolatile memory device has entered the suspend state, the controller 114 may issue another command such as an erase command or a read command to other nonvolatile memory devices belonging to other chips or levels. To continue the stopped program command, the controller 114 may issue the particular program command that includes a predetermined prefix indicating a request to resume the stopped program command. In this regard, a nonvolatile memory device may be transitioned from the suspend state back to a program state in the suspend state based on the subsequent program command. With respect to erase commands, the controller 114 outputs either a reset command or an erase stop command to prevent the erase operation from occurring. The controller 114 then monitors the status request from the non-volatile memory device to detect a ready signal. After detecting the ready signal, the controller 114 may resume the stopped erase command by issuing a same erase command to a same address in the nonvolatile memory device (e.g., an address pointing to a physical block of the nonvolatile memory device). In this regard, a nonvolatile memory device may be transitioned from the completion state back to an erase state in the completion state based on the subsequent erase command.In one or more implementations, a voltage detector (e.g., the sensing circuit 126) monitors the power supplied to the controller 114 and the nonvolatile memory devices. The voltage detector may be configured to detect a predetermined operating voltage (e.g., 3.3 V, 2.5 V, 1.8 V) with respect to a predetermined threshold. The predetermined threshold may correspond to a percentage of the power supply voltage (e.g., 90%). For example, if the power supply voltage drops by at least 10% (or below the 90% threshold), the voltage detector outputs an alarm signal (e.g., the detection circuit signal) that causes the controller 114 to issue a stop command to the nonvolatile memory devices.FIG. 2 shows a flow diagram of an example process 200 of power failure handling using command suspension, according to one or more implementations. For purposes of explanation, the example process 200 is described herein with reference to the controller 114 of FIG. 1 ; however, the example process 200 is not limited to the controller 114 of FIG. 1. Further, for purposes of explanation herein, the blocks of the example process 200 are described as being serial or linear. However, multiple blocks of the example process 200 may occur in parallel. Additionally, the blocks of the example process 200 need not be executed in the order shown and / or one or more of the blocks of the example process 200 need not necessarily be executed.The example process 200 begins at step 202 when the controller 114 (FIG. 1 ) of the data storage device 110 determines that a power failure event has occurred. For example, the controller 114 may receive a sensing circuit signal from the sensing circuit 126 indicating that a voltage monitored at the interface 124 has dropped by about 10% (e.g., from 5.0 V to 4.5 V) and the power supply from the host device 130 is therefore at or below a first threshold to indicate the power failure event. In this approach, the sensing circuit 126 may not need to detect the voltage in the flash memory circuits 112A-N to trigger the power failure event. In another aspect, the sensing circuit signal from the sensing circuit 126 may indicate that there is not enough power to operate the flash memory circuits 112A-N based on a second threshold, the second threshold being below the power supply level of the flash memory circuits by a predetermined percentage (e.g., 10%). For example, the sensing circuit 126 may detect the voltage in the flash memory circuits 112A-N to trigger the power failure event when the sensed voltage may have dropped from a 3.3V power supply to approximately 3.0V. In this example, the second threshold corresponds to the level of 3.0 V and is greater than the minimum operating voltage of the flash memory circuits 112A-N (e.g., 2.7 V). In this regard, the power failure event is triggered before the voltage level reaches the minimum operating voltage and not when the voltage level has dropped below the minimum operating voltage.In some aspects, the nonvolatile memory circuits 112A-N are powered by the internal power source 128 when the power failure event has occurred. The sensing circuit signal may cause the internal power supply 128 to supply power to the controller 114. In this regard, the controller 114 writes data from volatile memory, such as the RAM 122, to the nonvolatile memory circuits (e.g., 112A-N) before the power from the internal power source 128 falls below a predetermined threshold.In step 204, the controller 114 determines whether a first type of memory commands (e.g., write commands and / or erase commands) are executed in the nonvolatile memory circuits 112A-N. For example, command queues may be visible to the controller 114 so that it has knowledge of which non-volatile memory device or array of non-volatile memory devices is executing the first type of memory commands. If the controller determines that write commands and / or erase commands are being executed, the process 200 continues to step 206. Otherwise, the process 200 is ended. In some aspects, the first type of memory instructions includes erase instructions. In other aspects, the first type of memory commands includes programming commands for writing a first type of data. The first type of data may include unacknowledged host data.The first type of data may also include parity data. For example, the controller 114 may implement a RAID (Redundant Array of Low-Cost Disks) storage scheme via the flash memory circuits 112A-N. A bitwise function, such as an XOR function, may be performed on a set of host data to generate parity data that is written to the flash memory circuits 112A-N along with the set of host data. Should a first type of memory command for writing parity data be suspended or terminated in a power failure event, the parity data may be recomputed from the set of host data and written to the flash memory circuits 112A-N after the next power up of the data storage device.In step 206, the controller determines by reference to the command queues that nonvolatile memory circuits (e.g., 112A-N) execute the first type of memory commands when it is determined that the power failure event has occurred. In step 208, the controller issues a stop command to the particular nonvolatile memory circuits to suspend or end execution of the first type of memory commands.In one or more implementations, the controller 114 outputs a second type of memory commands to the particular non-volatile memory circuits. In some aspects, the second type of memory commands includes programming commands for writing a second type of data. The second type of data may consist of system data and / or acknowledged host data.In one or more implementations, the stop command includes a suspend command to suspend execution of the first type of memory commands. In this regard, a suspended first type of memory commands may be resumed in response to a subsequent command from the controller 114. In other implementations, the stop command includes a terminate command to terminate execution of the first type of memory commands such that the terminated commands may not be resumed or restored by the controller 114 in a subsequent write command.FIG. 3 illustrates example non-volatile memory circuits distributed over different channels in an example data storage device 110, according to one or more implementations. However, not all of the illustrated components may be required, and one or more implementations may include additional components not shown in the figure. Variations in the arrangement and type of components may be made without departing from the spirit or scope of the claims as set forth herein. Additional components, other components, or fewer components may be provided.The example data storage device 110 includes the interface 124, the controller 114, the bus 111, the channels 113A- 113N, and one or more flash memory circuits 112A-N. Flash memory circuits 112A-N each include one or more physical blocks (e.g., 302A-P) of flash memory, which may also be referred to as blocks and which are discussed further below with reference to FIG. 4.As shown in FIG. 3, channel 113A couples flash memory circuits 112A to bus 111, channel 113B couples flash memory circuits 112B to bus 111, channel 113C couples flash memory circuits 112C to bus 111, and channel 113N couples flash memory circuits 112N to bus 111. However, after the flash memory circuit 112A receives the data, the flash memory circuit 112A may be in a busy state during which the flash memory circuit 112A may not receive additional read and / or write commands. Thus, the number of flash memory circuits 112A-N that are simultaneously in the busy state may constrain the data storage device 110. The other channels 113B-N may operate in a similar manner.For purposes of explanation, the data storage device 110 of FIG. 3 is shown to include four channels 113A-N, and each of the channels 113A-N is shown to be communicatively coupled to the flash memory circuits 112A-N. However, the data storage device 110 may include any number of channels, such as 8, 16, 32. Likewise, each of the channels 113A-N may be communicatively coupled to any number of the flash memory circuits 112A-N, such as any number. In one or more implementations, one or more of the channels 113A-N may be communicatively coupled to different numbers of the flash memory circuits 112A-N.FIG. 4 illustrates example blocks of non-volatile memory circuits distributed over different channels in an example data storage device 110, according to one or more implementations. However, not all of the illustrated components may be required, and one or more implementations may include additional components not shown in the figure. Variations in the arrangement and type of components may be made without departing from the spirit or scope of the claims as set forth herein. Additional components, other components, or fewer components may be provided.For purposes of explanation, the data storage device 110 of FIG. 3 is illustrated as including a flash memory circuit 112A. Flash memory circuits 112A include one or more physical blocks 202A-D of flash memory, which may also be referred to as blocks 202A-D. Each of the physical blocks 202A-D may include one or more physical pages 402A-D of the flash memory. The individual physical pages 402A-D of the physical blocks 202A-D may be the smallest unit that can be written to the flash memory circuits 112AN, and may be, for example, 8-16 kilobytes in size. In one or more implementations, flash memory circuit 112A may have a size of 16 gigabytes and may include 4252 blocks, each of which includes 256 pages, each page storing 17760 bytes.Implementations within the scope of the present disclosure may be implemented in part or in whole using a tangible computer readable storage medium (or multiple tangible computer readable storage media of one or more types) encoding one or more instructions. The particular computer readable storage medium may also be non-transitory.The computer readable storage medium may be any storage medium upon which a general purpose or special purpose computing device can read, write, or otherwise access, including any processing electronics and / or processing circuitry that can execute instructions. For example, the computer readable medium may include, but is not limited to, any volatile semiconductor memory such as RAM, DRAM, SRAM, T-RAM, Z-RAM, and TTRAM. The computer readable medium may also include any non-transitory semiconductor memory, such as ROM, PROM, EPROM, EEPROM, NVRAM, flash, nvSRAM, FeRAM, FeRAM, MRAM, PRAM, CBRAM, SONOS, RRAM, NRAM, Racetrack memory, FJG, and Millipede memory.Further, the computer readable storage medium may include any non-semiconductor memory, for example, an optical disk storage, a magnetic disk storage, a magnetic tape, other magnetic storage devices, or any other medium capable of storing one or more instructions. In some implementations, the particular computer readable storage medium may be directly coupled to a computing device, while in other implementations, the particular computer readable storage medium may be indirectly coupled to a computing device, e.g., via one or more wired connections, one or more wireless connections, or any combination thereof.Instructions may be directly executable or may be used to develop executable instructions. For example, instructions may be implemented as executable or non-executable machine code or as high-level language instructions that may be compiled to generate executable or non-executable machine code. Furthermore, commands can also be realized as data or contain data. Computer-executable instructions may also be organized in any format, including routines, subroutines, programs, data structures, objects, modules, applications, applets, functions, etc. As will be appreciated by those skilled in the art, details including, but not limited to, the number, structure, order, and organization of the instructions may vary substantially without altering the underlying logic, function, processing, and output.Although the above discussion relates primarily to microprocessors or multi-core processors executing software, one or more implementations are performed by one or more integrated circuits, such as application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). In one or more implementations, such integrated circuits execute instructions stored in the circuit itself.Those skilled in the art will appreciate that the various illustrative blocks, modules, elements, components, methods, and algorithms described herein may be implemented as electronic hardware, computer software, or combinations of both. To illustrate this interoperability of hardware and software, various illustrative blocks, modules, elements, components, methods, and algorithms have been generally described above in terms of functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Skilled technicians may implement the described functionality in various ways for each particular application. Various components and blocks may be arranged differently (e.g., arranged in a different order or otherwise divided) without departing from the scope of the present technology.It should be understood that any specific order or hierarchy of blocks in the disclosed processes is an illustration of example approaches. It should be understood that the specific order or hierarchy of blocks in the processes may be rearranged based on design preferences or that all illustrated blocks are executed. Any of the blocks may be executed simultaneously. In one or more implementations, multi-tasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together into a single software product or packaged into multiple software products.As used in this specification and claims of this application, the terms "base station", "receiver", "computer", "server", "processor" and "memory" all refer to electronic or other technological devices. These terms exclude persons or groups of persons. For purposes of description, the term "display" or "display" means display on an electronic device.As used herein, the phrase "at least one / r / s of" preceding a sequence of elements with the terms "and" or "or" to separate any of the elements modifies the list as a whole, rather than every member of the list (i.e., every element). The term "at least one / r / s of" does not require the selection of at least one of each listed item; rather, the term allows a meaning in which at least one of any of the items includes and / or at least one of any combination of the items and / or at least one of each of the items. For example, the terms "at least one of A, B, and C" or "at least one of A, B, or C" refer to only A, only B, or only C, respectively; any combination of A, B, and C; and / or at least one of each of A, B, and C.The predicate words "configured to", "operable to", and "programmed to" do not imply any particular material or intangible modification of a subject, but rather are intended to be used interchangeably. In one or more implementations, a processor configured to monitor and control an operation or component may also mean that the processor is programmed to monitor and control the operation or the processor is operable to monitor and control the operation. Similarly, a processor configured to execute code may be understood as a processor programmed to execute code or operable to execute code.Phrases such as an aspect, the aspect, another aspect, some aspects, one or more aspects, an implementation, the implementation, another implementation, some implementations, one or more implementations, an implementation, the implementation, another implementation, some implementations, one or more implementations, a configuration, the configuration, another configuration, some configurations, one or more configurations, the present technology, the disclosure, the present disclosure, other modifications, and the like are for ease of illustration and do not imply that a disclosure related to such phrases is essential to the present technology or that such a disclosure applies to all configurations of the present technology. A disclosure related to such phrases may apply to all configurations or to one or more configurations. A disclosure related to such phrases may provide one or more examples. A phrase such as an aspect or some aspects may refer to one or more aspects and vice versa, and this applies similarly to other previous phrases.The word "exemplary" is used herein to mean "serving as an example, instance, or illustration.". Any implementation described herein as "exemplary" or "example" is not necessarily to be considered preferred or advantageous over other implementations. Moreover, to the extent that the term "include", "have", or the like is used in the specification or claims, such term is intended to be inclusive in a manner similar to the term "include", such as "include" being interpreted when used as a transitional word in a claim.All structural and functional equivalents to the elements of the various aspects described in this disclosure, which are known or will become known to those skilled in the art later, are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is expressly recited in the claims. No claim element is intended to be construed in accordance with the provisions of 35 U.S.C. §112, sixth paragraph, unless the element is expressly listed using the phrases "means for" or, in the case of a method claim, using the phrase "step for.".The foregoing description has been provided to enable those skilled in the art to practice the various aspects described herein. Various modifications of these aspects will be readily apparent to those skilled in the art and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but are intended to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean "one and only one" unless specifically stated, but rather "one or more.". Unless specifically stated otherwise, the term "some" refers to one or more. Male pronouns (e.g., his) include the female and neutral sex (e.g., her and his) and vice versa. Any headers and intermediate headers are for clarity only and do not limit the disclosure of the subject matter.

Claims

A data storage device (110) comprising: non-volatile memory circuits (112A-N); a sensing circuit (126) configured to detect a voltage of the non-volatile memory circuits (112A-N) and trigger a power failure event based on a threshold for the voltage; and a controller (114) configured to: determine (202) that the power failure event has occurred; in response to the determination that the power failure event has occurred, determine (206) which of the non-volatile memory circuits (112A-N) are executing a first type of memory commands; and issue (208) a stop command to the determined non-volatile memory circuits to stop execution of the first type of memory commands.The data storage device of claim 1, wherein the first type of storage instructions include instructions for writing parity data generated for a set of host data; wherein the stop instruction includes instructions for suspending or terminating the writing of parity data; and wherein the controller (114) is configured to recompute the parity data from the set of host data after the next startup of the data storage device (110).The data storage device of claim 1, wherein the first type of memory commands includes erase commands.The data storage device of claim 1, wherein the first type of memory commands includes programming commands for writing a first type of data.The data storage device of claim 4, wherein the first type of data includes unacknowledged host data.The data storage device of claim 1, wherein the controller (114) is further configured to: issue a second type of memory commands to the particular nonvolatile memory circuits in response to the issued stop command.The data storage device of claim 6, wherein the second type of memory commands includes programming commands for writing a second type of data.The data storage device of claim 7, wherein the second type of data includes system data and / or acknowledged host data.The data storage device of claim 1, wherein the stop command includes a suspend command to suspend execution of the first type of memory commands, wherein the suspended first type of memory commands is resumed in response to a subsequent command from the controller (114).The data storage device of claim 1, wherein the stop command includes a completion command to complete execution of the first type of memory commands, wherein the completed first type of memory commands is not resumed in response to a subsequent command from the controller (114).The data storage device of claim 1, wherein the controller (114) is further configured to: write data from a volatile memory to the nonvolatile memory circuits (112A-N) before power from an internal power source (128) falls below a predetermined threshold, the nonvolatile memory circuits being powered by the internal power source (128) when the power failure event has occurred.The data storage device of claim 11, wherein the internal power source (128) includes a battery or a capacitive element.The data storage device of claim 1, wherein the determined nonvolatile memory circuits transition from a programming state to a suspend state based on the stop command issued, wherein the determined nonvolatile memory circuits transition from the suspend state back to the programming state based on a subsequent programming command from the controller (114).The data storage device of claim 1, wherein the determined nonvolatile memory circuits transition from an erase state to a completion state based on the issued stop command, wherein the determined nonvolatile memory circuits transition from the completion state back to the erase state based on a subsequent erase command from the controller (114).A system, comprising: a plurality of flash memory circuits (112A-N); a sensing circuit (126) configured to detect a voltage of the flash memory circuits (112A-N) and trigger a power failure event based on a threshold for the voltage; a random access memory (RAM); and a controller (114) communicatively coupled to the plurality of flash memory circuits (112A-N), the controller (114) configured to: determine (202) that the power failure event has occurred; in response to determining that the power failure event has occurred, determine which of the plurality of flash memory circuits (112A-N) executes an erase command or a program command; and stopping execution of either the erase command or the program command based on a stop command output to the specific flash memory circuits.The system of claim 15, wherein the controller (114) is further configured to: issue a write command to the particular flash memory circuits in response to the issued stop command; and write data to at least one of the plurality of flash memory circuits (112AN) in response to the issued write command before power from an internal power source (128) falls below a predetermined threshold.The system of claim 16, wherein the controller (114) is further configured to: initiate a subsequent programming command to the particular flash memory circuits to resume the stopped programming command.The system of claim 16, wherein the particular nonvolatile memory circuits transition from a first state to a second state based on the stop command issued, the particular nonvolatile memory circuits transition from the second state back to the first state based on a subsequent command from the controller (114), the first state including a programming state and the second state including a suspend state, the first state including an erase state and the second state including a completion state.A method comprising: determining (202) that a power failure event has occurred using a sensing circuit (126) configured to detect a voltage of flash memory circuits (112A-N) in a data storage device (110) and trigger the power failure event based on a threshold for the voltage; in response to determining that the power failure event has occurred, determining which of the flash memory circuits in the data storage device (110) execute an erase command or a program command; and issuing a stop command to the determined flash memory circuits to end the erase command or to suspend the program command.The method of claim 19, further comprising: issuing a write command to the particular flash memory circuits in response to the issued stop command; and writing data to at least one of the plurality of flash memory circuits (112AN) in response to the issued write command before power from an internal power source (128) falls below a predetermined threshold.

Images