Semiconductor package with low-parasitic connection to a passive device and method for assembling a semiconductor assembly

Abstract

comprising a semiconductor assembly (100): a semiconductor package (102) comprising a first and a second transistor chip (118, 120) embedded in a package body, wherein the first and the second transistor chip (118, 120) are arranged side by side in the package body, such that a first load terminal (122) of the first transistor chip (118) faces an upper surface of the package body, and such that a second load terminal (124) of the second transistor chip (120) faces the upper surface of the package body, and a discrete capacitor (104) which is mounted on the semiconductor package (102) such that a first terminal of the discrete capacitor (104) is directly above and electrically connected to the first load terminal (122) of the first semiconductor chip (118), and such that a second terminal of the discrete capacitor (104) is directly above and electrically connected to the second load terminal (124) of the second semiconductor chip (120); wherein the first and second transistor chips (118, 120) are each vertical devices, and wherein a vertical orientation of the first transistor chip (118) is opposite to that of the second transistor chip (120).

Description

background

[0001] The invention relates to semiconductor assemblies and a method for assembling a semiconductor device.

[0002] Power modules are used in many applications, such as automotive and industrial applications. A power module can contain power devices designed to control high voltages and / or currents, such as MOSFETs (metal-oxide semiconductor field-effect transistors), IGBTs (insulated-gate bipolar transistors), diodes, etc., and driver devices configured to control these power devices. A power module can also contain passive electrical elements, such as inductors and capacitors, which improve performance, for example, power efficiency and switching speed.

[0003] From US 2020 / 0 219 846 A1, a multi-chip package power module is known which has two chips arranged side by side. Several input capacitors are arranged above the two chips and are connected to the chips via a connecting line and conductive vias. An insulating encapsulation material surrounds the chips and the conductive vias.

[0004] From DE 10 2018 202 484 A1, a power electronics arrangement is known which comprises two half-bridge modules and a capacitor, which are mounted on a printed circuit board. Conductors are arranged in the printed circuit board such that the half-bridge modules are connected in parallel and to the capacitor. Each half-bridge module has a housing with a cooling side.

[0005] It is desirable to provide a power module with high performance, e.g., high peak efficiency and high load efficiency, while maintaining a small footprint, and which has robust electrical connections. Summary

[0006] It is an object of the invention to provide an efficient semiconductor assembly. This object is achieved by means of the subject matter according to the independent claims. Further embodiments are provided by means of the dependent claims.

[0007] A semiconductor assembly is disclosed. According to one embodiment, the semiconductor assembly comprises a semiconductor package having a first and a second transistor chip embedded in a package body, wherein the first and the second transistor chip are arranged side by side in the package body, such that a first load terminal of the first transistor chip faces an upper surface of the package body, and such that a second load terminal of the second transistor chip faces the upper surface of the package body, and a discrete capacitor mounted on the semiconductor package, such that a first terminal of the discrete capacitor is directly across and electrically connected to the first load terminal of the first semiconductor chip, and such that a second terminal of the discrete capacitor is directly across and electrically connected to the second load terminal of the second semiconductor chip.The first and second transistor chips are each vertical devices, with the vertical orientation of the first power transistor chip being opposite to that of the second power transistor chip.

[0008] Individually or in combination, the first and second transistor chips are each vertical devices, wherein a vertical orientation of the first power transistor chip is opposite to that of the second power transistor chip.

[0009] The semiconductor package, individually or in combination, further comprises a first structured metallization layer applied to the upper surface of the package body, wherein the first structured metallization layer has a first bond pad which is directly above and electrically connected to the first load terminal of the first semiconductor chip, and a second bond pad which is directly above and electrically connected to the second load terminal of the second semiconductor chip.

[0010] Either individually or in combination, the first terminal of the discrete capacitor is bonded conductively to the first bond pad, and the second terminal of the discrete capacitor is bonded conductively to the second bond pad.

[0011] The semiconductor package, individually or in combination, further comprises a second structured metallization layer applied to a lower surface of the package body opposite the upper surface of the package body, wherein the second structured metallization layer has a third bond pad electrically connected to the first bond pad by means of a first via, and a fourth bond pad electrically connected to the second bond pad by means of a second via, and wherein both of the first and second transistor chips are located laterally between the first and second vias.

[0012] The semiconductor assembly, individually or in combination, further comprises a carrier which has an electrically insulating substrate and a plurality of semiconductor packages which are mounted on the carrier, wherein the first bond pads of each of the semiconductor packages are electrically connected to each other by the plurality by means of a first metal connection structure, and wherein the second bond pads of each of the semiconductor packages are electrically connected to each other by the plurality by means of a second metal connection structure.

[0013] Individually or in combination, one or both of the first and second metal compound structures are metal bridges that are arranged completely over the majority of the semiconductor packages.

[0014] Individually or in combination, one or both of the first and second metal compound structures are metal clips that are connected between the semiconductor packages and the substrate.

[0015] According to another embodiment, the semiconductor assembly comprises a semiconductor package which includes a power converter circuit which is monolithically integrated in a package body, wherein the power converter circuit has a first load terminal and a second load terminal, wherein the first and the second load terminal each face an upper surface of the package body, and a discrete capacitor which is mounted on the semiconductor package such that a first terminal of the discrete capacitor is directly above and electrically connected to the first load terminal, and such that a second terminal of the discrete capacitor is directly above and electrically connected to the second load terminal.The power converter circuit comprises a first and a second transistor chip embedded in the package body, wherein the first and second transistor chips are each vertical devices, and wherein a vertical orientation of the first power transistor chip is opposite to that of the second power transistor chip.

[0016] Individually or in combination, the power converter circuit comprises a first and a second transistor chip embedded in the package body, wherein the first and second transistor chips are each configured as a discrete power MOSFET, the first load terminal corresponding to a drain terminal of the first transistor chip, and the second load terminal corresponding to a source terminal of the second transistor chip.

[0017] Individually or in combination, the power converter circuit is configured as a half-bridge circuit, wherein the first transistor chip is a high-side switch of the half-bridge circuit, and wherein the second transistor chip is a low-side switch of the half-bridge circuit.

[0018] Individually or in combination, the first terminal of the discrete capacitor is a metal contact or conductor which is bonded conductively to the first load terminal, and wherein the second terminal of the discrete capacitor is a metal contact or conductor which is bonded conductively to the second load terminal.

[0019] A method for assembling a semiconductor device is disclosed.According to one embodiment, the method comprises providing a semiconductor package comprising a first and a second transistor chip embedded in a package body, wherein the first and the second transistor chip are arranged side by side in the package body, such that a first load terminal of the first transistor chip faces an upper surface of the package body, and such that a second load terminal of the second transistor chip faces the upper surface of the package body, and mounting a discrete capacitor on the semiconductor package, such that a first terminal of the discrete capacitor is directly above and electrically connected to the first load terminal of the first semiconductor chip, and such that a second terminal of the discrete capacitor is directly above and electrically connected to the second load terminal of the second semiconductor chip.The first and second transistor chips are each vertical devices, with the vertical orientation of the first power transistor chip being opposite to that of the second power transistor chip.

[0020] The semiconductor package, individually or in combination, has a first and a second bond pad applied to an upper surface of the semiconductor package, wherein the first bond pad is directly above and electrically connected to the first load terminal of the first semiconductor chip, wherein the second bond pad is directly above and electrically connected to the second load terminal of the second semiconductor chip, and wherein the mounting of the discrete capacitor comprises directly attaching the first terminal of the discrete capacitor to the first bond pad and directly attaching the second terminal of the discrete capacitor to the second bond pad.

[0021] Either individually or in combination, directly attaching the first terminal of the discrete capacitor to the first bond pad involves soldering the first terminal of the discrete capacitor to the first bond pad, and directly attaching the second terminal of the discrete capacitor to the second bond pad involves soldering the second terminal of the discrete capacitor to the second bond pad.

[0022] Individually or in combination, the method further comprises providing a circuit carrier having an electrically insulating substrate, mounting a plurality of semiconductor packages on the circuit carrier, providing a first and a second metal interconnect structure, electrically connecting the first bond pads of the semiconductor packages to each other using the first metal interconnect structure, electrically connecting the second bond pads of the semiconductor packages to each other using the second metal interconnect structure, and mounting one of the discrete capacitors onto each of the plurality of semiconductor packages.

[0023] Individually or in combination, providing the first and second metal interconnect structure includes providing a first and a second elongated metal web, wherein the electrical connecting of the first bond pads of the semiconductor packages includes arranging the first metal web over the first bond pad of each of the plurality of semiconductor packages, and wherein the electrical connecting of the second bond pads of the semiconductor packages includes arranging the second metal web over the second bond pad of each of the plurality of semiconductor packages.

[0024] Individually or in combination, the provision of the first and second metal connection structure comprises the provision of a first and a second metal clip, wherein the electrical connection of the first bond pads of the semiconductor packages comprises an electrical connection of the first bond pad of each of the majority semiconductor packages to the support using one of the first metal clips, and wherein the electrical connection of the second bond pads of the semiconductor packages comprises an electrical connection of the second bond pad of each of the majority semiconductor packages to the support using one of the second metal clips.

[0025] In most semiconductor packages, the discrete capacitor is mounted on top of the first and second metal clips, either individually or in combination.

[0026] Individually or in combination, providing the first and second elongated metal clips comprises providing a clip frame which includes groups of the first and second metal clips, each of which is attached to a peripheral structure, wherein electrically connecting the first bond pads of the semiconductor packages and electrically connecting the second bond pads of the semiconductor packages comprises arranging the clip frame over the majority of the semiconductor packages, and wherein the method further comprises separating the first and second metal clips from the peripheral structure. Brief description of the characters

[0027] The elements in the drawings are not necessarily to scale relative to one another. Identical reference numerals denote corresponding similar parts. The features of the various embodiments shown can be combined, provided they are not mutually exclusive. The embodiments are illustrated in the drawings and are described in detail below. Fig. 1, which the Fig. 1A and Fig. Figure 1B shows a cross-sectional view of a semiconductor assembly comprising a semiconductor package and a passive device, according to exemplary embodiments. Fig. Figure 2 shows a cross-sectional view of a semiconductor assembly comprising a semiconductor package and a passive device, according to one embodiment. Fig. Figure 3 shows a top view of a semiconductor assembly comprising several semiconductor packages and metal interconnect structures connected between the semiconductor packages, according to one embodiment. Fig. 4, which the Fig. 4A and Fig. Figure 4B shows a cross-sectional view of a semiconductor assembly comprising a semiconductor package, a passive device, and metal clips, according to embodiments. Fig. 5, which the Fig. 5A and Fig. Figure 5B shows a top view of a semiconductor assembly comprising a semiconductor package, a passive device, and metal clips, according to embodiments. Fig. Figure 6 shows a clip frame for providing multiple metal clips, according to one embodiment. Fig. 7, which the Fig. Figures 7A-7D show selected process steps for forming a semiconductor assembly comprising a semiconductor package and a passive device, according to one embodiment. Fig. Figure 8 shows a cross-sectional view of a semiconductor assembly comprising a semiconductor package and a passive device, according to one embodiment. Fig. 9, which the Fig. Figures 9A to 9D show selected process steps for forming a semiconductor assembly comprising a semiconductor package and a passive device mounted thereon, according to one embodiment. Detailed description

[0028] Embodiments of a semiconductor assembly with an advantageous arrangement of a discrete passive device are described here, which is mounted on top of a semiconductor package. The semiconductor package comprises a first and a second semiconductor chip, which are embedded within an encapsulation body of the semiconductor package. Advantageously, the terminals of the discrete passive device are located directly above the terminals of the semiconductor chips, to which they are electrically connected. This arrangement minimizes the length of conductors between the discrete passive device and the terminals of the semiconductor chips, thereby reducing the parasitic influence of the electrical connections and resulting in improved performance.

[0029] Referring to Fig. Figure 1 shows a semiconductor assembly 100 according to an exemplary embodiment. The semiconductor assembly 100 comprises a semiconductor package 102 and a discrete passive device 104 mounted thereon. The semiconductor package 102 includes a plurality of semiconductor chips 106 embedded in a package body. The discrete passive device 104 is electrically connected to the terminals of the semiconductor chips 106, which face a lower surface 108 and are located away from the discrete passive device 104. Vertical through-contact structures 110, extending through the thickness of the semiconductor package 102, are used to complete the electrical connection between the discrete passive device 104 and the terminals of the semiconductor chips 106.

[0030] In the exemplary embodiment, which is described in Fig. As shown in Figure 1A, the discrete passive device 104 is configured as a surface-mounted device, wherein the terminals of the discrete passive device 104 are coplanar with a lower surface of the device. The embodiment shown in Figure 1A Fig. The one shown in 1B is similar to the one shown in Fig. Figure 1A shows the discrete passive device 104, except that it has conductors 112 extending away from the body of the discrete passive device 104. The conductor configuration provides a vertical clearance which can be used to provide a metal bridge 114 on the upper surface of the semiconductor package 102. The metal bridge 114 can be used to reduce the electrical resistance between two terminals of a semiconductor package 102.

[0031] Referring to Fig. Figure 2 shows a semiconductor assembly 100 according to one embodiment. The semiconductor assembly 100 of Fig. 2 differs from that of Fig. 1 in that the terminals of the semiconductor chips, which are electrically connected to the discrete passive device 104, face an upper surface 116 of the semiconductor package 102, and therefore face the discrete passive device 104. This significantly shortens the distance of the electrical connection between the passive device and the semiconductor chips and eliminates the need for connecting elements, for example, vias between the passive device and the semiconductor chips. This reduces the parasitic influence (e.g., inductance, resistance, etc.) of these electrical connections and thus improves the performance of the semiconductor assembly 100.

[0032] According to one embodiment, the semiconductor package 102 is a laminated or so-called "chip-embedded" package. A chip-embedded package has an encapsulation body formed from several constituent layers of dielectric material laminated (stacked) on top of each other. This type of package differs from a molded package, where the encapsulation is provided by a monolithic area of ​​molding compound that encapsulates the semiconductor chip and associated electrical connectors, e.g., bond wires, clips, etc. In a chip-embedded package, each constituent laminate layer can generally comprise any dielectric material suitable for encapsulating a semiconductor device. Examples of such dielectric materials include epoxy materials, mixed epoxy and glass fiber materials, for example, FR-4, FR-5, CEM-4, etc.and resin materials, for example, bismaleimide triazine (BT) resin. A chip-embedded package may also contain multiple layers of metallization, e.g., copper, aluminum, etc., and alloys thereof, formed on top of at least some of the constituent laminate layers. These layers of metallization may be structured to form internal interconnects within the package body and the bond pads exposed on the outer surfaces of the package body. Conductive vias, e.g., vias containing tungsten, copper, etc., may be provided in openings extending through the constituent layers of the dielectric material to provide a vertical electrical connection.Due to the electrical connection provided by the internal structured metallization, a chip-embedded package does not require a conductor frame or electrical connectors, such as bond wires or clips. Therefore, the semiconductor package 102 can be free of a chip pad that holds the semiconductor chips and / or free of conductive conductors formed from the same conductor frame structure as a chip pad.

[0033] According to one embodiment, the semiconductor package 102 comprises a first and a second transistor chip 118, 120, which are embedded in the package body. The first and second transistor chips 118, 120 are arranged side by side in the package body. This means that the first and second transistor chips 118, 120 are arranged in a non-overlapping manner. Each of the first and second transistor chips 118, 120 has a first load terminal 122, a second load terminal 124, and a control terminal 126. In a generally known manner, the first and second transistor chips 118, 120 are configured to control a conductive connection between the first load terminal 122 and the second load terminal 124 via the control terminal 126.For example, the first and second transistor chips 118, 120 can be configured as MOSFET devices, with the first and second load terminals 122, 124 corresponding to the source and drain terminals (or vice versa), and the control terminal 126 corresponding to the gate terminal. In another embodiment, the first and second transistor chips 118, 120 can be configured as IGBT devices, with the first and second load terminals 122, 124 corresponding to the collector and emitter terminals (or vice versa), and the control terminal 126 corresponding to the gate terminal.

[0034] According to one embodiment, the first and second transistor chips 118, 120 are configured as discrete power transistors. A discrete power transistor is a switching device configured to accept voltages of at least 100 V (volts), and more commonly on the order of 600 V, 1200 V or more, and / or configured to accept currents of at least 1 A (ampere), and more commonly on the order of 10 A, 50 A, 100 A or more. Discrete power transistors can be, for example, MOSFETs (metal-oxide semiconductor field-effect transistors), IGBTs (insulated-gate bipolar transistors), and HEMTs (high-electron mobility transistors). The first and second transistor chips 118, 120 can internally incorporate several of these device types connected in parallel. The first and second transistor chips 118, 120 can be made of IV semiconductor materials, e.g., B. Silicon, silicon germanium, silicon carbide, etc.and / or contain type III-V semiconductor materials, e.g. gallium nitride, gallium arsenide, etc.

[0035] The first and second transistor chips 118, 120 can be arranged such that a first load terminal 122 of the first transistor chip faces an upper surface 118 of the package body, and such that a second load terminal 124 of the second transistor chip faces the upper surface 118 of the package body. The first and second transistor chips 118, 120 can be identical devices such that the first load terminal 122 of the first transistor chip 118 is the opposite terminal to the second load terminal 124 of the second transistor chip 120. For example, the first load terminal 122 of the first transistor chip 118 can be the source terminal of a MOSFET or the collector terminal of an IGBT, whereas the second load terminal 124 of the second transistor chip 120 can be the drain terminal of a MOSFET or the emitter terminal of an IGBT, or vice versa.

[0036] According to one embodiment, the first and second transistor chips 118, 120 are each configured as vertical devices. A vertical device is configured for current flow between a main surface and an oppositely oriented rear surface of the semiconductor chip. This means that the load terminals are located on opposite sides of the semiconductor chip. For example, the first and second transistor chips 118, 120 can each have a main surface with a control terminal 126 and a first load terminal 122 arranged thereon, and a rear surface with a second load terminal 124 arranged thereon.

[0037] According to one embodiment, the vertical orientation of the first transistor chip 118 is opposite to that of the second transistor chip 120. This means that the first and second transistor chips 118, 120 are arranged such that their load terminals face opposite directions. For example, as shown, the main surface of the first transistor chip 118 faces the upper surface 118 of the package body, whereas the main surface of the second transistor chip 120 faces the lower surface 108 of the package body.

[0038] The semiconductor package 102 can have a first and a second bond pad 128, 130, which are applied to an upper surface 118 of the package body. The first bond pad 128 is an externally accessible contact surface for the first load terminal 122 of the first transistor chip 118, and the second bond pad 130 is an externally accessible contact surface for the second load terminal 124 of the second transistor chip 120. The semiconductor package 102 can have a first structured metallization layer, which is applied to the upper surface 118 of the package body, wherein the first and the second bond pads 128, 130 correspond to structured sections of this first structured metallization layer. These structured sections can directly contact the first load terminal 122 of the first transistor chip 118 and the second load terminal 124 of the second transistor chip 120, or can be connected by means of a via structure.In another embodiment, the first and second bond pads 128, 130 can correspond to sections of the first load terminal 122 of the first transistor chip 118 and the second load terminal 124 of the second transistor chip 120 (i.e., chip-level bond pads) which are directly exposed from the encapsulation body of the semiconductor package 102.

[0039] According to one embodiment, the semiconductor package 102 includes a power converter circuit which is monolithically integrated into the package body. As used herein, the term power converter circuit refers to any type of circuit which includes one or more switching devices and is configured to change the signal characteristics of an electrical signal by periodically switching the power switching device or devices. Power converter circuits include, for example, DC-to-DC converters, DC-to-AC converters, AC-to-DC converters, and AC-to-AC converters. Power converter circuits can be configured to convert between AC and DC and vice versa, to change the voltage of a signal, to change the frequency of a signal, or any combination thereof.Exemplary circuit topologies for power converter circuits include buck converters, boost converters, buck-boost converters, and inverters, to name a few. Power converter circuits can have single-phase circuit topologies, multi-phase topologies (e.g., three-phase circuit topologies), and multi-stage circuit topologies, with one or more switching devices provided for each phase or stage.

[0040] According to one embodiment, the semiconductor package 102 comprises a half-bridge circuit. A half-bridge circuit refers to a specific type of circuit topology that includes a high-side switch connected in series with a low-side switch. One load terminal of the high-side switch (e.g., the drain) is connected to a first DC voltage (positive potential / VDD), one load terminal of the low-side switch (e.g., the source) is connected to a second DC voltage (e.g., negative potential or GND), and the remaining two load terminals (e.g., the source of the high-side switch and the drain of the low-side switch) are connected together to form the output of the half-bridge circuit. The inputs of the high-side and low-side switches (e.g., the gate terminals) can be controlled according to a power control scheme (e.g.,Pulse-width modulation (PWM) is used to generate a desired voltage and frequency at the output of the half-bridge circuit. The power converter circuits described above can incorporate one or more of these half-bridge circuits to perform any of the power conversion operations described above.

[0041] In an embodiment where the semiconductor package 102 comprises a half-bridge circuit, the first transistor chip 118 can correspond to a high-side switch of the half-bridge circuit, and the second transistor chip 120 can correspond to a low-side switch of the half-bridge circuit. The first load terminal 122 of the first transistor chip 118 can be a drain terminal connected to a first DC voltage terminal (e.g., positive potential / VDD), and the second load terminal 124 of the second transistor chip 120 can be a source terminal connected to a second DC voltage terminal (e.g., negative potential or GND) of the half-bridge circuit. The first load terminal 122 of the second transistor chip 120 and the second load terminal 124 of the first transistor chip 118 can form the output of the half-bridge circuit.For this purpose, the semiconductor package 102 can have a second structured metallization layer applied to the lower surface of the package body. The second structured metallization layer can have bond pads that provide electrical contact points to the first load terminal 122 of the second transistor chip 120 and the second load terminal 124 of the first transistor chip 118, in a manner similar to that described above. Optionally, the second structured metallization layer can have a section that forms a direct electrical connection between the first load terminal 122 of the second transistor chip 120 and the second load terminal 124 of the first transistor chip 118.Furthermore, the second structured metallization layer can have additional bond pads (not shown) which provide electrical access to the control terminals 126 of the first and second transistor chips 118, 120. These additional bond pads can be electrically connected to the control terminal 126 of the first and second transistor chips 118, 120 via internal vias and / or an internal structured metallization of the semiconductor package 102.

[0042] According to one embodiment, the semiconductor package 102 has a third bond pad 132, which is electrically connected to the first bond pad 128 via a first via 134, and a fourth bond pad 136, which is electrically connected to the second bond pad 130 via a second via 138. As a result, the second load terminal 124 of the first transistor chip 118 and the first load terminal 122 of the second transistor chip 120 are electrically accessible on a lower surface 108 of the package body. The third and fourth bond pads 132, 136 can be structured sections of the second structured metallization layer that forms the other bond pads on the lower surface 108 of the package body. The first and second vias 134, 138 can be integral parts of the semiconductor package 102 and may comprise copper, aluminum, tungsten, nickel, etc., and alloys or combinations thereof.As shown, the semiconductor package 102 can be configured such that both the first and second transistor chips 118, 120 are arranged laterally between the first and second vias 118, 120. As a result, a space-efficient arrangement is provided.

[0043] More generally, the semiconductor package 102 can include semiconductor chips embedded within the package body. These chips can have a wide variety of device configurations, such as discrete device configurations (e.g., a MOSFET, an IGBT, a diode, etc.) or integrated circuit configurations (e.g., a controller, a driver, etc.). These semiconductor chips can be configured as vertical or lateral devices, which are configured to control a current flowing parallel to a main surface of the respective semiconductor chip. In the case of a power converter circuit, for example, a half-bridge circuit, the semiconductor package 102 can include a driver chip configured to control the switching operation of the high-side and low-side switches. The semiconductor package 102 can include one or more passive devices (e.g., capacitors, inductors, resistors, etc.)., which are monolithically integrated within it, which can form part of the power converter circuit, e.g. for smoothing, impedance matching, resonance, etc.

[0044] The semiconductor assembly 100 further comprises a carrier 140. Generally speaking, the carrier 140 can be any electronic substrate configured to mechanically support multiple electronic components, e.g., semiconductor packages, passive components, heat sinks, etc., and can be configured to accommodate these electronic components or to provide electrical connections between them. In one embodiment, the carrier 140 is a printed circuit board (PCB). In this case, the carrier 140 can comprise a prepreg material, for example, FR-4, CEM-1, G-10, etc., and a structured metallization layer, e.g., a copper metallization layer, with conductive bond pads applied to an upper surface of the carrier 140. In another embodiment, the carrier 140 is a power electronics substrate.Examples of these power electronics substrates include, for example, DBC (directly bonded copper) substrates, AMB (active metal brazed) substrates, or IMS (insulated metal substrate) substrates. In the case of a power electronics substrate, the carrier 140 can comprise an electrically insulating substrate, e.g., a ceramic substrate, and a structured metallization layer bonded to the substrate.

[0045] The semiconductor package 102 can be mounted on the substrate 140, with each of the bond pads formed in the second structured metallization layer being electrically connected to corresponding bond pads (not shown) of the substrate 140. A conductive adhesive, for example a solder, sinter, conductive glue, etc., can be incorporated between the semiconductor package 102 and the substrate 140 to effect these electrical connections.

[0046] The semiconductor assembly 100 further comprises a discrete passive component 104, which is mounted on the upper surface 118 of the package body. The discrete passive component 104 has a first terminal 142, which is directly connected to and electrically linked with the first load terminal 122 of the first transistor chip 118, and a second terminal 144, which is directly connected to and electrically linked with the second load terminal 124 of the second transistor chip 120. These first and second terminals 142, 144 are exposed conductors of the discrete passive component 104, which represent the predefined impedance of the discrete passive component 104. As shown, the discrete passive component 104 can, for example, be configured as a so-called SMD (surface-mount device), wherein the first and second terminals 144 are planar metal contacts applied to a lower surface of the discrete passive component 104.Alternatively, the first and second terminals 142, 144 can be metal conductors extending away from the body of the discrete passive component 104.

[0047] The first terminal 142 of the discrete capacitor can be bonded to the first bond pad 128 using a conductive adhesive, and the second terminal 144 of the discrete capacitor can be bonded to the second bond pad 130 using a conductive adhesive. This means that the terminals of the discrete capacitor can be directly attached to the first and second bond pads 128 and 130 using a conductive adhesive material. The conductive adhesive material can be a solder, sintered material, conductive adhesive, etc.

[0048] Due to the arrangement of the discrete passive component 104 and the semiconductor chips, the parasitic influence (e.g., inductance, capacitance, resistance) of the conductive connections between the discrete passive component 104 and the semiconductor chips is minimized. Since the terminals of the discrete passive component 104 are directly above the load terminals of the semiconductor chips, and the only intermediate conductors required to complete the electrical connections are a conductive adhesive and the bond pads, the parasitic influence of these intermediate conductors is minimized.

[0049] In one embodiment, the discrete passive component 104 is a discrete capacitor. The capacitance of this capacitor can be used for a variety of purposes, such as impedance matching, power conversion, AC signal filtering, etc. In one particular embodiment, the semiconductor package 102 is configured as a power inverter circuit, with the discrete passive component 104 forming the DC link capacitor of the power inverter circuit. More generally, the discrete passive component 104 can be any type of passive component, such as a resistor, inductor, capacitor, etc., with a minimized parasitic influence of the electrical connections between the discrete passive component 104 and the semiconductor package 102 being preferred.

[0050] According to one embodiment, the semiconductor assembly 100 additionally comprises a first metal compound structure 146 and a second metal compound structure 148. The first and the second metal compound structures 146, 148 can comprise an electrically conductive metal, for example, copper, aluminum, gold, silver, zinc, nickel, tungsten, and any alloy or combination thereof. The first and the second metal compound structures 146, 148 can each be configured as elongated webs arranged only above the semiconductor package 102, an example of which is shown in the Fig. 2 and Fig. Figure 3 shows. Alternatively, the first and second metal compound structures 146, 148 can each be configured as metal clips connected between the semiconductor package 102 and the support 140, an example of which is shown in the Fig. 4 and Fig. Figure 5 shows that the first and second metal connection structures 146, 148 can be electrically connected to the first and second bond pads 128, 130, respectively, by means of the conductive adhesive.

[0051] Referring to Fig. Figure 3 shows a top view of a semiconductor assembly 100, which comprises a plurality of semiconductor packages 102 mounted on the carrier 140, according to one embodiment. Each of the semiconductor packages 102 can be identically configured and mounted on the carrier 140, according to any one of the embodiments described above. Fig. 2 are described. This arrangement can be used to form a multiphase or multistage power converter circuit. In this arrangement, each of the I / O signals and the power signals can be supplied to / from the semiconductor packages 102 via the carrier 140.

[0052] In this embodiment, the first and second metal interconnect structures 146, 148 are configured as elongated metal webs extending over a group of semiconductor packages 102. Furthermore, the first and second metal interconnect structures 146, 148 are arranged completely over each of the semiconductor packages 102 and thus do not contact the support 140. In this case, the first and second metal interconnect structures 146, 148 are used to reduce resistance and stabilize the DC signal distribution to each of the semiconductor packages 102 in the group.

[0053] Referring to Fig. Figure 4 shows a semiconductor assembly 100 according to another embodiment. The semiconductor assembly 100 is essentially identical to the one described with reference to the Fig. as described in Figures 2-3, except that the first and second metal connection structures 146, 148 are configured as metal clips instead of elongated metal ribs. Thus, a first metal clip 150 is arranged over the first bond pad 128, and a second metal clip 152 is arranged over the second bond pad 130. These metal clips can extend over several semiconductor packages 100, e.g., in a similar manner to the elongated metal ribs described in Figures 2-3. Fig. Figure 3 shows that these metal clips can be assigned to individual semiconductor packages 100. In either case, these metal clips reduce the resistance and stabilize the DC signal distribution to each semiconductor package 102 in a similar manner to that described above.

[0054] As in Fig. As shown in Figure 4A, the metal clips can be used to supplement the conductive connections provided by the first and second vias 134 and 138. Fig. As shown in Figure 4B, the metal clips alternatively allow the first and second vias 134, 138 in the semiconductor package 102 to be omitted, thereby reducing the footprint of the semiconductor package 102. One arrangement may be preferred over another depending on the weighting of performance considerations, for example, the required size of the discrete passive element (e.g., capacitance) and the electrical resistance for the DC signal connections.

[0055] Referring to Fig. Figure 5 shows a top view of the semiconductor assembly 100, which is shown with reference to Fig. 4 is described according to two different embodiments. As shown, the first and second metal clips 150, 152 can have different geometries, which are adapted to a specific geometry of the discrete passive component 104. In the embodiment of Fig. 5A The first and second metal clips 150, 152 have recessed inner edge surfaces which face each other in the assembled arrangement, so that they extend around the edge surfaces of a relatively smaller discrete passive component 104. In the embodiment of Fig. 5 B the first and second metal clips 150, 152 have linear inner edge sides which face each other in the mounted arrangement so that they accommodate a larger discrete passive component 104.

[0056] Referring to Fig. Figure 6 shows a clip frame 200, which can be used to provide the metal clips that are related to the Fig. 4 and Fig. 5 are described. The clip frame 200 has pairs of the first and second metal clips 150, 152, which are attached to a peripheral structure 202. These pairs are arranged in an opposite configuration so that the clip frame 200 can be positioned over the semiconductor package 102, and the first and second metal clips 150, 152 of each pair are appropriately positioned. Furthermore, the pairs of metal clips can be arranged in groups to provide a multi-package assembly, as shown, for example, in Fig. Figure 3 shows that the Clip Frame 200 can be made of a conductive material, for example, copper (Cu), aluminum (Al), nickel (Ni), nickel phosphorus (NiP), silver (Ag), palladium (Pd), gold (Au), etc., alloys, or combinations thereof. The Clip Frame 200 can be manufactured using standard conductor frame processing techniques. According to one technique, the Clip Frame 200 is provided from a single layer of metal, e.g., a layer of substantially uniform thickness made of any of the metals listed above, or a combination of them. The various features of the Clip Frame 200 are formed by techniques such as embossing, stamping, etching, bending, etc.

[0057] Referring to Fig. Figure 7 shows a method for assembling a semiconductor device according to one embodiment. This method can be used to produce the semiconductor assembly 100 according to any of the embodiments, which are related to the Fig. 2-4 are described.

[0058] Referring to Fig. A circuit carrier 140 is provided in 7A, which has an electrically insulating substrate. The carrier 140 can be a PCB or a power electronics substrate (e.g., DBC, AMB, IMS, etc.), according to any of the configurations described above. A plurality of semiconductor packages 102 are arranged on the circuit carrier 140. A solder material can be provided between the bond pads, which are applied to the lower surface of the semiconductor package 102, and the circuit carrier 140. A solder reflow process can be performed at this time to form soldered connections, or these soldered connections can be formed later during a standard reflow step.

[0059] Referring to Fig. 7B are areas of solder material 154 provided on the first and second bond pads 128, 130 of each of the semiconductor packages 102. These areas of solder material 154 can be a soft solder material, e.g., a tin-based solder paste.

[0060] Referring to Fig. In 7C, the first and second metal clips 150, 152 are arranged on each side of the semiconductor packages 102 to contact the areas of solder material. The first and second metal clips 150, 152 can also contact a solder material on the carrier 140 (not shown) to form electrical connections with bond pads on the carrier 140. The first and second metal clips 150, 152 can be connected by arranging a clip frame 200, such as with reference to Fig. As described in section 6, the first and second metal clips 150, 152 are provided above each of the semiconductor packages 102, and subsequently separated from the peripheral structure 202, e.g. by mechanical cutting or other separation techniques. This separation can take place before or after the solder material reflow step, which is described in more detail below.

[0061] Referring to Fig. In step 7D, the discrete passive device 104 is positioned on the areas of the solder material 154 such that the terminals of the discrete passive device contact the areas of the solder material 154. After positioning the discrete passive device 104 on the areas of the solder material 154, a solder reflow step can be performed to form the soldered connections. As a result, the first and second metal clips 150, 152, the semiconductor package 102, and the discrete passive device 104 are electrically connected and securely attached to the appropriate terminals.

[0062] Instead of using the first and second metal clips 150, 152, as in Fig. As shown in Figure 7, a similar technique can be used to form an assembly, wherein the first and second metal connection structures 146, 148 are configured as elongated metal webs, as shown, for example, with reference to the Fig. 2 and Fig. 3 is described. Instead of the clip frame 200, a similar structure having a first and a second elongated metal rib can be provided and arranged over the groups of semiconductor packages 102, and similar steps as described above can be carried out.

[0063] Referring to Fig. Figure 8 shows a semiconductor assembly 100 according to another embodiment. The semiconductor assembly 100 of Fig. 8 can be identical to the one which refers to Fig. as described in Figure 4, except that the discrete passive element is mounted on top of the first and second metal clips 150, 152. This arrangement may be preferred to reduce the footprint required for each of the semiconductor packages 102. While the concept is generally applicable to each of the embodiments of semiconductor packages 102 described herein, the illustrated packages correspond to the package described in Figure 4. Fig. 4B is shown, with the first and second through contacts 134, 138 omitted, resulting in further space efficiency.

[0064] Referring to Fig. Figure 9 shows a technique for forming the semiconductor assembly 100, which is described with reference to Fig. 8 is described, according to one embodiment. As in the Fig. 9A and Fig. As shown in Figure 9B, the circuit carrier 140 is provided, and the semiconductor packages 102 are mounted on the circuit carrier 140 in a similar manner to that described above. As shown in Fig. As shown in Figure 9C, the first and second metal clips 150, 152 are arranged on each side of the semiconductor packages 102 such that the first and second metal clips 150, 152 contact the areas of the solder material 154. The geometry of the first and second metal clips 150, 152 may differ from that of the preceding embodiments in that the overlapping section of the metal clips may be larger, since there is no need to accommodate the discrete passive element 104 between the clips. Subsequently, for each of the assemblies, further areas of the solder material 154 are provided on top of the first and second metal clips 150, 152. As shown in Fig. As shown in Figure 9D, the discrete passive element 104 is then placed on the further areas of the solder material 154. A solder material reflow process can be performed to form the soldered connections. According to one technique, the solder material reflow is performed after the step which is shown in Fig. 9C is shown, and a second solder material reflow step is performed after the step which is shown in Fig. 9D is shown. In this way, two different types of solder material can be used. Alternatively, after the step which is shown in Fig. Figure 8D shows that a single solder material reflow step is performed to form all soldered connections simultaneously.

[0065] The term "electrical connection," as used herein, describes a conduction path between two elements that has low electrical resistance and is non-rectifying. An "electrical connection" can consist of several different electrically conductive structures, for example, bond pads, solder, and conductive vias.

[0066] Spatially relative terms, such as "under," "below," "lower," "above," "upper," and similar terms, are used to facilitate description and explain the positioning of one element relative to another. These terms are intended to encompass various orientations of the device in addition to those depicted in the figures. Furthermore, terms such as "first," "second," and similar terms are also used to describe different elements, areas, sections, etc., and are likewise not intended to be restrictive. Throughout the description, the same terms refer to the same elements.

[0067] As used herein, the terms "have," "comprise," "contain," "exhibit," and similar open-ended terms indicate the presence of the elements or features mentioned, but do not exclude any additional elements or features. The articles "a," "an," and "the" are intended to include both the singular and the plural unless the context clearly indicates otherwise.

Claims

[1] A semiconductor assembly (100) comprising: a semiconductor package (102) comprising a first and a second transistor chip (118, 120) embedded in a package body, wherein the first and the second transistor chip (118, 120) are arranged laterally next to one another in the package body such that a first load terminal (122) of the first transistor chip (118) faces an upper surface of the package body, and such that a second load terminal (124) of the second transistor chip (120) faces the upper surface of the package body, and a discrete capacitor (104) mounted on the semiconductor package (102) such that a first terminal of the discrete capacitor (104) is directly above and electrically connected to the first load terminal (122) of the first semiconductor chip (118), and such that a second terminal of the discrete capacitor (104) is directly above and electrically connected to the second load terminal (124) of the second semiconductor chip (120); wherein the first and second transistor chips (118, 120) are each vertical devices, and wherein a vertical orientation of the first transistor chip (118) is opposite to the second transistor chip (120). [2] The semiconductor assembly (100) of claim 1, wherein the semiconductor package (102) further comprises a first patterned metallization layer deposited on the upper surface of the package body, the first patterned metallization layer comprising a first bond pad (128) directly over and electrically connected to the first load terminal (122) of the first semiconductor chip (118) and a second bond pad (130) directly over and electrically connected to the second load terminal (124) of the second semiconductor chip (120). [3] The semiconductor device (100) of claim 2, wherein the first terminal of the discrete capacitor (104) is adhesively conductively connected to the first bond pad (128), and wherein the second terminal of the discrete capacitor (104) is adhesively conductively connected to the second bond pad (130). [4] The semiconductor assembly (100) according to claim 2 or 3, wherein the semiconductor package (102) further comprises a second patterned metallization layer applied to a lower surface of the package body opposite the upper surface of the package body, the second patterned metallization layer comprising: a third bonding pad (132) which is electrically connected to the first bonding pad (128) by means of a first via (134); and a fourth bonding pad (136) which is electrically connected to the second bonding pad (130) by means of a second via (138), and wherein both of the first and second transistor chips (118, 120) are laterally between the first and second vias (138). [5] The semiconductor device (100) according to any one of claims 1 to 4, further comprising: a carrier (140) having an electrically insulating substrate; and a plurality of semiconductor packages (102) mounted on the carrier (140), wherein the first bond pads (128) of each of the semiconductor packages (102) of the plurality are electrically connected to one another by means of a first metal interconnect structure (146), and wherein the second bond pads (130) of each of the semiconductor packages (102) of the plurality are electrically connected to one another by means of a second metal interconnect structure (148). [6] The semiconductor assembly (100) of claim 5, wherein one or both of the first and second metal interconnect structures (146, 148) are metal lands completely deposited over the plurality of semiconductor packages (102). [7] The semiconductor assembly (100) of claim 5, wherein one or both of the first and second metal interconnect structures (146, 148) are metal clips (150, 152) connected between the semiconductor packages (102) and the carrier (140). [8] A semiconductor assembly (100) comprising: a semiconductor package (102) comprising a power converter circuit monolithically integrated in a package body, the power converter circuit comprising a first load terminal (122) and a second load terminal (124), the first and second load terminals (122, 124) both facing a top surface of the package body; and a discrete capacitor (104) mounted on the semiconductor package (102) such that a first terminal of the discrete capacitor (104) is directly above and electrically connected to the first load terminal (122), and such that a second terminal of the discrete capacitor (104) is directly above and electrically connected to the second load terminal (124); wherein the power converter circuit comprises first and second transistor chips (118, 120) embedded in the package body; wherein the first and second transistor chips (118, 120) are each vertical devices, and wherein a vertical orientation of the first transistor chip (118) is opposite to the second transistor chip (120). [9] The semiconductor device (100) according to claim 8, wherein the first and second transistor chips (118, 120) are each configured as a discrete power MOSFET, wherein the first load terminal (122) corresponds to a drain terminal of the first transistor chip (118), and wherein the second load terminal (124) corresponds to a source terminal of the second transistor chip (120). [10] The semiconductor device (100) according to claim 9, wherein the power converter circuit is configured as a half-bridge circuit, wherein the first transistor chip (118) is a high-side switch of the half-bridge circuit, and wherein the second transistor chip (120) is a low-side switch of the half-bridge circuit. [11] The semiconductor package (100) of any one of claims 8 to 10, wherein the first terminal of the discrete capacitor (104) is a metal contact or a conductor adhesively conductively attached to the first load terminal (122), and wherein the second terminal of the discrete capacitor (104) is a metal contact or a conductor adhesively conductively attached to the second load terminal (124). [12] A method of assembling a semiconductor device, the method comprising: Providing a semiconductor package (102) comprising a first and a second transistor chip (118, 120) embedded in a package body, wherein the first and the second transistor chip (118, 120) are arranged laterally next to one another in the package body such that a first load terminal (122) of the first transistor chip (118) faces an upper surface of the package body, and such that a second load terminal (124) of the second transistor chip (120) faces the upper surface of the package body; and Mounting a discrete capacitor (104) on the semiconductor package (102) such that a first terminal of the discrete capacitor (104) is directly above and electrically connected to the first load terminal (122) of the first semiconductor chip (118), and such that a second terminal of the discrete capacitor (104) is directly above and electrically connected to the second load terminal (124) of the second semiconductor chip (120); wherein the first and second transistor chips (118, 120) are each vertical devices, and wherein a vertical orientation of the first transistor chip (118) is opposite to the second transistor chip (120). [13] The method of claim 12, wherein the semiconductor package (102) comprises first and second bond pads (130) disposed on a top surface of the semiconductor package (102), the first bond pad (128) being directly above and electrically connected to the first load terminal (122) of the first semiconductor chip (118), the second bond pad (130) being directly above and electrically connected to the second load terminal (124) of the second semiconductor chip (120), wherein mounting the discrete capacitor (104) comprises directly attaching the first terminal of the discrete capacitor (104) to the first bond pad (128) and directly attaching the second terminal of the discrete capacitor (104) to the second bond pad (130). [14] The method of claim 13, wherein directly attaching the first terminal of the discrete capacitor (104) to the first bond pad (128) comprises soldering the first terminal of the discrete capacitor (104) to the first bond pad (128), and wherein directly attaching the second terminal of the discrete capacitor (104) to the second bond pad (130) comprises soldering the second terminal of the discrete capacitor (104) to the second bond pad (130). [15] The method according to claim 13 or 14, further comprising: Providing a circuit carrier (140) having an electrically insulating substrate; Mounting a plurality of the semiconductor packages (102) on the circuit carrier (140); Providing first and second metal interconnect structures (146, 148); electrically connecting the first bond pads (128) of the semiconductor packages (102) to one another using the first metal interconnect structure (146); electrically connecting the second bond pads (130) of the semiconductor packages (102) to one another using the second metal interconnect structure (148); and Mounting one of the discrete capacitors (104) on each of the semiconductor packages (102) of the plurality. [16] The method of claim 15, wherein providing the first and second metal interconnect structures (148) comprises providing first and second elongated metal fins, wherein electrically connecting the first bond pads (128) of the semiconductor packages (102) comprises disposing the first metal fin over the first bond pad (128) of each semiconductor package (102) of the plurality, and wherein electrically connecting the second bond pads (130) of the semiconductor packages (102) comprises disposing the second metal fin over the second bond pad (130) of each semiconductor package (102) of the plurality. [17] The method of claim 15, wherein providing the first and second metal interconnect structures (146, 148) comprises providing first and second metal clips (150, 152), wherein electrically connecting the first bond pads (128) of the semiconductor packages (102) comprises electrically connecting the first bond pad (128) of each semiconductor package (102) of the plurality to the carrier (140) using one of the first metal clips (150), and wherein electrically connecting the second bond pads (130) of the semiconductor packages (102) comprises electrically connecting the second bond pad (130) of each semiconductor package (102) of the plurality to the carrier (140) using one of the second metal clips (152). [18] The method of claim 17, wherein for each of the plurality of semiconductor packages (102), the discrete capacitor (104) is mounted on top of the first and second metal clips (150, 152). [19] The method of claim 17 or 18, wherein providing the first and second elongated metal clips (150, 152) comprises providing a clip frame (200) having groups of the first and second metal clips (150, 152) each attached to a peripheral structure, wherein electrically connecting the first bond pads (128) of the semiconductor packages (102) and electrically connecting the second bond pads (130) of the semiconductor packages (102) comprises disposing the clip frame (200) over the plurality of semiconductor packages (102), and wherein the method further comprises separating the first and second metal clips (150, 152) from the peripheral structure.

Images