TIMER CIRCUIT, OSCILLATOR CIRCUIT AND SEMICONDUCTOR DEVICE

Abstract

a timer circuit (100) comprising: a capacitor (C1); a first current source (CS1) configured to charge the capacitor (C1); an inverter (120); a second current source (CS2) configured to supply a current to an input node (122) of the inverter (120); a current mirror circuit (110) with an output node (114) connected to the input node (122) of the inverter (120); and a resistor (R1) connected between an input node (112) of the current mirror circuit (110) and the capacitor (C1).

Description

BACKGROUNDTechnical FieldThe present disclosure relates to a timer circuit.Description of the Prior ArtIn a semiconductor integrated circuit, a timer circuit is used for time measurement. The timer circuit includes a capacitor, a current source that charges the capacitor, and a voltage comparator that compares the voltage across the capacitor to a predetermined threshold voltage.If an operational amplifier including a differential amplifier is used as a voltage comparator, this leads to a greater circuit scale and a higher power consumption. In applications requiring small area and low power consumption, an inverter is employed as such a voltage comparator. US 2008 / 0 290 955 A1 discloses an oscillator circuit for use in integrated circuits. The oscillator circuit includes a delay generation circuit having a current mirror with at least a first current mirror branch and a second current mirror branch, a current source coupled to the first current mirror branch, a capacitive element coupled to the first current mirror branch, and a resistive element coupled to the second current mirror branch. The oscillator circuit further includes a plurality of inverting elements connected in series and a transconducing element connected to an output of the plurality of inverting elements. The transconducing element is configured to discharge the capacitive element. A latch element is coupled to latch an output signal of the plurality of inverting elements.US 2010 / 0 201 454 A1 discloses an oscillator comprising a positive power supply node for providing a positive power supply voltage, a capacitor, and a constant current source that supplies a first constant current and is connected to the positive power supply node. The oscillator also includes a charging current source configured to provide a second constant current for charging the capacitor, the second constant current mirroring the first constant current. The oscillator further includes a constant current source inverter having a third constant current which mirrors the first constant current. The constant current source inverter is configured to control the oscillator to transition to the transition state at a constant state transition voltage.EP 1 693 960 A1 describes an electrical circuit having a circuit path from a first reference voltage to a second reference voltage which is lower than the first reference voltage. The path comprises power supply means, at least one capacitor and first switching means suitable for connecting or disconnecting the capacitor to and from the power supply means. The first switching means have a certain trigger value, and the electrical circuit comprises second switching means arranged in parallel with the at least one capacitor and control means adapted to act on the first and second switching means to control the charging and discharging of the at least one capacitor. The control means comprise further means operable during charging of the capacitor and adapted to act on the first switching means to block charging of the capacitor when the voltage value at its terminals reaches a predefined voltage value. The predefined voltage value is lower than the trigger voltage of the first switching means and higher than the second reference voltage.In addition, JP 2003-85 972 A is also known. In a case in which an inverter is used as a voltage comparator, its threshold voltage is the mean voltage of the supply voltage of the inverter. Accordingly, a change in the supply voltage results in a change in the threshold voltage. When such a voltage comparator is used as an oscillator, there is a problem that the oscillation frequency increases as the supply voltage decreases.OVERVIEWThe present disclosure has been made to solve such a problem.An embodiment of the present disclosure relates to a timer circuit. The timing circuit includes: a capacitor; a first current source structured to charge the capacitor; an inverter; a second current source structured to provide a current to an input node of the inverter; a current mirror circuit having an output node connected to the input node of the inverter; and a resistor connected between an input node of the current mirror circuit and the capacitor.With the voltage across the capacitor as V C1, the threshold voltage of the input-side transistor of the current mirror circuit as V TH and the resistance value of the resistor as R1, the current I 3, which flows through the resistor and the input node of the current mirror circuit, is represented by I 3= ( V C1- V TH) / R1. When the mirror ratio of the current mirror circuit is K, the output current I 4 of the current mirror circuit is represented by I 4= K×I 3= K×(V C1- V TH) / R1. When the current I 2 generated by the second current source becomes equal to the output current I 4 of the current mirror circuit, the output of the inverter changes. Accordingly, the capacitor voltage V C1(TH) at the point where the output of the inverter changes is represented by V C1(TH)= I 2 × R1 / K + V TH. The voltage V C1(TH) is a constant value which does not depend on the supply voltage of the inverter. Accordingly, such a timer circuit is capable of performing time measurement without depending on the power supply voltage.In an embodiment, the current mirror circuit may be configured using a field effect transistor (FET).In one embodiment, the relationship between the channel width W and the channel length L, i.e., W / L, is determined so that, when the output of the inverter changes, a variation in the gate-source voltage of an input-side transistor of the current mirror circuit is maintained in a range of 0.1 V or less or, more preferably, 0.05 or less in a case where a variation in temperature occurs within a guaranteed operating temperature range. As a result, the temperature dependence of the measurement time can be reduced.In an embodiment, the current mirror circuit may be configured using a bipolar transistor.In an embodiment, the timing circuit may be monolithically integrated on a single semiconductor substrate. Examples of such an "integrated" arrangement are:an arrangement in which all circuit components are formed on a semiconductor substrate; and an arrangement in which the most important circuit components are monolithically integrated. A part of the circuit components such as resistors or capacitors can also be arranged in the form of components outside such a semiconductor substrate,to adjust the circuit constants. By integrating the circuit on a single chip, such an arrangement enables a reduction in circuit area and uniform characteristics of the circuit elements.An oscillator according to an embodiment may include: one of the above-described timer circuits; and a reset circuit configured to discharge the capacitor in response to the output of the inverter of the timer circuit.An oscillator according to an embodiment may include two timing circuits. Each of the two timer circuits may be reset by an output of the other timer circuit.A semiconductor device according to an embodiment may include any one of the above-described oscillator circuits, a charge pump circuit driven by an output signal of the oscillator circuit, and an N-type transistor arranged such that the output voltage of the charge pump circuit is received via its control electrode.BRIEF DESCRIPTION OF THE DRAWING FIGURESThe embodiments are described herein by way of example only with reference to the accompanying drawing figures, which are intended to be exemplary and not limiting, and in which like elements are numbered the same in multiple figures: FIG. 1 is a circuit diagram of a timer circuit according to an embodiment; FIG. 2 is an operation waveform diagram of the timer circuit shown in FIG. 1; FIG. 3 is a circuit diagram of a timer circuit according to a comparison technique; FIG. 4 is a circuit diagram of an oscillator according to an embodiment; FIG. 5 is an operation waveform diagram of the oscillator shown in FIG. 4; FIG. 6 is a schematic view for explaining temperature characteristics of a MOSFET; FIG. 7 is a view showing the voltage-current characteristics of an input-side transistor in a case where the input-side transistor has an improper size; FIG. 8 is a view showing the voltage-current characteristics of the input-side transistor with optimized size; FIG. 9 is a circuit diagram of an oscillator according to a modification; FIG. 10 is an operation waveform diagram of the oscillator shown in FIG. 9; and FIG. 11 is a circuit diagram of a semiconductor device including an oscillator.DETAILED DESCRIPTIONThe following is an overview of several exemplary embodiments of the disclosure. This summary is provided to provide the reader with a basic understanding of such embodiments and does not fully define the scope of the disclosure. This summary is not a comprehensive overview of all contemplated embodiments, and is not intended to identify key or critical elements of all embodiments, nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more embodiments in simplified form as a prelude to the more detailed description that follows. For convenience, the term "an embodiment" may be used herein to refer to a single embodiment or multiple embodiments of the disclosure.EMBODIMENTSPreferred embodiments will be described below with reference to the drawing figures. The same or similar components, elements and methods are denoted by the same reference numerals, and redundant description is omitted as appropriate. The embodiments have been described for exemplary purposes only and are not intended to limit the present disclosure and the present invention in any way. Also, it is not necessarily required for the present disclosure and the present invention that all features or a combination thereof are provided as described in the embodiments.In some cases, the sizes (thickness, length, width, etc.) of the individual components illustrated in the drawing figures are expanded (enlarged) or reduced for ease of understanding. The proportion between a plurality of components in the drawing figures does not necessarily correspond to the actual proportion between them. That is, even in a case where a certain component A has a thickness larger than that of another component B in the drawing figures, in some cases, the component A actually has a thickness smaller than that of the component B.In the present specification, a state represented by the phrase "the element A is coupled to the element B" includes a state in which the element A is indirectly coupled to the element B via another element that does not substantially impair the electrical connection therebetween or that does not damage the functions or effects of the connection therebetween, in addition to a state in which they are physically and directly coupled.Similarly, a state represented by the phrase "the element C is provided between the element A and the element B" includes a state in which the element A is indirectly coupled to the element C or the element B is indirectly coupled to the element C via another element that does not substantially impair the electrical connection therebetween or does not impair the functions or effects of the connection therebetween, in addition to a state in which they are directly coupled. In the present specification, those reference symbols indicating electrical signals such as a voltage signal, a current signal, or the like and the reference symbols indicating circuit elements such as a resistor, a capacitor, an inductor, or the like also represent the corresponding voltage value, current value, or circuit constants (resistance value, capacitance value, inductance) as needed.FIG. 1 is a circuit diagram of a timer circuit 100 according to an embodiment. After a predetermined time (measurement time) τ MEAS has elapsed after a start signal / START (" / " means logic inversion) is activated (e.g., set low), the timer circuit 100 activates (e.g., sets high) a signal OUT output from an output terminal (output line) 104.The timer circuit 100 includes a capacitor C 1, a first current source CS 1, a second current source CS 2, a current mirror circuit 110, a resistor R 1, an inverter 120, and a reset transistor M 3. A power supply voltage V DD is applied to a power supply line 102 of the timer circuit 100.The capacitor C 1 is disposed such that one end is grounded. The first current source CS 1 is connected to the other end of the capacitor C 1. The first current source CS1 serves as a constant current source I 1 to the capacitor C1 to charge the capacitor C1.The inverter 120 includes a high-side transistor M 21 and a low-side transistor M 22 connected between the power supply line 102 and the ground. Specifically, the high-side transistor M 21 is connected between the power supply line 102 and the output line 104. The low-side transistor M 22 is connected between the output line 104 and the ground.The second current source CS 2 is connected to an input node 122 of the inverter 120. The second current source CS 2 functions as a source of a current I 2 to the input node of the inverter 120.The current mirror circuit 110 mirrors the current flowing through the input node 112 in a manner that it is multiplied by K ("K" is referred to as mirror ratio) and that the mirrored current is folded back and dropped from an output node 114. The current mirror circuit 110 includes an input-side transistor M 11 and an output-side transistor M 12. Output node 114 of current mirror circuit 110 is connected to input node 122 of inverter 120.The resistor R 1 is connected between the input node 112 of the current mirror circuit 110 and the capacitor C 1.The reset transistor M 3 (also: reset transistor M 3) is connected in parallel with the capacitor C 1. During a period in which the start signal / START is negated (high), the reset transistor M3 is turned on to discharge the capacitor C1. During a period in which the start signal / START is activated (low), the reset transistor M 3 is switched off in such a way that the capacitor C 1 can be charged with the aid of the first current source CS 1.The above is a diagram showing the structure of the timer circuit 100. Their operation will be described below.FIG. 2 is an operation waveform diagram of the timer circuit 100 shown in FIG. 1. FIG. 2 shows the start signal / START, the voltage V C1 across the capacitor C1, the current I 3, which flows through the resistor R1, the output current I 4 of the current mirror circuit 110 and the output signal OUT.Before time t 0 the start signal / START is negated and the reset transistor M3 is turned on. In this state, the capacitor voltage V C1 is set to 0 V.When the start signal / START is 0 at time t, the capacitor C1 is charged by the current I 1 generated from the first current source CS1. Thus, the capacitor voltage V C1 increases with time.When the capacitor voltage V C1 exceeds a gate-source threshold voltage V GS(th) of the input-side transistor M11 of the current mirror circuit 110, the current I 3 starts to flow through the resistor R1 and the input side of the current mirror circuit 110. The current I 3 is represented by the following equation.For convenience of description, FIG. 2 shows an example in which the current I 3 is zero during a period from t 0 to t 1 but an arrangement in which a current I 3 actually flows may be adopted. Current I 4, which results from multiplying input current I 3 by K, flows through output node 114 of current mirror circuit 110. For the convenience of description, an example is shown in FIG. 2 in which the capacitor voltage V C1 and the current I 3 each increase with a constant slope. In reality, however, the capacitor voltage V C1 is charged by the difference of the currents I 1 and I 3. Accordingly, the slope of the capacitor voltage V C1 is non-linear.Before time t 2 the relationship I 4< I 2. holds. Accordingly, the voltage V INV of the input node 122 of the inverter 120 is high (V DD). Accordingly, the output of inverter 120, i.e., the output OUT of timer circuit 100, is low.If the current I 4 exceeds the current I 2( I 1 > I 2) at time t 3, the voltage V INV of the input node 122 of the inverter 120 is set to low (0 V). In this state, the output of the inverter 120, i.e., the output OUT of the timer circuit 100, goes high.The time between the timings t 0 and t 2 is used by the timer circuit 100 as the measurement time τ MEAS. The capacitor voltage V C1(TH) at the time t 2 is represented by V C1(TH)= I 2 × R 1 / K + V C1(TH).With respect to the capacitor C1, the capacitor voltage V C1 is generated by charging the capacitor C1 with a charging current I CHG= I 1- I 3. Accordingly, the integration time τ is represented by C1×(I 2×R1 / K+V C1(TH)) = ophthalmological τI CHG( t) dt, and the measurement time τ is MEAS.The above describes the operation of the timing circuit 100. The advantages of the timer circuit 100 can be clearly understood compared to conventional techniques.FIG. 3 is a circuit diagram of a timer circuit 100R according to a comparison technique. The timer circuit 100R includes a capacitor C 1, a first current source CS 1, a reset transistor M 3, and an inverter 120.The capacitor C1 is charged in 1 by the current I generated by the current source CS1. The capacitor voltage V C1 increases with a constant slope with time. When the capacitor voltage V C1 reaches the threshold voltage of the inverter 120, the output OUT changes from high to low.Here, the threshold voltage of the inverter 120 is half of the supply voltage V DD. Accordingly, in the timing circuit 100R shown in FIG. 3, a change in the supply voltage V DD results in a change in the measurement time τ MEAS. The timer circuit 100 shown in FIG. 1, on the other hand, has the advantage that the measurement time τ MEAS does not depend on the supply voltage V DD.Next, the use of the timer circuit 100 will be described. The timer circuit 100 may be used in an oscillator circuit.FIG. 4 is a circuit diagram of an oscillator 200A according to an embodiment. The oscillator 200A includes a first timer circuit 100_ 1, a second timer circuit 100_ 2, and a control circuit 210.The first timer circuit 100_ 1 and the second timer circuit 100_ 2 each have the same configuration as the above-described timer circuit 100. The respective measurement times τ MEAS1 and τ MEAS2 of the first timer circuit 100_ 1 and the second timer circuit 100_ 2 may be the same or different.The control circuit 210 sets a second start signal / START2 to the second timer circuit 100_2 in response to activation of an output OUT1 of the first timer circuit 100_1. In addition, the control circuit 210 sets a first start signal / START1 for the first timer circuit 100_1 in response to activation of an output OUT2 of the second timer circuit 100_2. During a period in which either the first start signal / START1 or the second start signal / START2 is activated, an output CLK of the controller 210 is set to a first level (e.g., high). During a period when the other signal is asserted, the output CLK of the controller 210 is set to a second level (e.g., low).FIG. 5 is an operation waveform diagram of the oscillator 200A shown in FIG. 4. In the oscillator 200A, the first timer circuit 100_ 1 and the second timer circuit 100_ 2 are activated alternately. The oscillator 200A generates the clock signal CLK having a period represented by the sum of the two measurement times (τ MEAS1+ τ MEAS2).Next, the temperature characteristics of the timer circuit 100 will be described. The measurement time τ MEAS of the timer circuit 100 is affected by the temperature characteristics of the current mirror circuit 110.FIG. 6 is a schematic view for explaining temperature characteristics of a MOSFET. FIG. 6 shows the voltage-current characteristics at two temperatures, i.e., high and low temperatures. In the description, it is assumed that the gate and drain of the MOSFET are connected and the gate-source voltage Vgs is equal to the gate-drain voltage Vds. The horizontal axis represents the gate-source voltage Vgs, and the vertical axis represents the drain current Id.A MOSFET has the following characteristics. (i) As the temperature increases, the gate-source threshold voltage V GS(th) of the MOSFET becomes lower, resulting in that the drain current easily flows. In FIG. 6, V GS(th) is represented as a voltage determined using the Gmmax method. (ii) As the temperature rises, the conductance Gm of the MOSFET, i.e. the slope of the drain current Id in relation to the gate voltage Vgs (dId / dVgs), becomes smaller.Accordingly, the operating point of the input-side transistor M 11 of the current mirror circuit 110 (gate-source voltage, i.e. the gate-drain voltage, i.e. the voltage at the input node 112 of the current mirror circuit 110) can preferably be determined. Further, the relationship between the channel width W and the channel length L of the input-side transistor M 11, i.e., W / L, may be preferably determined such that the temperature characteristics described in (i) and the temperature characteristics described in (ii) cancel each other out.For example, the gate-source voltage Vgs of the input-side transistor at a time when the output of the inverter 120 changes may be controlled within a variation of 0.1 V or less, preferably 0.05 V or less, when the temperature changes within the guaranteed operating temperature range.FIG. 7 is a view showing the voltage-current characteristic of the input-side transistor M 11 in a case where the input-side transistor M 11 has an improper size. The operating point (i.e., the point at which the output of the inverter 120 changes) is I 3= 5 μ A. The input-side transistor M 11 has a magnitude of W / L=10 μm / 1 μm. In a case where the input-side transistor M 11 has an unsuitable magnitude as described above, the gate-source voltage Vgs at the operating point fluctuates in a range on the order of 0.4 V that is larger than 0.1 V when the temperature changes on the order of -50° C., 25° C., and 150° C.FIG. 8 is a view showing the voltage-current characteristic of the input-side optimized-magnitude transistor M 11. The operating point is I 3= 5 μ A. The input-side transistor M 11 has a magnitude of W / L=10 μm / 10 μm. In a case where the input-side transistor M 11 has such an optimized magnitude as described above, when the temperature changes in the order of -50° C., 25° C., and 150° C., such an arrangement is capable of controlling the variation of the gate-source voltage Vgs at the operating point in a range of 0.1 V in a range narrower than 0.05 V. FIG. 9 is a circuit diagram of an oscillator 200B according to a modification. The oscillator 200B includes the above-described timer circuit 100 and a reset circuit (reset circuit) 210B. The reset circuit 210B is embodied as a one-shot circuit, for example. The reset circuit 210B generates a reset pulse RST having a predetermined pulse width T ON with the activation (e.g., high level) of the output OUT of the timer circuit 100 as a trigger. The reset pulse RST is input to the timer circuit 100 as a start signal / START.FIG. 10 is an operation waveform diagram of the oscillator 200B shown in FIG. 9. The reset pulse RST has a period Tp that is the sum of the measurement time τ MEAS of the timer circuit 100 and the pulse width T ON of the reset pulse RST.Note that the configuration of the oscillator 200 including the timing circuit 100 is not limited to the configuration shown in FIG. 4 or FIG. 9. The use of the oscillator 200 using the timing circuit 100 will be described below.FIG. 11 is a circuit diagram of a semiconductor device 300 including the oscillator 200. The semiconductor device 300 includes an under voltage protection (UVP) circuit 310, a charge pump circuit 320, a regulator circuit 330, a start bias circuit 340, a reference current source 350, a band gap reference circuit 352, and so forth.An external power supply voltage V CC is supplied from an external power supply circuit to a power supply terminal VCC of the semiconductor device 300. The regulator circuit 330 receives the external supply voltage V CC as an input voltage and generates an internal supply voltage V REG5, which is stabilized at a predetermined target level (e.g., 5 V). The internal supply voltage V REG5 is supplied to load circuits such as the reference current source 350, the band gap reference circuit 352, and so forth.The regulator circuit 330 is configured as a source follower circuit including an NMOS transistor 332 and a bias circuit 334. The bias circuit 334 includes a zener diode DLZ and a resistor R 11. The bias circuit 334 generates a Zener voltage Vz of the Zener diode DLZ at the gate of the NMOS transistor 332. The internal supply voltage V REG5 is stabilized to a target value represented by VREF (REF)= V Z- V GS. Here, V GS represents the gate-source voltage of the NMOS transistor 332. The Zener voltage Vz is set, for example, such that VREF (REF)= 5 V applies.When the external supply voltage V CC is lower than the target value (5 V) of the internal supply voltage V REG5, i.e., the zener voltage Vz of the zener diode DLZ, the bias circuit 334 cannot operate. In order to appropriately bias the NMOS transistor 332 in this state, the UVP circuit 310, the oscillator 200, and the charge pump circuit 320 are provided.The UVP circuit 310 compares the external supply voltage V CC with an under voltage threshold V UVP. When V CC > V UVP the UVP circuit 310 asserts the UVP signal (e.g., high).If the UVP signal is activated, the oscillator 200 enters the operating state. In this state, the oscillator 200 generates a clock signal CLK. In addition, the UVP signal is supplied to an enable terminal of the charge pump circuit 320. When the UVP signal is activated, the charge pump circuit 320 enters the enable state. In this state, the charge pump circuit 320 increases the internal power supply voltage V REG5 in synchronization with the clock signal CLK to generate the charge pump voltage V CP. The charge pump voltage V CP is higher than the target level of the internal power supply voltage V REG5.The turn-on bias circuit 340 operates with the charge pump voltage V CP as a power supply. The turn-on bias circuit 340 functions as a source of the turn-on current I in START with the gate of the NMOS transistor 332. With such an arrangement, in which the starting current I START flows through the zener diode DLZ, it is capable of generating the zener voltage Vz at the gate of the NMOS transistor 332 even in a state where the external supply voltage V CC is low.In such an arrangement that the oscillator 200 is configured to supply the clock signal CLK to the charge pump circuit 320 using the timer circuit 100 according to the present embodiment, it is capable of generating the clock signal CLK at a stable frequency.MODIFICATIONSIn the embodiment, an arrangement in which the current mirror circuit 110 is configured with MOSFETs has been described. However, the current mirror circuit 110 may be configured with bipolar transistors. The circuit blocks other than the current mirror circuit 110, for example, the inverter 120, the reset transistor M 3, the first current source CS 1, the second current source CS 2, or the like, may be configured with bipolar transistors.The present invention has been described with reference to the specific term embodiments. However, the above-described embodiments only show one aspect of the mechanisms and applications of the present invention. Rather, various modifications and various changes in arrangement may be made without departing from the spirit or scope of the present invention as defined in the appended claims.

Claims

A timing circuit (100) comprising: a capacitor (C1); a first current source (CS1) structured to charge the capacitor (C1); an inverter (120); a second current source (CS2) structured to provide a current to an input node (122) of the inverter (120); a current mirror circuit (110) having an output node (114) connected to the input node (122) of the inverter (120); and a resistor (R1) connected between an input node (112) of the current mirror circuit (110) and the capacitor (C1).The timing circuit of claim 1, wherein the current mirror circuit (110) is configured with a field effect transistor.The timer circuit according to claim 2, wherein a ratio between a channel width W and a channel length L, i.e., W / L, is determined such that when an output of the inverter (120) changes, a variation of a gate-source voltage of an input-side transistor of the current mirror circuit (110) in a case where a variation occurs at a temperature within a guaranteed operating temperature range is kept within a range of 0.05 V or less.The timing circuit according to claim 1, wherein the current mirror circuit (110) is configured using a bipolar transistor.The timing circuit according to any one of claims 1 to 4, monolithically integrated on a single semiconductor substrate.The oscillator circuit (200A) comprising two timer circuits (100_1, 100_2) according to any one of claims 1 to 4, wherein each of the two timer circuits (100_1, 100_2) is reset by an output of the other timer circuit (100_2, 100_1).An oscillator circuit (200B) comprising: the timer circuit (100) according to any one of claims 1 to 4; and a reset circuit (210B) configured to discharge the capacitor (C1) in response to an output signal of the inverter (120) of the timer circuit (100).A semiconductor device (300) comprising: the oscillator circuit (200A) according to claim 6; a charge pump circuit (320) configured to be driven according to an output signal of the oscillator circuit (200A); a linear regulator (330) including an NMOS transistor; and a turn-on bias circuit (340) configured to receive an output voltage of the charge pump circuit (320) and generate a bias voltage at a gate of the NMOS transistor.A semiconductor device (300) comprising: the oscillator circuit (200B) according to claim 7; a charge pump circuit (320) configured to be driven according to an output signal of the oscillator circuit (200B); a linear regulator (330) including an NMOS transistor; and a turn-on bias circuit (340) configured to receive an output voltage of the charge pump circuit (320) and generate a bias voltage at a gate of the NMOS transistor.

Images