PHOTICAL DEVICE MANUFACTURED BY SELF-ALIGNING PROCESSES

Abstract

A photonic device comprises a substrate, a p-doped component positioned above the substrate, an n-doped component positioned above the substrate, an optical absorption layer positioned above the substrate, and a charging layer positioned above the substrate. The optical absorption layer is positioned between the p-doped and n-doped components. The optical absorption layer and the substrate have different material compositions. A charging layer is positioned between the p-doped and n-doped components. The charging layer has a first face that is essentially linear. This first face is in direct contact with the optical absorption layer.

Description

PRIORITY

[0001] This application is a U.S. patent application of U.S. Provisional Application 63 / 519,509, filed August 14, 2023, entitled "Silicon Photonic Device," the disclosure of which is hereby incorporated by reference in its entirety. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and designs have produced generations of ICs, with each generation featuring smaller and more complex circuits than the previous generation. As ICs have evolved, feature density (i.e., the number of interconnected devices per chip area) has generally increased, while feature size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This downscaling process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] As semiconductor devices become smaller yet more powerful, they can be used in a wide variety of applications. These applications can include photonic devices, such as semiconductor image sensors used to detect radiation (e.g., visible light). For example, complementary metal oxide semiconductor (CMOS) image sensors and charge-coupled device (CCD) sensors are used in various applications such as digital cameras, mobile phones, medical devices, automotive sensors, etc. However, as devices become smaller, it can become more difficult to manufacture certain components of photonic devices with the desired precision, for example, with regard to the size and / or location of these specific components. This can lead to a degradation in the performance of the photonic devices.What is needed is an improved method for manufacturing photonic device components with sufficient precision in terms of size and / or location, even as the size of semiconductor devices continues to decrease with each technology generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with standard industry practice, various elements are not drawn to scale and are for descriptive purposes only. Indeed, the dimensions of the various elements may be arbitrarily exaggerated or reduced for clarity of description. Fig. 1A shows a planar top view of a photonic semiconductor device according to various aspects of the present disclosure. Fig. 1B shows a diagram corresponding to an electric field of a photonic semiconductor device according to various aspects of the present disclosure. The Fig. 2 to 34 show a sequence of cross-sectional side views of a photonic semiconductor device at various stages of fabrication associated with a process flow according to various aspects of the present disclosure. Fig. 35 shows a planar top view of a photonic device according to various aspects of the present disclosure. The Fig. 36A to 36H illustrate several cross-sectional side views of a portion of a photonic semiconductor device corresponding to several embodiments according to various aspects of the present disclosure. Fig. 37 shows a sequence of cross-sectional side views of a photonic semiconductor device at various manufacturing stages associated with a process flow according to various aspects of the present disclosure. Fig. 38 shows a flow diagram illustrating a method of fabricating a photonic device according to various aspects of the present disclosure. Fig. 39 shows a block diagram of a system for manufacturing integrated circuits according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, in the following description, forming a first element over or on top of a second element may cover embodiments in which the first and second elements are formed in direct contact, and may also cover embodiments in which additional elements may be formed between the first and second elements such that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.

[0006] Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, impose any relationship between the various described embodiments and / or configurations. Furthermore, the formation of an element on, connected to, and / or coupled to another element in the following present disclosure may include embodiments where the elements are formed in direct contact, and may also include embodiments where additional elements may be formed that lie between the elements such that the elements need not be in direct contact. Furthermore, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "top," "over," "bottom," "beneath," "upward," "downward," "topmost," "lowermost," etc., as well as derivatives thereof (e.g.,For the purpose of simplifying this disclosure, spatially relative terms (e.g., "horizontal," "downward," "upward," etc.) are used to relate one element to another element. The spatially relative terms are intended to cover different orientations of the device, including the elements. Still further, when a number or range of numbers is described with "about," "approximately," and the like, the term is intended to include numbers that are within a reasonable range of the described number, such as within + / - 10% or other values ​​of the described number, as understood by those skilled in the art. For example, the term "about 5 nm" includes the dimensional range of 4.5 nm to 5.5 nm.

[0007] The present disclosure relates generally to semiconductor devices, and more particularly to photonic semiconductor devices. For example, the present disclosure presents a method for fabricating an avalanche photodiode (APD) through a self-aligned process. By using such a self-aligned process, the resulting APD can achieve a narrow width for its doped regions (e.g., for a charging layer) as well as a substantially vertical doping profile for the portion of the doped region directly adjacent to an optical absorption layer. The various aspects of the present disclosure will now be described in more detail below.

[0008] With reference to the Fig. 1A and Fig. 1B, there is shown a schematic fragmentary plan view of a portion 100 of an APD and a diagram 110 associated with the APD 100. The APD 100 in Fig. 1A has an X-axis running in a first, horizontal direction and a Y-axis running in a second, horizontal direction. The APD 100 includes several components arranged side by side along the X-axis. For example, the APD 100 includes a p+ contact, an optical absorption layer, a charging layer, a multiplication layer, an n+ contact, and a substrate. The substrate may be part of a semiconductor substrate. For example, the substrate may include a silicon material. The p+ contact may include silicon doped with a p-type dopant, and the n+ contact may include silicon doped with an n-type dopant. The p+ contact and the n+ contact may function as the p-region and n-region of a pn diode. The optical absorption layer—which in some embodiments may include a germanium material—is configured to absorb radiation, such as visible light.The ML—which may include silicon in some embodiments—may perform a similar function to an amplifier and is configured to control a multiplication factor and breakdown voltage of the APD 100. The charging layer is implemented to divide or otherwise separate the electric fields of the optical absorption layer and the ML. For example, the charging layer may include a silicon material doped with a p-type dopant, but the dopant concentration of the charging layer is significantly lower than the dopant concentration of the p+ contact.

[0009] Diagram 110 in Fig. 1B also has an X-axis that runs in a horizontal direction and a Z-axis that runs in a vertical direction. The positions along the X-axis of Fig. 1B correspond to the positions along the X-axis of Fig. 1A. The Z-axis shows the intensity of the electric field. More specifically, the plot 110 includes a curve 120 that corresponds to the electric field of the APD 100 in different regions of the APD 100. For example, the electric field of the ML is the strongest, which is reflected in the plot 120 having the greatest height at locations corresponding to the ML. The electric field of the optical absorption layer is significantly weaker, which is reflected in the plot 120 having a significantly lower height at locations corresponding to the optical absorption layer. Because the charging layer separates the ML and the optical absorption layer, the electric field of the charging layer changes such that it is stronger near the ML and decreases toward the optical absorption layer.One of the inventive aspects of the present invention relates to the formation of the charging layer such that it can achieve a relatively small width while being directly adjacent to the optical absorption layer, wherein an interface between the charging layer and the optical absorption layer has a substantially vertical doping profile.

[0010] The manufacturing process flow of the APD 100 will now be described below with reference to the Fig. 2 to 34, which are cross-sectional side views of the APD 100 at various stages of production. The cross-sectional views are taken along a plane defined by a horizontal X-direction (or X-axis) and a vertical Z-direction (or Z-axis).

[0011] With reference to Fig. 2, the fabrication of the APD 100 includes providing a substrate 210 as part of a wafer. The substrate 210 may contain a semiconductor material. For example, the substrate 210 may contain silicon as the semiconductor material. An insulating layer 220 is formed over the substrate 210. In some embodiments, the insulating layer 220 may contain silicon oxide (SiO2). A further semiconductor layer 230 is formed over the insulating layer 220. For example, the semiconductor layer 230 may also contain silicon with a lattice direction <100> or silicon with a lattice direction <111> In this way, substrate 210, insulating layer 220, and semiconductor layer 230 form a silicon-on-insulator (SOI) structure. The SOI structure can provide lower parasitic capacitance, which contributes to improved device performance.

[0012] With reference to Fig. 3, an etching process 250 is performed on the APD 100 to form a plurality of openings in the semiconductor layer 230. In some embodiments, the etching process 250 comprises a lithography process, which may include one or more photoresist spin coating processes, photoresist exposure processes, post-exposure baking processes, photoresist development processes, etc. (which are not necessarily performed in this order). In the lithography process, a patterned photoresist mask (not separately shown here for simplicity) may be formed over the semiconductor layer 230. The etching process 250 may include one or more dry etching processes or wet etching processes that partially etch away the semiconductor layer 230. The patterned photoresist mask serves as a protective mask to prevent the underlying portions of the semiconductor layer 230 from being etched during the etching process 250.By performing the etching process 250, openings 260 and 261 are formed in the semiconductor layer 230. The openings 260 and 261 each extend partially downward in the Z direction through the semiconductor layer 230. The patterned photoresist mask can be removed after the formation of the openings 260 and 261, for example, by a photoresist ashing process or a photoresist stripping process.

[0013] With reference to Fig. 4, a deposition process 270 is performed on the APD 100 to form a dielectric layer 280. The deposition process 270 may include a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or combinations thereof. In some embodiments, the dielectric layer 280 includes silicon oxide. The dielectric layer 280 is deposited over the semiconductor layer 230 and fills the openings 260 and 261.

[0014] With reference to Fig. 5, an etching process 290 is performed on the APD 100 to form an opening 300. In some embodiments, the etching process 290 includes a dry etching process, a wet etching process, or combinations thereof. It should be understood that a lithography process may also be performed to form a patterned photoresist mask that may be used as a protective mask while performing the etching process 290. As a result of the etching process 290, the opening 300 extends downward in the Z-direction through the dielectric layer 280 and partially through the semiconductor layer 230. Note that the etching process 290 is specifically configured to ensure that a segment 230A of the semiconductor layer 230 remains after performing the etching process 290. In other words, the segment 230A of the semiconductor layer 230 is exposed through the opening 300.

[0015] With reference to Fig. 6, a selective growth process 310 is performed on the APD 100 to form an optical absorption layer 320 in the opening 300. More specifically, the segment 230A serves as a seed layer during the selective growth process 310. The selective growth process 310 may then use a deposition technique (such as CVD) to grow a semiconductor material on the segment 230A. In some embodiments, the semiconductor material grown on the segment 230A may include germanium. This germanium material may be referred to as the optical absorption layer 320. The optical absorption layer 320 is selectively grown on the segment 230A (which, in this embodiment, includes silicon), but not on the upper surfaces of the dielectric layer 280 (which, in this embodiment, includes silicon oxide). Thus, the optical absorption layer 320 is grown within the opening 300, but not outside it. Note that in this Fig. 6, the thickness (or height) of the optical absorption layer 320 is configured such that an uppermost surface of the optical absorption layer 320 has a vertically higher position than an uppermost surface of the semiconductor layer 230. However, this need not be the case in alternative embodiments.

[0016] Furthermore, although germanium is used as an example material for the optical absorption layer 320, it is to be understood that this is not to be construed as limiting unless otherwise stated. For example, in some embodiments, a silicon germanium (Si x Ge 1-x , where x is between 0 and 1) may be used to implement the optical absorption layer 320, depending on the operating wavelength (e.g., in the range between about 1100 nm and about 2000 nm) of the APD 100.

[0017] After forming the optical absorption layer 320 in the opening 300, several deposition processes (e.g., CVD, PVD, ALD, or combinations thereof) may be performed to form additional layers, such as layers 330, 340, and 350, over the optical absorption layer 320 in the opening 300. For example, layer 330 may contain a semiconductor material such as silicon, layer 340 may contain a dielectric such as silicon oxide, and layer 350 may contain another semiconductor material such as polysilicon. Layers 330-350 may have a significantly smaller thickness compared to the optical absorption layer 320. In the embodiment shown, the combination of the optical absorption layer 320 and layers 330-350 does not yet completely fill the opening 300. In other words, a top surface of layer 350 has a lower vertical height than a top surface of the dielectric layer 280.Layers 330-350 may be used together to serve as a mask structure in later processes, as described in more detail below.

[0018] With reference to Fig. 7, a dielectric removal process 360 is performed on the APD 100 to remove the dielectric layer 280. The dielectric removal process 360 is configured to remove the dielectric layer 280 without significantly damaging the semiconductor layer 230, the optical absorption layer 320, or the layers 330-350. For example, the dielectric removal process 360 may include one or more etch processes configured with a sufficiently high etch selectivity between the dielectric layer 280 and the other layers 230 and 320-350. In some embodiments, the etching processes of the dielectric removal process 360 may be configured such that the dielectric layer 280 may be etched away at a rate that is more than five times or more than ten times higher than that of the other layers 230 and 320-350.Consequently, it is possible to remove the dielectric layer 280 while the other layers 230 and 320-350 substantially remain.

[0019] With reference to Fig. 8, a patterned photoresist mask 370 is formed over a portion of the APD 100. For example, the patterned photoresist mask 370 is formed to cover a "right side" of the APD 100, e.g., the portion of the semiconductor layer 230 up to the "right side" of the optical absorption layer 320, as well as a "right-side" portion of the layer 350 from the top. Subsequently, a doping process 380 is performed to convert the portion of the semiconductor layer 230 on the "left side" of the optical absorption layer 320 into a p+ contact 400. For example, the doping process 380 may implant a p-type dopant into the exposed portion of the semiconductor layer 230 (i.e., the portion of the semiconductor layer 230 on the "left side" of the optical absorption layer 320).The patterned photoresist mask 370 protects the various underlying layers (including the semiconductor layer 230 on the "right side" of the optical absorption layer 320) from dopant implantation. Similarly, layers 330-350 can also serve as a mask structure to protect the underlying optical absorption layer 320 from dopant implantation. This converts the semiconductor layer 230 on the "left side" of the optical absorption layer 320 into the p+ contact 400, while the semiconductor layer 230 on the "right side" of the optical absorption layer 320 remains substantially undoped at this stage of manufacturing. It should be understood that the p+ contact 400 corresponds to the structure described above with reference to FIG. Fig. 1 described p+ contact.

[0020] Note that as an inherent result of the unique manufacturing processes described above, the optical absorption layer 320 is formed directly adjacent to the p+ contact 400. For example, etching the opening 300 (see Fig. 5) and the subsequent selective growth of the optical absorption layer 320 in the opening 300 such that the optical absorption layer 320 directly adjoins the semiconductor layer 230 on its "left side." Subsequently, the doping process 380 converts the portion of the semiconductor layer 230 directly adjacent to the "left side" of the optical absorption layer 320 into the p+ contact 400, while layers 330-350 protect the optical absorption layer 320 from doping. Thus, the optical absorption layer 320 is formed to directly adjoin the p+ contact 400 through self-alignment.

[0021] With reference to Fig. 9, the patterned photoresist mask 370 is removed, for example, by a photoresist ashing or photoresist stripping process. Next, another patterned photoresist mask 410 is formed over a portion of the APD 100. For example, the patterned photoresist mask 410 is formed to cover a "left side" of the APD 100, such that it overlies, for example, the p+ contact 400, the optical absorption layer 320 and the overlying layers 330-350, and a portion of the semiconductor layer 230 on the "right side" of the optical absorption layer 320.

[0022] Subsequently, a doping process 430 is performed to convert the portion of the semiconductor layer 230 not covered by the patterned photoresist mask 410 into an n+ contact 450. For example, the doping process 430 may implant an n-type dopant into the exposed portion of the semiconductor layer 230. The patterned photoresist mask 410 protects the various underlying layers from the implantation of the dopant. As a result, the exposed portion of the semiconductor layer 230 is converted into the n+ contact 450, while the portion of the semiconductor layer 230 on the “right side” of the optical absorption layer 320, which is covered by the patterned photoresist mask 410, remains substantially undoped at this stage of manufacturing. It is understood that the n+ contact 450 corresponds to the process described above with reference to Fig. 1 corresponds to the n+ contact described.

[0023] With reference to Fig. 10, the patterned photoresist mask 410 is removed, for example, by a photoresist ashing or photoresist stripping process. Next, another patterned photoresist mask 470 is formed over portions of the APD 100. For example, the patterned photoresist mask 470 is formed to define an opening 480 that exposes a portion of the semiconductor layer 230 directly adjacent to a "right side" of the optical absorption layer 320. The opening 480 also exposes a portion of the layer 350. The remaining components of the APD 100 are covered by the patterned photoresist mask 470.

[0024] Subsequently, a doping process 490 is performed to convert the portion of semiconductor layer 230 not covered by patterned photoresist mask 470 into a charging layer 500. For example, doping process 490 may implant a p-type dopant into the exposed portion of semiconductor layer 230. Patterned photoresist mask 470 and layers 330-350 protect the various underlying layers from the implantation of the dopant. As a result, the portion of semiconductor layer 230 exposed by opening 480 is converted into charging layer 500, while the portion of semiconductor layer 230 covered by patterned photoresist mask 470 remains substantially undoped at this stage of fabrication. Optical absorption layer 320 also remains undoped due to the protection provided by layers 330-350. It is understood that the charging layer 500 of the above with reference to Fig. 1 described loading layer.

[0025] It is also clear that the dose of the p-dopant of the doping process 490 is significantly lower than the dose of the p-dopant of the doping process 380 (see Fig. 8) used to form the p+ contact 400. Thus, the resulting charging layer 500 formed by the doping process 490 is significantly more lightly doped (i.e., it has a significantly lower dopant concentration) compared to the p+ contact 400. It will further be appreciated that the dopant concentration levels in the various doped regions of the APD 100 can be adjusted according to a breakdown condition (e.g., to avoid breakdown) and / or to produce a desired electric field profile.

[0026] Note that as a further inherent result of the unique manufacturing processes described above, the charging layer 500 is formed to directly adjoin the optical absorption layer 320. For example, etching the opening 300 (see Fig. 5) and the subsequent selective growth of the optical absorption layer 320 in the opening 300 such that the optical absorption layer 320 directly adjoins the portion of the semiconductor layer 230 on its "right side." Subsequently, in the doping process 490, the portion of the semiconductor layer 230 directly adjacent to the "right side" of the optical absorption layer 320 is converted into the charging layer 500, while layers 330-350 protect the optical absorption layer 320 from doping. Thus, the charging layer 500 is formed to directly adjoin the optical absorption layer 320 through self-alignment.

[0027] It should also be understood that a width (e.g., horizontal dimension in the X-direction) of the charging layer 500 can be flexibly configured. For example, the width of the charging layer 500 is determined at least in part by a width of the opening 480 defined by the patterned photoresist mask 470. In embodiments where the width of the charging layer 500 is desired to be somewhat smaller, the patterned photoresist mask 470 can be configured to define a narrower opening exposing a smaller portion of the underlying semiconductor layer 230, thereby allowing the resulting charging layer 500 (formed by the doping process 490) to have a narrower width.Conversely, in embodiments where the width of the charging layer 500 is desired to be somewhat larger, the patterned photoresist mask 470 may be formed to define a wider opening that exposes a larger portion of the underlying semiconductor layer 230, and this allows for a larger width of the resulting charging layer 500 (formed by the doping process 490).

[0028] With reference to Fig. 11, the patterned photoresist mask 470 is removed, for example, by a photoresist ashing or photoresist stripping process. Subsequently, a deposition process 510 is performed to form a passivation layer 520 over the other components of the APD 100. For example, the deposition process 510 may include a CVD process, a PVD process, an ALD process, or combinations thereof, in which a dielectric is deposited as a passivation layer. In some embodiments, the deposited dielectric may include a silicon nitride material or a silicon oxide material. The resulting passivation layer 520 protects the underlying components of the APD 100 from contaminants and / or moisture.

[0029] The Fig. 2 to 11, a process flow according to a first embodiment of the present disclosure was shown. Fig. 12 to 18 illustrate a process flow according to a second embodiment of the present disclosure. For consistency and clarity, similar components in the first and second embodiments are denoted the same.

[0030] With reference to Fig. 12, the APD 100 is in the same production stage as above with reference to Fig. 8. This means that the APD 100 performs the processing steps of the Fig. 2 to 8, which resulted in the formation of the optical absorption layer 320, the layers 330 to 350 over the optical absorption layer 320, and the p+ contact 400. Since these processes are essentially the same in the first and second embodiments, descriptions of these processes will not be repeated here for the sake of simplicity.

[0031] With reference to Fig. 13, the patterned photoresist mask 370 is removed, for example, by a photoresist ashing or photoresist stripping process. Thereafter, another patterned photoresist mask 540 is formed over a portion of the APD 100. For example, the patterned photoresist mask 540 is formed to cover a "left side" of the APD 100, such that it overlies, for example, the p+ contact 400, the optical absorption layer 320 and the overlying layers 330-350, and a portion of the semiconductor layer 230 on the "right side" of the optical absorption layer 320. The patterned photoresist mask 540 is formed to define an opening 480 that exposes a portion of the semiconductor layer 230 directly adjacent to a "right side" of the optical absorption layer 320. The opening 480 also exposes a portion of the layer 350.The remaining components of the APD 100 are covered by the patterned photoresist mask 540.

[0032] Subsequently, a doping process 550 is performed to convert the portion of semiconductor layer 230 not covered by patterned photoresist mask 540 into charging layer 500. For example, doping process 550 may implant a p-type dopant into the exposed portion of semiconductor layer 230. Patterned photoresist mask 540 and layers 330-350 protect the various underlying layers from the implantation of the dopant. As a result, the portion of semiconductor layer 230 exposed by opening 480 is converted into charging layer 500, while the portion of semiconductor layer 230 covered by patterned photoresist mask 540 remains substantially undoped at this stage of fabrication. Optical absorption layer 320 also remains undoped due to the protection provided by layers 330-350.As described above, the charging layer 500 is significantly less doped (e.g., it has a significantly lower dopant concentration) than the p+ contact 400, although both contain a p-type dopant.

[0033] With reference to Fig. 14, the patterned photoresist mask 540 is removed, for example, by a photoresist ashing or photoresist stripping process. Subsequently, a sputtering process 570 is performed on the APD 100 to form a spacer layer 580. In some embodiments, the sputtering process 570 forms silicon oxide as the material for the spacer layer 580. The sputtering process 570 is performed such that the spacer layer 580 covers the exposed top surfaces and side surfaces of the APD 100, including the top surfaces and side surfaces of the exposed portions of the optical absorption layer 320 and layers 330-350. In some embodiments, the sputtering process 570 is configured such that the spacer layer 580 has a substantially uniform thickness.It will be appreciated that this thickness of the spacer layer 580 may be used to control the width of spacers to be formed in a subsequent process described below.

[0034] With reference to Fig. 15, one or more etch processes 590 are performed to convert the spacer layer 580 into spacers. More specifically, the one or more etch processes 590 may include one or more isotropic etch processes (e.g., wet etching) that etch away portions of the spacer layer 580. The isotropic etch processes are configured to have a sufficiently high etch selectivity between the spacer layer 580 and the remaining components of the APD 100 (e.g., the p+ contact 400, the layer 350, the charging layer 500, and the semiconductor layer 230). Therefore, etching the spacer layer 580 does not have a significant impact on the remaining components of the APD 100. The portions of the spacer layer 580 disposed on the exposed side surfaces of the optical absorption layer 320 and layers 330-350 are significantly taller than the portions of the spacer layer 580 disposed elsewhere on the APD 100.As a result, after performing the etching processes 590, a significant portion of the spacer layer 580 remains, disposed on the exposed side surfaces of the optical absorption layer 320 and the layers 330-350. These remaining portions of the spacer layer 580 are referred to below as spacers 580A and 580B. The spacers 580A and 580B may each have a width 600 (e.g., a horizontal dimension measured in the X-direction). Again, the value of the width 600 is determined by the thickness of the spacer layer 580, as defined above with reference to FIG. Fig. 14 described sputtering process 570.

[0035] With reference to Fig. 16, a patterned photoresist mask 610 is formed over a portion of the APD 100. For example, the patterned photoresist mask 610 is formed to cover a "left side" of the APD 100, such that it is formed approximately over the p+ contact 400, over a portion of the optical absorption layer 320 and overlying layers 330-350, and over the semiconductor layer 230. The patterned photoresist mask 610 is formed to define an opening 620 that exposes the charging layer 500, as well as a portion of layer 350 and spacer 580B. Subsequently, a doping process 630 is performed that converts the exposed portion of the charging layer 500 into the n+ contact 450. For example, the doping process 430 may implant an n-type dopant into the exposed portion of the charging layer 500. The patterned photoresist mask 610 protects the various underlying layers from the implantation of the dopant material.The spacer 580B also protects a portion of the underlying charging layer 500 from the implantation of the dopant material.

[0036] As a result of the doping process 630, the exposed portion of the charging layer 500 is converted into the n+ contact 450, while the portion of the semiconductor layer 230 covered by the patterned photoresist mask 610 remains substantially undoped at this manufacturing stage. The remaining portion of the charging layer 500 below the spacer 580B also remains substantially unaffected by the doping process 630. In other words, the remaining portion of the charging layer 500 is still lightly p-doped at this manufacturing stage. In this way, a substantially elongated and narrow profile (e.g., with a width of 600) is achieved for the charging layer 500 herein, and it directly adjoins the optical absorption layer 320. Such a physical property of the charging layer 500 is an inherent result of implementing the unique manufacturing process flow of the present disclosure.For example, the charging layer 500 is formed herein by self-alignment such that its horizontal position is defined by the spacer 580B. Because the spacer 580B is formed to directly adjoin the optical absorption layer 320, the charging layer 500 automatically assumes the horizontal position of the spacer 580B and therefore also directly adjoins the optical absorption layer 320. Furthermore, because the charging layer 500 is defined by the spacer 580B, the charging layer 500 substantially assumes the width 600 of the spacer 580B. In this way, a lightly p-doped narrow charging layer 500 with a substantially vertical shape is formed directly adjacent to the optical absorption layer 320, which is one of the unique physical properties of the present disclosure.

[0037] With reference to Fig. 17, the patterned photoresist mask 610 is removed, for example, by a photoresist ashing or photoresist stripping process. Thereafter, another patterned photoresist mask 650 is formed. The patterned photoresist mask 650 exposes a portion of the semiconductor layer 230 (which was previously covered by the patterned photoresist mask 610, see Fig. 16), but covers a remainder of the APD 100. Subsequently, a doping process 660 is performed. The doping process 660 may implant an n-type dopant into the semiconductor layer 230. The patterned photoresist mask 650 protects the various underlying layers from the implantation of the dopant. This converts the semiconductor layer 230 into an n++ contact 450A. It is understood that a higher dosage of the n-type dopant may be used in the doping process 660 than in the doping process 630. This results in the dopant concentration of the n-type dopant in the n++ contact 450A being higher than the dopant concentration of the n-type dopant in the n+ contact 450. It is understood that the n+ contact 450 and the n++ contact 450A together correspond to the dopant concentration described above with reference to Fig. 1 described n+ contact.

[0038] With reference to Fig. 18, the patterned photoresist mask 650 is removed, for example, by a photoresist ashing or photoresist stripping process. Subsequently, the deposition process 510 described above is performed, forming the passivation layer 520 over the other components of the APD 100. For example, the deposition process 510 may include a CVD process, a PVD process, an ALD process, or combinations thereof, in which a dielectric is deposited as a passivation layer. In some embodiments, the deposited dielectric may include a silicon nitride material or a silicon oxide material. The resulting passivation layer 520 protects the underlying components of the APD 100 from dirt particles and / or moisture.

[0039] The Fig. 2 to 11 and Fig. 12 to 18 have shown process flows according to the first embodiment and the second embodiment of the present disclosure, wherein the etching of the semiconductor layer 230 (e.g., the etching process 290 of Fig. 5) is carried out before the various doping processes described above are carried out, which form the p+ contact 400 and the n+ contact 450. In other words, in the first embodiment and the second embodiment described above with reference to the Fig. 2 to 18, the doping processes used to form the p+ contact 400 and the n+ contact 450 are carried out after the selective growth process for forming the optical absorption layer 320. However, such a process sequence is not limiting unless otherwise claimed. For example, the Fig. 19 to 33 (described in more detail below) illustrate a process flow according to a third embodiment of the present disclosure, in which doping processes for forming the n+ contact and the p+ contact are performed before the selective growth process 320 for forming the optical absorption layer 320 is performed. For consistency and clarity, similar components in the first embodiment, the second embodiment, and the third embodiment are referred to alike.

[0040] With reference to Fig. 19, the APD 100 is in the same production stage as above with reference to Fig. 2. That is, the APD 100 includes the substrate 210, the insulating layer 220, and the semiconductor layer 230, but no other manufacturing processes have been performed on the APD 100.

[0041] With reference to Fig. 20, a patterned photoresist mask 680 is formed. The patterned photoresist mask 680 exposes a portion of the semiconductor layer 230 but covers the remainder of the APD 100.

[0042] With reference to Fig. 21, a doping process 690 is performed. The doping process 690 may implant a p-type dopant into the semiconductor layer 230. The patterned photoresist mask 680 protects the underlying semiconductor layer 230 from the implantation of the dopant. As a result, the exposed portion of the semiconductor layer 230 is converted into the p+ contact 400. It is understood that the p+ contact 400 corresponds to the one described above with reference to Fig. 1 described p+ contact.

[0043] With reference to Fig. 22, the patterned photoresist mask 680 is removed, for example, by a photoresist stripping or ashing process. Subsequently, a patterned photoresist mask 700 is formed. The patterned photoresist mask 700 exposes a portion of the semiconductor layer 230 but covers the remainder of the APD 100.

[0044] With reference to Fig. 23, a doping process 710 is performed. The doping process 710 may implant a p-type dopant into the exposed portion of the semiconductor layer 230. The patterned photoresist mask 700 protects the p+ contact 400 and a portion of the semiconductor layer 230 beneath it from the implantation of the dopant. The doping process 710 is performed at a dosage similar to that described above with reference to Fig. 17. As a result, the exposed portion of the semiconductor layer 230 is converted into the n++ contact 450A, similar to the doping process described above with reference to Fig. 17 described n++ contact 450A.

[0045] With reference to Fig. 24, one or more etch processes 720 are performed on the APD 100. The one or more etch processes 720 are performed using a patterned mask layer 730 as a protective mask, such that the portions of the APD 100 underlying the patterned mask layer 730 are not etched by the one or more etch processes 720. In some embodiments, the patterned mask layer 730 may include a dielectric. The patterned mask layer 730 defines an opening 740 that is partially extended vertically downward through the semiconductor layer 230 and the p+ contact 400 by one or more etch processes 720. Note that the top and side surfaces of a portion of the semiconductor layer 230 and a portion of the p+ contact 400 remain exposed through the opening 740 after the one or more etch processes 720 have been performed.

[0046] With reference to Fig. 25, the selective growth process 310 (described above with reference to Fig. 6) is performed on the APD 100 to form the optical absorption layer 320 in the opening 740. As described above, the optical absorption layer 320 may include a germanium material. After the formation of the optical absorption layer 320 in the opening 740, layers 330, 340, and 350 are also formed over the optical absorption layer 320 in the opening 740. For example, layer 330 may include a semiconductor material such as silicon, layer 340 may include a dielectric such as silicon oxide, and layer 350 may include another semiconductor material such as polysilicon. Layers 330-350 may have a significantly smaller thickness compared to the optical absorption layer 320.

[0047] With reference to Fig. 26, the patterned mask layer 730 is removed. Subsequently, a patterned photoresist mask 750 is formed over the APD 100. The patterned photoresist mask 750 exposes the semiconductor layer 230 and a portion of the layer 350, but covers the remainder of the APD 100. In other words, the patterned photoresist mask 750 defines an opening 760 that exposes the top surface of the semiconductor layer 230 and a portion of the top surface of the layer 350, as well as side surfaces of the layers 330-350 and a portion of the side surface of the optical absorption layer 320.

[0048] With reference to Fig. 27, a doping process 770 is performed through opening 760. More specifically, doping process 770 implants a p-type dopant material into the portion of semiconductor layer 230 exposed through opening 760. Patterned photoresist mask 750 and layers 330-350 protect the various layers below from the implantation of the dopant material. As a result, the portion of semiconductor layer 230 exposed through opening 760 is converted into charging layer 500, while the portion of semiconductor layer 230 covered by optical absorption layer 320 remains substantially undoped at this stage of fabrication. Optical absorption layer 320 itself also remains substantially undoped due to the protection provided by layers 330-350. Here too, the dose of the p-dopant material of the doping process 770 is significantly lower than that of the p-dopant material of the doping process 690 (see Fig. 21) used to form the p+ contact 400. Thus, the resulting charging layer 500 formed by the doping process 770 is significantly less doped (i.e., it has a significantly lower dopant concentration) compared to the p+ contact 400.

[0049] Similar to the other embodiments described above, one of the inherent results of the third embodiment of the present disclosure is that the charging layer 500 is still formed directly adjacent to the optical absorption layer 320. For example, the optical absorption layer 320 is formed prior to the charging layer 500, and the charging layer 500 is self-aligned by doping a portion of the semiconductor layer 230 immediately adjacent to the optical absorption layer 320. Therefore, a substantially vertical interface of the optical absorption layer 320 and the charging layer 500 extending in the Z direction can be achieved.Note that another inherent result of the fabrication processes of the third embodiment is that after the formation of the charging layer 500, a substantially undoped segment 230A of the semiconductor layer 230 is still disposed beneath the optical absorption layer 320. This is because this portion of the semiconductor layer 230A is protected from doping during the doping process 770 by the optical absorption layer 320 and the overlying layers 330-350.

[0050] With reference to Fig. 28, the patterned photoresist mask 750 is removed, for example, by a photoresist ashing or photoresist stripping process. Subsequently, the sputtering process 570 (described above with reference to Fig. 14) is performed on the APD 100 to form the spacer layer 580. In some embodiments, the sputtering process 570 forms silicon oxide as the material for the spacer layer 580. The sputtering process 570 is performed such that the spacer layer 580 covers the exposed top surfaces and side surfaces of the APD 100, including the top surfaces and side surfaces of the exposed portions of the optical absorption layer 320 and layers 330-350. In some embodiments, the sputtering process 570 is configured such that the spacer layer 580 has a substantially uniform thickness. As described above, this thickness of the spacer layer 580 can be used to control a width of the spacers subsequently formed on the side surfaces of the optical absorption layer 320 and layers 330-350.

[0051] With reference to Fig. 29, the etching processes 590 (described above with reference to Fig. 15) to convert the spacer layer 580 into spacers 580A and 580B. For example, the one or more etch processes 590 may include one or more isotropic etch processes that etch away portions of the spacer layer 580 disposed on the top surfaces of the p+ contact 400, layer 350, the charging layer 500, and the n++ contact 450A. The spacers 580A and 580B on the side surfaces of the optical absorption layer 320 and layers 330-350 are largely preserved because the etch processes 590 only affect the top portions of these spacers 580A and 580B. As also described above, the initial thickness of the spacer layer 580 (when formed by the sputtering process 570) corresponds to the width 600 of each of the spacers 580A and 580B.It should be understood, however, that the exact value of the width 600 of the two spacers 580A and in this third embodiment is not necessarily the same as the value of the width 600 of the two spacers 580A and in the second embodiment (see . Fig. 15) must be.

[0052] With reference to Fig. 30, a patterned photoresist mask 780 is formed over a portion of the APD 100. For example, the patterned photoresist mask 780 is formed to cover the p+ contact 400, a portion of the optical absorption layer 320 and the overlying layers 330-350, and the n++ contact 450A. Thus, the patterned photoresist mask 780 defines an opening 790 that exposes the charging layer 500, as well as a portion of the layer 350 and the spacer.

[0053] With reference to Fig. 31, a doping process 800 is performed to convert the portion of the charging layer 500 not covered by the patterned photoresist mask 780 or the spacer into the n+ contact 450. For example, the doping process 800 may implant an n-type dopant into the exposed portion of the charging layer 500. The patterned photoresist mask 780, as well as layers 330-350 and the spacer, protect the various layers below from the implantation of the dopant. As a result, the exposed portion of the charging layer 500 is converted into the n+ contact 450, while the portion of the charging layer 500 on the "right side" of the optical absorption layer 320, which is covered by the spacer, still remains substantially undoped at this stage of manufacturing. Note that the doping process 800 may be configured to be more efficient than the doping process 710 (see Fig. 23) used to form the n++ contact 450A uses a lower implantation dose. Therefore, the n+ contact 450 formed by the doping process 800 has a lower dopant concentration than the n++ contact 450A, even though both the n+ contact 450 and the n++ contact 450A are doped with an n-type dopant. It is understood that the n+ contact 450 and the n++ contact 450A together correspond to the dopant described above with reference to Fig. 1 described n+ contact.

[0054] With reference to Fig. 32, the patterned photoresist mask 780 is removed, for example, by a photoresist ashing process or a photoresist stripping process. Thereafter, one or more etching processes 810 are performed to form a plurality of openings. For example, the one or more etching processes 810 may etch an opening 820 into the p+ contact 400, as well as an opening 821 into the n+ contact 450 and the n++ contact 450A.

[0055] With reference to Fig. 33, the above-mentioned with reference to Fig. 11 is performed to form the passivation layer 520 over the other components of the APD 100. For example, the deposition process 510 may include a CVD process, a PVD process, an ALD process, or combinations thereof, in which a dielectric is deposited as a passivation layer. In some embodiments, the deposited dielectric may include a silicon nitride material or a silicon oxide material. The passivation layer 520 completely fills the openings 820-821. The resulting passivation layer 520 protects the underlying components of the APD 100 from contaminants and / or moisture.

[0056] The various dimensions and physical characteristics of the APD 100 will now be described with reference to the Fig. 34 and Fig. 35, which are a fragmentary cross-sectional side view and a planar top view, respectively, of the APD 100 according to an embodiment of the present disclosure. For example, the Fig. 34 and Fig. 35 largely corresponds to the APD shown in the first embodiment of the device described above with reference to Fig. 1 to 11. In this particular embodiment, the n+ contact 450 is formed, but not the n++ contact. In addition, the Fig. 34 does not include the spacers 580A and 580B implemented in the embodiment of the APD 100 formed according to the second embodiment (see Fig. 18) and the third embodiment (see Fig. 33). Nevertheless, unless otherwise stated, the following description of the dimensions and other physical characteristics of the APD 100 applies equally to the APD 100 manufactured according to the second and third embodiments of the manufacturing process flow. It is also clear that the Fig. 34 to 35 show a conductive pad 840 and a conductive pad 841 over the p+ contact 400 and the n+ contact 450, respectively. These conductive pads 840 and 841 are implemented to provide electrical connection to the APD 100.

[0057] As in the Fig. 34-35, the charging layer 500 is located directly adjacent to (i.e., directly contiguous with) the optical absorption layer 320 and the segment 230A of the semiconductor layer 230. In other words, one side surface of the charging layer 500 forms an interface 850 with the side surfaces of the optical absorption layer 320 and the segment 230A, with this interface 850 extending substantially vertically in the Z-direction. This is one of the unique physical characteristics of the APD 100 fabricated according to the present disclosure. Unlike the APD 100 described herein, APDs not fabricated using the unique fabrication process of the present disclosure typically rely on photolithography to define the location of their optical absorption layer and charging layer.However, because the precision of photolithography has limitations—especially given the ever-shrinking size of semiconductor devices—there's a possibility that the optical absorption layer and the charging layer are not directly adjacent to each other. For example, a buffer region (e.g., an undoped region) may be present between the optical absorption layer and the charging layer. Such a buffer region is not configured for light collection and therefore represents undesirable wasted space in the APD.

[0058] Another possibility when using photolithography to define the position of the optical absorption layer and the charging layer is that the charging layer does not need to have a completely vertical side surface facing the optical absorption layer. Instead, the charging layer can have a segmented side surface, with a portion of the side surface extending further into the segment of the semiconductor layer below the optical absorption layer. However, this can result in the strongest electric field being located in the segment of the semiconductor layer below the optical absorption layer, meaning that the electric field in the optical absorption layer itself may not be strong enough. This can degrade the performance of the APD.

[0059] In comparison, the APD 100 herein uses self-alignment processes to define the location of the optical absorption layer 320 and the charging layer 500. This allows the charging layer 500 to be formed immediately adjacent to the optical absorption layer 320 and the segment 230A, while achieving a substantially linear interface 850 extending vertically upward. One advantage is that the buffer region is eliminated, thereby saving valuable device area and improving optical sensing efficiency. Another advantage is that the strongest electric field is maintained within the optical absorption layer 320, which contributes to improving the performance of the APD 100.

[0060] It should be noted that in the Fig. 34 to 35, a distinguished interface 850 is shown, but this is done for simplicity. In an actual fabricated device, the interface 850 may have a more gradient-like profile. This is because dopant diffusion may occur between the charging layer 500 (e.g., containing silicon doped with the p-type dopant) and the optical absorption layer 320 (e.g., containing substantially undoped germanium), and also between the charging layer 500 and the segment 230A (e.g., containing substantially undoped silicon). Due to dopant diffusion, the interface 850 in an actual fabricated APD 100 need not appear as a one-dimensional line, but may extend horizontally for a certain distance in the X direction.In other words, the interface 850 may have a width measured in the X-direction, within which the dopant concentration is higher toward the charging layer 500 and lower toward the optical absorption layer 320 (thereby, for example, exhibiting the gradient-like profile). In some embodiments, such a width may be approximately 8%-12% of a maximum width W. C the loading layer 500, with the maximum width W C itself may be in a range between about 50 nanometers (nm) and about 100 nm. Regardless of the precise horizontal dimension of the interface 850 or its gradient-like profile, the interface 850 extends substantially vertically and linearly in the Z direction, which is one of the unique physical characteristics of the APD 100 of the present disclosure.

[0061] The Fig. 34 to 35 also show a horizontal dimension W Ofor the optical absorption layer 320 and a horizontal dimension W A for the undoped semiconductor layer 230, which is arranged between the charging layer 500 and the n+ contact 450, wherein both W O like W A measured in the X direction. In some embodiments, W O is greater than or equal to W A , and W A is much larger than W C In some embodiments, the horizontal dimension W O in a range between about 300 nm and about 1000 nm, and the horizontal dimension W A lies in a range between about 200 nm and about 400 nm.

[0062] Fig. 34 also shows several horizontal dimensions S1, S2, S4, S5, S P and S N . More precisely, the horizontal dimension S Pa width of a portion of the p+ contact 400 that is located "left" of the opening 260 (and away from the optical absorption layer 320). The horizontal dimension S1 corresponds to a width of the opening 260. The horizontal dimension S2 corresponds to a width of a portion of the p+ contact 400 that is located "right" of the opening 260 (e.g., the portion directly adjacent to the optical absorption layer 320). The horizontal dimension S4 corresponds to a width of a narrower upper portion of the charging layer 500 that is directly adjacent to the optical absorption layer 320. The horizontal dimension S5 corresponds to a width of the opening 261. The horizontal dimension S Ncorresponds to a width of a portion of the n+ contact 450 located to the "right" of the opening 261 (and away from the optical absorption layer 320). In some embodiments, S1 need not be significantly different from S5, but S1 and S5 are greater than or equal to W O In some embodiments, S1 is much larger than S2 and S4, but S2 and S4 need not be significantly different from each other. In some embodiments, S1 ranges between about 550 nm and about 650 nm, and S2 ranges between about 40 nm and about 60 nm. It should be understood that the above dimensional ranges are not randomly selected, but are specifically configured to optimize device performance. For example, these ranges are configured to properly match the electric field strength and / or optical absorption efficiency of the various components of APD 100.

[0063] One of the advantages of the present disclosure is that the horizontal dimensions W A and W C can be controlled precisely. This is because the horizontal dimensions W A and W C be defined by the self-aligned processes described above and not solely based on the performance of photolithography. This can improve process uniformity. For example, multiple APDs 100 formed using the process flows of the present disclosure can have substantially similar values ​​for the horizontal dimensions W A and W C which is desirable from a quality control perspective. In comparison, APDs manufactured using other processes can exhibit significantly greater differences between the different APDs in terms of the dimensions of their optical absorption layer and their charging layer regions.

[0064] Fig. 34 also shows several vertical dimensions V1, V2, V3, V4, and V5 (each measured in the Z direction). For example, V1 is a vertical dimension corresponding to a vertical projection of the optical absorption layer 320 above the charging layer 500. For example, a top surface 860 of the optical absorption layer 320 is at a vertically higher height than a top surface 870 of the charging layer 500. The distance value of these top surfaces 860 and 870 is represented by the vertical dimension V1. Note that the top surface 880 of the n+ contact 450 has a substantially similar vertical height to the top surface 870 of the charging layer 500. Therefore, it can be said that the vertical dimension V1 also corresponds to a vertical distance between the top surface 860 of the optical absorption layer 320 and the top surface 880 of the n+ contact 450.

[0065] V2 is a vertical dimension corresponding to a vertical projection of the n+ contact 450 above the semiconductor layer 230. For example, the top surface 880 of the n+ contact 450 is at a vertically higher height than a top surface 890 of the semiconductor layer 230. The distance value of these top surfaces 880 and 890 is represented by the vertical dimension V2. Note that the n+ contact 450 has another upward-facing surface 881 exposed through the opening 261, and that this upward-facing surface 881 is at the same vertical height as the top surface 890 of the semiconductor layer 230. It can therefore be said that the vertical dimension V2 also corresponds to a vertical distance between the top surface 880 and the upward-facing surface 881 of the n+ contact 450.It is also clear that the above descriptions regarding V2 can apply not only to the n+ contact 450, but also to the p+ contact 400.

[0066] V3 is a vertical dimension corresponding to the distance between the upward-facing surface 881 and a top surface 900 of the insulating layer 220, which also coincides with the bottom surface of the n+ contact 450. V4 is a vertical dimension corresponding to the distance between the top surface 900 and a top surface 910 of the substrate 210, which also coincides with the bottom surface of the insulating layer 220. In other words, V4 corresponds to a thickness of the insulating layer 220. V5 is a vertical dimension corresponding to the distance between the top surface 910 and the bottom surface 911 of the substrate 210. In other words, V5 corresponds to a thickness of the substrate 210. It is also clear that the above descriptions regarding V3 can apply not only to the n+ contact 450, but also to the p+ contact 400.

[0067] It is understood that the vertical dimension V1 depends on the process configurations of the selective growth process 310 described above (see Fig. 6). For example, a longer growth time may result in higher V1. In the illustrated embodiment, V1 is a positive value, meaning that the top surface 860 is vertically higher than the top surface 870. However, this may not be the case in alternative embodiments. In other words, in some embodiments, the top surface 860 may be vertically lower than the top surface 870. The vertical dimensions V2 and V3 are configured based on an optical wavelength of the light to be detected by the APD 100, and the vertical dimensions V4 and V5 can be flexibly configured depending on manufacturing processing requirements.

[0068] Another unique physical characteristic of the APD 100 herein concerns the relative vertical alignments between the bottom surface 861 of the optical absorption layer 320 and the upward-facing surface 890 (of the semiconductor layer 230), or the upward-facing surface 881 (of the n+ contact 450), or an upward-facing surface 920 (of the p+ contact 400). Specifically, an APD formed by a different manufacturing method than the present disclosure document may have openings for its optical absorption layer and the n+ and p+ contacts etched simultaneously. That is, the opening in which the optical absorption layer is formed is etched at the same time as the openings in the n+ contact and the p+ contact, and the openings are etched into the same type of material (e.g., silicon).Accordingly, an optical absorption layer formed by fabrication methods other than those of the present disclosure typically has a bottom surface that is substantially coplanar with, or at a similar vertical height to, the upwardly facing surfaces of the p+ and n+ contacts exposed by the openings in the p+ and n+ contacts.

[0069] In contrast, the unique manufacturing process flows of the present disclosure either etch the opening 300 for the optical absorption layer 320 (see Fig. 5), after the openings 260-261 for the p+ contact 400 and the n+ contact 450 (see Fig. 3) have been etched, as is the case in the first and second embodiments of the process flow described herein, or they etch the opening 740 for the optical absorption layer 320 (see Fig. 24) before the openings 820-821 for the p+ contact and the n+ contact 450 and the n++ contact 450A (see Fig. 32), as is the case with the third embodiment of the process flow described herein. Because the openings for the optical absorption layer 320 and the p+ contact 400 and the n+ contact 450 are etched at different times, the depth of these openings may differ. Indeed, it may be desirable to configure the opening 300 or the opening 740 for the optical absorption layer 320 to have a greater depth than the openings for the p+ contact 400 and the n+ contact 450 to maximize the optical sensing efficiency of the APD 100.Therefore, one of the inherent results of the unique manufacturing process flow herein is that the bottom surface 861 of the optical absorption layer 320 is at a lower vertical elevation than the upward-facing surfaces 920 of the p+ contact 400 located below the opening 260 and / or the upward-facing surface 890 of the semiconductor layer 230 or the upward-facing surface 881 of the p+ contact 400 located below the opening 261. Such a unique physical characteristic may be used alone or in combination with the other unique physical characteristics described above as an indication to determine whether an APD was fabricated using the unique process flows of the present disclosure.

[0070] It will also be appreciated that while segment 230A of semiconductor layer 230 located beneath optical absorption layer 320 largely comprises undoped silicon, some portions thereof may also contain a dopant material. For example, dopant diffusion may occur at or near an interface between p+ contact 400 and segment 230A of semiconductor layer 230, allowing p-type dopant to diffuse from p+ contact 400 into portions of segment 230A located near the interface. This results in the portion of segment 230A adjacent to p+ contact 400 also being lightly doped with the p-type dopant, although the remainder of segment 230A remains substantially undoped.

[0071] It is further understood that the APD 100 (or at least parts of it) can operate similarly to a waveguide. Assume W = S2 + W O+ S4, h = V3 and H = V2 + V3. Suppose further that P total = the total amount of optical power and that P opt in a range between approximately 0 dBm and approximately 10 dBm. In the single-mode state of the waveguide, the following conditions must be met: WH≤0.3+r1−r2, r=hH≥0.5

[0072] In addition, the following applies to S1 and S5: 0.01×Ptotal≤∫0dPopt⋅dx which means that the total energy of the optical power propagation on both sides of the platform must be less than 0.01%, which is an optional condition.

[0073] In the multimode state of the waveguide, the following applies to S1 and S5: 0.05×Ptotal≤∫0dPopt⋅dx is an optional condition.

[0074] It is further understood that the precise physical appearance of the optical absorption layer 320 and / or its relative arrangement with respect to the charging layer 500 may be configured differently in various embodiments. For example, Fig. 36A to 36H each illustrate a schematic, fragmentary cross-sectional side view of a portion of the APD 100 including the optical absorption layer 320, according to another embodiment of the present disclosure.

[0075] More precisely, Fig. 36A illustrates an optical absorption layer 320 having a substantially rectangular shape, wherein both the top and bottom surfaces of the optical absorption layer 320 are substantially flat. Fig. 36B shows an optical absorption layer 320 having a polygon shape, wherein an uppermost surface of the optical absorption layer 320 is substantially flat, but a lower portion of the optical absorption layer 320 has a trapezoidal shape. Fig. 36C shows an optical absorption layer 320 having an irregular shape, wherein an uppermost surface of the optical absorption layer 320 is substantially curved downward (e.g., has a concave shape), but a lowermost surface of the optical absorption layer 320 is substantially flat. Fig. Figure 36D shows an optical absorption layer 320 having a polygon shape similar to the shape of Fig. 36B, but the optical absorption layer 320 is spaced from the charging layer 500. For example, a portion of a semiconductor layer 230A is disposed between the optical absorption layer 320 and the charging layer 500. Fig. 36E shows an optical absorption layer 320 having a polygonal shape, wherein an upper portion of the optical absorption layer 320 and a lower portion of the optical absorption layer 320 each have a trapezoidal shape. Fig. Figure 36F shows an optical absorption layer 320 having a polygon shape similar to the shape of Fig. 36B, but the optical absorption layer 320 is spaced from the p+ contact 400. For example, a portion of a semiconductor layer 230A is disposed between the optical absorption layer 320 and the p+ contact 400. Fig. 36G shows an optical absorption layer 320 having an irregular shape, wherein a top surface of the optical absorption layer 320 is substantially curved upward (e.g., having a convex shape) and a bottom surface of the optical absorption layer 320 is substantially curved downward (e.g., having a convex shape). Fig. 36H shows an optical absorption layer 320 with an irregular shape, where a top surface of the optical absorption layer 320 is substantially curved upward (e.g., having a convex shape) and a bottom surface of the optical absorption layer 320 is substantially flat. Furthermore, a passivation layer is implemented not only on the top surface of the optical absorption layer 320, but also on portions of a top surface of the p+ contact 400 and a top surface of the charging layer 500. The passivation layer 930 protects the charging layer 500 from air or other contamination sources.

[0076] In relation to Fig. 37, an optical intensity profile 940 is shown in a cross-sectional side view of the APD 100. The optical intensity profile 940 corresponds to the optical radiation (e.g., in the form of a light beam) that is injected into the APD 100, for example, into the optical absorption layer 320. The various dimensions of the APD 100 are specifically configured to ensure that the optical radiation is completely absorbed by the optical absorption layer 320. For example, a dimension H1 corresponds to a measure of the vertical projection of the p+ contact 400. In some embodiments, H1 is substantially equal to the vertical dimension V2 described above with reference to Fig. 34. A dimension H2 corresponds to an overlap amount of the optical absorption layer 320 and the p+ contact 400. In some embodiments, H2 is greater than about 10 nm. A dimension H3 corresponds to a total height of the optical absorption layer 320. A dimension H4 corresponds to the desired length (in the Z-direction) of the optical intensity profile 940. In some embodiments, H3 is greater than or equal to H4 because it is desirable for H3 to overlap the optical intensity profile 940.

[0077] The above descriptions refer to the implementation of the APD 100 as part of an image sensor device. However, it should be understood that the APD 100 (or its components) may also be used in the manufacture of three-dimensional integrated circuits (3DICs). For example, a 3DIC manufacturing system may include an optical transmission path in which a photodetector is used. Such a photodetector is configured to detect light and may operate in a similar manner to the APD 100 described above. Therefore, in some embodiments, the APD 100 may be implemented as a replacement for the photodetector in the optical transmission path of the 3DIC manufacturing system. In such a system, the APD 100 may operate in conjunction with waveguide components to establish an optical transmission path. The structural arrangement of the APD 100 in such a system (e.g.,as a photodetector in the 3DIC system) is otherwise essentially similar to the APD 100 described above.

[0078] Fig. 38 is a flowchart illustrating a method 1000 for fabricating an image sensor device, such as an APD, according to embodiments of the present disclosure. The method 1000 includes a step 1010 of forming a semiconductor layer over a substrate.

[0079] The method 1000 includes a step 1020 of etching an opening into the semiconductor layer.

[0080] The method 1000 includes a step 1030 of forming an optical absorption layer on a portion of the semiconductor layer exposed by the opening using a selective growth process.

[0081] The method 1000 includes a step 1040 for forming a charging layer directly adjacent to the optical absorption layer. The charging layer forms a substantially straight interface with the optical absorption layer and a portion of the semiconductor layer.

[0082] The method 1000 includes a step 1050 of forming a passivation layer over the optical absorption layer and the charging layer.

[0083] It is understood that the method 1000 may include further steps performed before, during, or after steps 1010-1050. For example, in some embodiments, the method 1000 may include a step of forming a p-contact in a first portion of the semiconductor layer disposed on a first side of the optical absorption layer by a first doping process. The optical absorption layer and a second portion of the semiconductor layer are protected from doping by the first doping process. The method 1000 may further include a step of forming an n-contact in a second portion of the semiconductor layer disposed on a second side of the optical absorption layer by a second doping process. The second side is opposite the first side. The optical absorption layer and the p-contact are protected from doping by the second doping process.The charging layer is formed in a third portion of the semiconductor layer by a third doping process performed after the second doping process. In some embodiments, method 1000 may further include a step of forming a mask structure over the optical absorption layer before the p-type contact or the n-type contact is formed. The mask structure protects the optical absorption layer from doping by the first and second doping processes.

[0084] As another example, in some embodiments, method 1000 may include a step of forming a p-type contact in a first portion of the semiconductor layer disposed on a first side of the optical absorption layer by a first doping process. The optical absorption layer and a second portion of the semiconductor layer are protected from doping by the first doping process. The charging layer is formed in a first segment of the second portion of the semiconductor layer by a second doping process performed after the first doping process. Method 1000 may further include a step of forming an n-type contact in a second segment of the second portion of the semiconductor layer disposed on a second side of the optical absorption layer by a third doping process. The second side is opposite the first side.The optical absorption layer and the p-contact are protected from doping by the second doping process.In some embodiments, the method 1000 may further include the steps of: forming a mask structure over the optical absorption layer before forming the p-contact; forming a spacer layer after forming the charging layer, wherein the spacer layer is formed over the p-contact, over the mask structure, over the charging layer, and over the second portion of the semiconductor layer; converting the spacer layer into a first spacer and a second spacer arranged on opposite side surfaces of the mask structure; and forming another n-contact in a first portion of the charging layer by a fourth doping process, wherein a second portion of the charging layer directly adjacent to the optical absorption layer is protected by at least the second spacer before the fourth doping process.

[0085] As another example, in some embodiments, the method 1000 may include steps ofwhich are performed before the formation of the optical absorption layer. These steps may include a step of forming a p-contact in a first portion of the semiconductor layer by a first doping process. A second and a third portion of the semiconductor layer are protected from doping by the first doping process. The method 1000 may further include a step of forming an n-contact in the second portion of the semiconductor layer by a second doping process. The third portion of the semiconductor layer and the p-contact are protected from doping by the second doping process. The optical absorption layer and the charging layer are formed in the third portion of the semiconductor layer. In some embodiments, the method 1000 may further include the following steps: forming a mask structure over the optical absorption layer before the charging layer is formed,wherein the charging layer is formed by a third doping process that implants a p-type dopant into the third portion of the semiconductor layer that directly adjoins the optical absorption layer, and wherein the mask structure protects the optical absorption layer from implantation during the third doping process; forming a spacer layer after the third doping process, wherein the spacer layer is formed over the p-type contact, over the mask structure, over the charging layer, and over the n-type contact; converting the spacer layer into a first spacer and a second spacer that are arranged on opposite side surfaces of the mask structure; and forming another n-type contact in a first portion of the charging layer by a fourth doping process, wherein a second portion of the charging layer that directly adjoins the optical absorption layeris protected by at least the second spacer before the fourth doping process. For simplicity, these additional steps are not described in detail here.

[0086] Fig. 39 shows an integrated circuit fabrication system 1100 according to embodiments of the present disclosure. Fabrication system 1100 includes multiple units 1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, ..., N, connected by a communications network 1118. Network 1118 may be formed by a single network or multiple different networks, such as an intranet and the Internet, and may include both wired and wireless communications channels.

[0087] In one embodiment, entity 1102 represents a manufacturing collaboration service system; entity 1104 represents a user, such as a product engineer, who monitors the products in question; entity 1106 represents an engineer, such as a processing engineer, who controls the process and relevant recipes, or a plant engineer who monitors or adjusts the conditions and settings of the processing tools; entity 1108 represents a metrology tool for IC testing and measurements; entity 1110 represents a semiconductor processing tool, such as an EUV tool used to perform lithography processes; entity 1112 represents a virtual metrology module associated with processing tool 1110; entity 1114 represents an advanced processing control module associated with processing tool 1110 and additional processing tools.and entity 1116 represents a sample testing module associated with processing tool 1110;

[0088] Each entity may interact with other entities and provide for the fabrication of integrated circuits, processing control, and / or computational capabilities, and / or obtain such capabilities from the other entities. Each entity may also include one or more computer systems for performing computations and achieving automation. For example, the advanced processing control module of entity 1114 may include multiple computer hardware elements with software instructions encoded therein. The computer hardware elements may include hard disks, flash drives, CD-ROMs, RAM, display units (e.g., monitors), and input / output units (e.g., mouse and keyboard). The software instructions may be written in any suitable programming language and designed to perform specific tasks.

[0089] The integrated circuit fabrication system 1100 enables interaction between the entities for the purpose of integrated circuit fabrication (IC fabrication) as well as advanced processing control of the IC fabrication. In one embodiment, the advanced processing control includes adjusting the processing conditions, settings, and / or recipes of a processing tool used for the relevant wafers according to the measurement results.

[0090] In another embodiment, the measurement results are measured from a portion of the processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, the measurement results are measured at selected fields and points of the portion of the processed wafers according to an optimal sampling field / point determined based on various characteristics of process quality and / or product quality.

[0091] One of the capabilities provided by the IC fabrication system 1100 may enable collaboration and information access in areas such as design, engineering and processing, metrology, and advanced processing control. Another capability provided by the IC fabrication system 1100 may integrate systems between facilities, for example, between the metrology tool and the processing tool. Such integration allows the facilities to coordinate their processes. For example, integrating the metrology tool and the processing tool may enable manufacturing information to be more effectively integrated into the manufacturing process or an advanced processing control (APC) module may provide wafer data from online or local measurements, where the metrology tool is integrated with the corresponding processing tool.

[0092] The advanced lithography process, method, and materials described above can be used in many applications, such as applications where the transistors are implemented as fin-type field-effect transistors (FinFETs). For example, the fins can be patterned to create a relatively narrow spacing between elements, for which the above disclosure is well suited. Additionally, spacers used in forming FinFETs, also referred to as mandrels, can be processed according to the above disclosure. It is also understood that the transistors can also be implemented using multi-channel devices, such as gate-all-around (GAA) devices. To the extent that the present disclosure refers to a fin structure or FinFET devices, such descriptions may equally apply to GAA devices.

[0093] The present disclosure may offer advantages over conventional devices. However, it should be understood that not all advantages are described here, that other embodiments may offer other advantages, and that no particular advantage is required for any embodiment. One advantage is improved device performance. In particular, while other photonic devices rely on photolithography to define the location of the optical absorption layer and charging layer regions, the photonic device of the present disclosure utilizes self-alignment processes to define the location of the optical absorption layer and charging layer regions.Accordingly, the charging layer can be formed directly adjacent to the optical absorption layer, such that the charging layer forms a substantially vertically linear interface with the optical absorption layer and an underlying segment of undoped silicon. By directly adjoining the charging layer and the optical absorption layer, a buffer region is eliminated that is often present between the charging layer and the optical absorption layer in some other types of photonic devices. Since such a buffer region is not designed for light collection, it can represent wasted space in the photonic device, resulting in lower optical collection efficiency for these other types of photonic devices.In contrast, the photonic device of the present disclosure provides improved optical detection efficiency due at least in part to the elimination of the buffer region.

[0094] Furthermore, certain other types of photonic devices not fabricated according to the unique process flows of the present disclosure may have a nonlinear interface between the charging layer and the optical absorption layer and the undoped silicon segment below the optical absorption layer. For example, the charging layer and the optical absorption layer may form a first interface, and the charging layer and the undoped silicon segment may form a second interface, with the first interface and the second interface not aligned (e.g., having a different horizontal orientation). This may result in an undesirable electric field distribution within the photonic device, which may also negatively impact the performance of the photonic device.In comparison, as an inherent result of the unique self-aligned process flow implemented here, the charging layer can jointly define an interface with the optical absorption layer and the underlying undoped silicon segment, with the interface extending in a substantially vertical direction. This allows the electric field in the photonic device to achieve a desired distribution, which in turn improves the performance of the photonic device. Another advantage is that the location and / or size of the optical absorption layer and / or the charging layer can be flexibly adjusted (e.g., by configuring the thickness of the spacers or other masking layers), which is helpful in fine-tuning the electric field distribution in the photonic device.Another advantage is that the self-aligned processes can ensure that the optical absorption layer and the charging layer are formed in a more repeatable manner, so that their position and / or size do not vary significantly between devices, which is desirable, at least from a quality control perspective. Other advantages may include compatibility with existing manufacturing processes and simple and cost-effective implementation.

[0095] One aspect of the present disclosure relates to a photonic device. The photonic device comprises a substrate, a p-doped component disposed over the substrate, an n-doped component disposed over the substrate, an optical absorption layer disposed over the substrate, and a charging layer disposed over the substrate. The optical absorption layer is disposed between the p-doped component and the n-doped component. The optical absorption layer and the substrate have a different material composition. A charging layer is disposed between the p-doped component and the n-doped component. The charging layer has a first side surface that is substantially linear. The first side surface is in direct contact with the optical absorption layer.

[0096] Another aspect of the present disclosure relates to a structure. The structure includes a substrate and a p-contact disposed in a vertical direction above the substrate. The p-contact includes silicon. The structure further includes an n-contact disposed in the vertical direction above the substrate. The n-contact includes silicon. The structure further includes an optical absorption layer disposed in the vertical direction above the substrate and in a horizontal direction between the p-contact and the n-contact. The optical absorption layer includes germanium. The structure further includes a charging layer disposed in the vertical direction above the substrate and in the horizontal direction between the optical absorption layer and the n-contact. The charging layer includes silicon doped with a p-dopant.An interface between the optical absorption layer and the charging layer extends substantially in the vertical direction.

[0097] Another aspect of the present disclosure relates to a method. A semiconductor layer is formed over a substrate. An opening is etched into the semiconductor layer. An optical absorption layer is formed on a portion of the semiconductor layer exposed by the opening through a selective growth process. A charging layer is formed directly adjacent to the optical absorption layer. A passivation layer is formed over the optical absorption layer and the charging layer.

[0098] The foregoing describes features of various embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should recognize that they can readily use the present disclosure as a basis to design or modify other processes and structures to achieve the same objectives and / or realize the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 519 509

[0001]

Claims

[1] Photonic device comprising: a substrate; a p-doped component disposed above the substrate; an n-doped component disposed above the substrate; an optical absorption layer disposed above the substrate and between the p-doped component and the n-doped component, wherein the optical absorption layer and the substrate have a different material composition; and a charging layer disposed above the substrate and between the p-doped component and the n-doped component, the charging layer having a first side surface that is substantially linear, and the first side surface being in direct contact with the optical absorption layer. [2] A photonic device according to claim 1, wherein: the charging layer has a second side surface opposite to the first side surface; and the second side surface is essentially linear. [3] A photonic device according to claim 1 or 2, wherein: the charging layer is doped with a p-dopant; and a dopant concentration level of the charging layer is lower than a dopant concentration level of the p-doped component disposed above the substrate. [4] A photonic device according to any one of the preceding claims, further comprising a multiplication layer disposed between the charging layer and the n-doped component. [5] A photonic device according to any preceding claim, wherein the substrate comprises a silicon material composition and the optical absorption layer comprises a germanium material composition. [6] Photonic device according to one of the preceding claims, wherein: the p-doped component or the n-doped component has a recess, the recess having a lower surface directed vertically; and a lowermost surface of the optical absorption layer has a lower vertical height than the lower surface of the recess. [7] A photonic device according to any one of the preceding claims, further comprising a silicon component disposed beneath the optical absorption layer and between the p-doped component and the charging layer. [8] A photonic device according to claim 7, wherein the silicon component and the optical absorption layer have substantially coplanar side surfaces. [9] A photonic device according to any one of the preceding claims, further comprising one or more mask layers disposed over the optical absorption layer. [10] Photonic device according to one of the preceding claims, further comprising: a first dielectric spacer disposed above the p-doped component and on a first side surface of the optical absorption layer; and a second dielectric spacer disposed above the charging layer and on a second side surface of the optical absorption layer. [11] Structure comprising: a substrate; a p-contact disposed in a vertical direction above the substrate, the p-contact containing silicon; an n-contact disposed in the vertical direction above the substrate, the n-contact containing silicon; an optical absorption layer disposed in the vertical direction above the substrate and in a horizontal direction between the p-contact and the n-contact, the optical absorption layer containing germanium; and a charging layer disposed in the vertical direction above the substrate and in the horizontal direction between the optical absorption layer and the n-contact, wherein the charging layer contains silicon doped with a p-type dopant, and wherein an interface between the optical absorption layer and the charging layer extends substantially in the vertical direction. [12] The structure of claim 11, further comprising: a silicon layer disposed in the vertical direction above the optical absorption layer; a silicon oxide layer disposed in the vertical direction above the silicon layer; and a polysilicon layer arranged vertically above the silicon oxide layer. [13] The structure of claim 11 or 12, further comprising an undoped silicon component disposed in the vertical direction below the optical absorption layer, wherein the p-contact and the charging layer are in direct contact with opposite side surfaces of the undoped silicon component. [14] Method comprising: Forming a semiconductor layer over a substrate; Etching an opening in the semiconductor layer; Forming, using a selective growth method, an optical absorption layer on a portion of the semiconductor layer exposed through the opening; Forming a charging layer adjacent to the optical absorption layer, the charging layer forming a substantially straight interface with the optical absorption layer and a portion of the semiconductor layer; and Forming a passivation layer over the optical absorption layer and the charging layer. [15] The method of claim 14, further comprising: Forming, by a first doping process, a p-contact in a first portion of the semiconductor layer arranged on a first side of the optical absorption layer, wherein the optical absorption layer and a second portion of the semiconductor layer are protected from doping by the first doping process; and Forming, by a second doping process, an n-contact in a second portion of the semiconductor layer arranged on a second side of the optical absorption layer, the second side being opposite the first side, the optical absorption layer and the p-contact being protected from doping by the second doping process; wherein the charging layer is formed in a third portion of the semiconductor layer by a third doping process performed after the second doping process. [16] The method of claim 15, further comprising: forming a mask structure over the optical absorption layer before forming the p-contact or the n-contact, wherein the mask structure protects the optical absorption layer from doping by the first doping process and the second doping process. [17] A method according to any one of claims 14 to 16, further comprising: Forming, by a first doping process, a p-contact in a first portion of the semiconductor layer arranged on a first side of the optical absorption layer, wherein the optical absorption layer and a second portion of the semiconductor layer are protected from doping by the first doping process, wherein the charging layer is formed in a first segment of the second portion of the semiconductor layer by a second doping process performed after the first doping process; and Forming, by a third doping process, an n-contact in a second segment of the second portion of the semiconductor layer arranged on a second side of the optical absorption layer, the second side being opposite the first side, the optical absorption layer and the p-contact being protected from doping by the second doping process. [18] The method of claim 17, further comprising: Forming a mask structure over the optical absorption layer before forming the p-contact; Forming a spacer layer after the charging layer has been formed, wherein the spacer layer is formed over the p-contact, over the mask structure, over the charging layer, and over the second portion of the semiconductor layer; Converting the spacer layer into a first spacer and a second spacer arranged on opposite side surfaces of the mask structure; and Forming, by a fourth doping process, a further n-contact in a first portion of the charging layer, wherein a second portion of the charging layer, which directly adjoins the optical absorption layer, is protected by at least the second spacer from the fourth doping process. [19] A method according to any one of claims 14 to 18, further comprising, before the optical absorption layer has been formed: Forming, by a first doping process, a p-contact in a first portion of the semiconductor layer, wherein a second portion and a third portion of the semiconductor layer are protected from doping by the first doping process; and Forming, by a second doping process, an n-contact in the second portion of the semiconductor layer, wherein the third portion of the semiconductor layer and the p-contact are protected from doping by the second doping process; wherein the optical absorption layer and the charging layer are formed in the third portion of the semiconductor layer. [20] The method of claim 19, further comprising: Forming a mask structure over the optical absorption layer before forming the charging layer, wherein the charging layer is formed by a third doping process that implants a p-type dopant into the third portion of the semiconductor layer adjacent to the optical absorption layer, and wherein the mask structure protects the optical absorption layer from implantation during the third doping process; Forming a spacer layer after the third doping process, wherein the spacer layer is formed over the p-contact, over the mask structure, over the charging layer and over the n-contact; Converting the spacer layer into a first spacer and a second spacer arranged on opposite side surfaces of the mask structure; and Forming, by a fourth doping process, a further n-contact in a first portion of the charging layer, wherein a second portion of the charging layer adjacent to the optical absorption layer is protected by at least the second spacer from the fourth doping process.

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