Microstructured IC chip

Abstract

The invention relates to an IC chip with an IC substrate (100) with at least one IC functional layer (110) on the substrate, with an etch hole (130) which penetrates the IC functional layer from an outer surface (111) to the substrate. The core of the invention consists in the fact that a metallic seal (120) is arranged between an area of ​​the IC functional layer and the etched hole.

Description

State of the art

[0001] The invention relates to an IC chip comprising an IC substrate and at least one IC functional layer. The IC functional layer contains at least one etched hole of arbitrary geometry.

[0002] IC chips are typically composed of a sequence of different functional layers, such as silicon oxides or silicon nitrides. The choice of material and the method of fabrication of the IC functional layer, as well as the underlying material, influence the crystalline properties of the functional layer. Due to changes in the intrinsic lattice constant, the IC functional layer exhibits an altered crystal structure. These distortions are partially relaxed by lattice defects, but an intrinsic stress always remains in the layer. This intrinsic stress can also vary during the subsequent manufacturing process due to the influence of temperature or the deposition of additional functional layers. Subsequent large-area and uniform structuring of the IC functional layer can relax the layer's intrinsic stress.If the IC functional layer is locally structured, this structuring can act as a weak point or defect, causing the layer stress to dissipate uncontrollably. This can lead to defects, delaminations, and cracks, which can propagate into deeper layers and irreparably damage the component. Object of the invention

[0003] The object of the invention is to integrate a sealing and mechanically or crystallographically decoupling structure into IC functional layers in order to prevent the propagation of defects, delaminations or cracks in the vicinity of local structuring. Advantages of the invention

[0004] The invention relates to an IC chip comprising an IC substrate and at least one functional layer. The functional layer contains at least one etched hole of arbitrary geometry.

[0005] The core of the invention lies in the fact that the functional layer has a metal-filled structure which acts as a seal, in particular as a sealing ring, and protects local structures from the formation of defects, delaminations, and cracks. The metallic sealing ring can have additional functions and, for example, act as an electrical contact between the IC chip and the MEMS chip, which is connected to the IC chip via a bonding process, or as a particle barrier.

[0006] The core of the invention is a metallic sealing ring that acts as a vertical barrier against the propagation of layer stress-induced defects in IC functional layers. This makes it possible to create etch holes of any size, shape, and location. The metallic sealing ring can also incorporate additional functions such as an electrical contact or a particle barrier.

[0007] Advantageously, the invention allows defects, delaminations, and cracks originating from local structural features to be prevented or layer stress to be reduced by means of a metal-filled structure (metallic sealing ring). Should such defects arise in the structural feature, they can only propagate as far as this sealing ring, where they are prevented or reduced. The metallic sealing ring is particularly advantageous when the layer undergoes further manufacturing processes that induce layer stress again through temperature or additional functional layers.

[0008] An advantageous embodiment of the invention provides that the metallic sealing ring is located in the uppermost layer of the IC chip and is electrically connected to relevant electrical potentials of the IC chip. In this way, an electrical contact, for example for the ground potential of the IC chip, can be created on the surface.

[0009] An advantageous embodiment of the invention provides that the metallic sealing ring does not terminate flush with the IC functional layer, but has a raised topography.

[0010] When an IC chip is bonded to a MEMS chip with a cavity, the metallic sealing ring can be advantageously used to locally establish a defined distance between the surface of the MEMS chip and the surface of the metallic sealing ring. For example, this distance can be minimized to create areas within the cavity where gas exchange can occur, but no exchange of particles larger than the distance between the sealing ring and the surface of the MEMS chip. If the etched hole enclosed by the metallic sealing ring serves, for instance, as an access point for a trench running through the IC chip substrate, allowing gas access to the cavity, and is subsequently sealed using a laser melting process, the metallic sealing ring with its increased topography can additionally act as a constriction between the IC and MEMS chips.This allows gas exchange between the outer atmosphere and the cavern of the MEMS chip before the trench closes, and prevents particles from entering the MEMS chip beyond the etch hole through the metallic sealing ring.

[0011] Further advantageous embodiments of the invention can be found in the dependent claims. drawing The Fig. Figures 1 a and b schematically show an IC chip according to the invention in a first and a second embodiment with a metallic sealing ring surrounding an etched hole. The Fig. Figures 2 a and b schematically show an IC chip according to the invention in a third and fourth embodiment with a metallic sealing ring which contacts an underlying electrically conductive layer. Fig. Figure 3 schematically shows an IC chip according to the invention in a fifth embodiment with a metallic sealing ring with a collar. The Fig. Figures 4 a to d schematically show, in further embodiments, an IC chip according to the invention with a metallic sealing ring which completely or partially penetrates an IC functional layer system of several layers in different ways. Description

[0012] The Fig. Figures 1 a and b schematically show an IC chip according to the invention in a first and a second embodiment with a metallic sealing ring surrounding an etched hole.

[0013] Fig. Figure 1a schematically shows, in top view and section, the IC chip according to the invention in a first embodiment. The figure shows an IC chip with a substrate 100, with at least one IC functional layer 110, and a rectangular etched hole 130. The etched hole is directly surrounded by a portion of the IC functional layer and indirectly by a metallic sealing ring 120, which is also rectangular.

[0014] Fig. Figure 1b schematically shows, in top view and section, the IC chip according to the invention in a second embodiment. The figure shows an IC chip with a substrate 100, with at least one IC functional layer 110, and a rectangular etched hole 130. The etched hole is directly surrounded by a metallic sealing ring 120, which is also rectangular.

[0015] The IC chip, for example, is an application-specific integrated circuit (ASIC). The layer system of this integrated circuit, including metal layers, is not shown in detail here, but is summarized in the IC functional layer and the IC chip itself. The etched hole can have a rectangular or square outline, as shown here, but can also take on any other possible shape. The metallic sealing ring can completely or partially enclose the etched hole in any shape and, for example, be filled with aluminum.

[0016] The Fig. Figures 2 a and b schematically show an IC chip according to the invention in a third and fourth embodiment with a metallic sealing ring which contacts an underlying electrically conductive layer.

[0017] Fig. Figure 2a schematically shows, in top view and section, the IC chip according to the invention in a third embodiment. The figure shows an IC chip with a substrate 100, with at least one IC functional layer 110, and a rectangular etched hole 130. The etched hole is directly surrounded by a portion of the IC functional layer and indirectly by a metallic sealing ring 120, which is also rectangular. The metallic sealing ring is arranged in an outer IC functional layer. The sealing ring has an electrically conductive contact on its underside with an underlying electrically conductive layer 140. The conductive layer 140 can be electrically contacted from the outside via an outer contact surface 121 of the metallic sealing ring 120.

[0018] Fig. Figure 2b schematically shows, in top view and section, the IC chip according to the invention in a fourth embodiment. The etched hole 130 is directly surrounded by the metallic sealing ring 120. The metallic sealing ring 120, in turn, has an electrically conductive contact on its underside with the underlying electrically conductive layer 140.

[0019] Fig. Figure 3 schematically shows a fifth embodiment of an IC chip according to the invention, featuring a metallic sealing ring with a collar. The figure shows an IC chip with a substrate 100, at least one IC functional layer 110, and a rectangular etched hole 130. The etched hole 130 is directly surrounded by the metallic sealing ring 120. The metallic sealing ring 120 does not terminate flush with the uppermost IC functional layer 110 of the IC chip, but instead has a raised topography, a collar 122. When the IC chip is bonded to a MEMS chip 200, which has a cavity, the metallic sealing ring can be used to adjust the distance between the surface 201 of the MEMS chip 200 and the outer contact surface 121 on the upper side of the collar 122 of the metallic sealing ring 120.

[0020] For example, the distance can be minimized to create areas within the cavity where gas exchange can occur, but no exchange of particles larger than the distance between the sealing ring and the surface of the MEMS chip. If the etch hole enclosed by the metallic sealing ring serves, for instance, as an access point for a trench running through the IC chip substrate and subsequently used for a laser fusion seal, the metallic sealing ring with its raised topography can also function as a constriction within the MEMS chip. This allows gas exchange during the laser fusion seal between the external atmosphere and the MEMS chip cavity, while preventing the penetration of particles into the MEMS chip beyond the etch hole by the metallic sealing ring.

[0021] The Fig. Figures 4a to d schematically show, in further embodiments, an IC chip according to the invention with a metallic sealing ring which penetrates a multi-layer IC functional system completely or partially in different ways. Here, the IC chip has an IC functional system 150 consisting of several IC functional layers, and the metallic sealing ring 120 can penetrate one, several, or all functional layers.

[0022] Fig. Figure 4a schematically shows a sectional view of an IC chip according to the invention, comprising a substrate 100, an IC functional layer system 150 consisting of several IC functional layers, and an etch hole 130. The etch hole is directly surrounded by a portion of the IC functional layer system and indirectly by a metallic sealing ring 120. The metallic seal penetrates the entire IC functional layer system down to the substrate.

[0023] Fig. Figure 4b schematically shows a sectional view of an IC chip according to the invention, similar to the one in Fig. 4a, however, the metallic seal 120 only partially penetrates the IC layer system 150. The metallic sealing ring therefore does not extend to the substrate 100.

[0024] Fig. Figure 4c schematically shows a sectional view of an IC chip according to the invention, comprising a substrate 100, an IC functional layer system 150 consisting of several IC functional layers, and an etch hole 130. The etch hole is directly surrounded by a metallic sealing ring 120. The metallic seal extends through the entire IC functional layer system down to the substrate.

[0025] Fig. Figure 4d schematically shows a sectional view of an IC chip according to the invention, similar to that shown in Fig. 4c, however, the metallic seal 120 only partially delimits the IC layer system 150 and the etch hole 130. The metallic sealing ring therefore does not extend to the substrate 100, and a portion of the IC layer system borders directly on the etch hole.

[0026] Further designs can additionally include an increased topography of the metallic seal, for example in the form of a collar as in Fig. 3 shown, or also an electrically conductive contact, as in the Fig. 2 a and b shown, include. Reference symbol list 100 IC substrate 110 IC functional layer 111 Outside 120 metallic seals 121 outer contact surface of the metallic seal 122 collars 130 etching holes 140 electrically conductive layer 150 IC functional layer system of multiple layers 200 MEMS chips 201 Surface of the MEMS chip

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