Semiconductor Device and Method for Creating a Layout Plan for Semiconductor Devices

Abstract

One embodiment of the semiconductor device comprises a first circuit cell and a second circuit cell, the latter adjoining the first circuit cell at an intermediate cell boundary. The first circuit cell has one or more first conductive traces in a first metallization region of a first metallization layer and has one or more first vias beneath the first metallization layer. The second circuit cell has one or more second conductive traces in a second metallization region of the first metallization layer and has one or more second vias beneath the first metallization layer. The first metallization region and the second metallization region are spaced apart by a common space and extend along the cell boundary.The one or more first via structures and the one or more second via structures are located within an area with a zigzag structure along the cell boundary.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over preliminary US application No. 63 / 703,782, filed on October 4, 2024, which is incorporated by reference into the present application. BACKGROUND

[0002] An integrated circuit (IC) comprises one or more semiconductor devices. When designing a semiconductor device, designers can specify the sizes and shapes of various structural elements of the semiconductor device in the form of layout structures in a layout plan for the semiconductor device. The components and structures of the semiconductor structure are typically formed based on the creation and / or removal of features of different layers of semiconductor materials or structures, as specified by the layout structures in the layout plan. In some applications, a semiconductor device comprises a collection of modules that perform higher-level functions according to the design specifications of the semiconductor device. The modules often consist of a combination of circuit cells, each of which represents one or more semiconductor structures configured to perform a specific function.In some applications, a layout plan comprises layout cells corresponding to different circuit cells, each with pre-designed layout structures. These layout cells are sometimes referred to as standard cells. In many applications, templates of the standard cells are stored in standard cell libraries (hereafter referred to simply as "libraries" or "cell libraries") and are accessible through various tools, such as electronic design automation (EDA) tools, which can be used to create, optimize, and verify designs for semiconductor devices.

[0003] As semiconductor devices have become increasingly smaller and more complex, some structural elements within the same layer of semiconductor material or structure, constrained by the design rules of the relevant fabrication process, may be too close together to be fabricated simultaneously. Instead, structural elements that are too close according to the design rules can be fabricated using multiple structuring techniques with multiple masks. This approach involves increased costs for fabricating additional masks, increased costs for performing additional lithography, deposition, and / or removal processes, increased complexity in aligning different masks of the same layer, and / or reduced yield in the fabrication of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a block diagram of a semiconductor device in accordance with some embodiments. Fig. Figure 2 is a cross-sectional view of a semiconductor device in accordance with some embodiments. Fig. 3A-3E are layout diagrams of various exemplary layout cells in accordance with some embodiments. Fig. 4A-4B are layout diagrams of different sections of a first exemplary layout plan in accordance with some embodiments. Fig. 5A-5B are layout diagrams of different sections of a second exemplary layout plan in accordance with some embodiments. Fig. Figure 6 is a diagram of several placement sites of a layout plan for a semiconductor device in accordance with some embodiments. Fig. Figure 7A is a layout diagram of a section of an exemplary layout base cell in accordance with some embodiments. Fig. 7B-7I are layout diagrams of different sections of various example layout cells based on the layout base cell of Fig. 7A in accordance with some embodiments. Fig. Figures 8A-8C are simplified layout diagrams of various inverted variations of a layout candidate base cell in accordance with some embodiments. Fig. 9A-9B are simplified layout diagrams of exemplary layout plans in accordance with some embodiments. Fig. Figure 10A is a circuit diagram of an AND-OR-INVERT logic (AOI logic) in accordance with some embodiments. Fig. 10B-10D are layout diagrams of layout candidate cells of the AOI logic in Fig. 10A in accordance with some embodiments. Fig. Figure 11A is a circuit diagram of a NAND logic gate in accordance with some embodiments. Fig. 11B-11C are layout diagrams of layout candidate cells of the NAND logic in Fig. 11A in accordance with some embodiments. Fig. 12A-12B are diagrams of a simplified exemplary layout plan in accordance with some embodiments. Fig. Figure 13 is a flowchart of a procedure for creating a layout plan for a semiconductor device in accordance with some embodiments. Fig. Figure 14 is a flowchart of a procedure for creating a layout plan for a semiconductor device in accordance with some embodiments. Fig. Figure 15 is a block diagram of an Electronic Design Automation System (EDA system) in accordance with some embodiments. Fig. Figure 16 is a block diagram of an IC manufacturing system and an associated IC manufacturing process in accordance with some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, such that the first and second structural elements might not be in direct contact. Additionally, this disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves the purpose of simplification and clarity and does not itself imply any relationship between the different embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "underlying," "below," "under," "superior," "above," and the like may be used herein to facilitate description and to describe the relationship of one element or structural element to another element(s) or structural element(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Additionally, the term "made of" may mean either "having" or "consisting of."In this revelation, the phrase “one of A, B and C” means “A, B and / or C” (A, B, C, A and B, A and C, B and C, or A, B and C) and does not mean one element of A, one element of B and one element of C, unless otherwise described.

[0007] In some applications, a semiconductor device based on a back-side power delivery network (BSPDN) configuration features conductive power supply pathways on the rear side of the substrate, offering the advantage of wider power supply pathways and smaller cell sizes on the front side. However, in some applications, the reduced cell sizes (e.g., cell heights) can result in some circuit elements being too close together, making their fabrication practically impossible without employing a more complex lithographic process and / or introducing additional masks, leading to increased manufacturing costs and / or reduced yield.

[0008] In some embodiments according to the present application, restrictions and / or guidelines are applied such that the via structures adjacent to a cell boundary are confined within an area with a zigzag structure. Therefore, the via pitch of these structures is effectively increased without increasing the cell heights. In some embodiments, a semiconductor device and the corresponding layout plan based on one or more embodiments of the present disclosure would reduce or eliminate the need to employ a more complex lithographic process and / or introduce additional masks, resulting in reduced manufacturing costs and / or increased yield.

[0009] Fig. Figure 1 is a block diagram of a semiconductor device 100 in accordance with some embodiments of the present disclosure. In some embodiments, semiconductor device 100 corresponds to an IC device or a section of the IC device.

[0010] As in Fig. In embodiment 1, semiconductor device 100 comprises, among other things, at least one circuit macro 110. In some embodiments, circuit macro 110 corresponds to a set of semiconductor components configured as a memory, a control unit, one or more logic gates, or the like. Circuit macro 110 comprises, among other things, one or more circuit cells, such as circuit cell 112, circuit cell 114, and circuit cell 116. In some embodiments, each of circuit cells 112, 114, and 116 corresponds to one or more layout cells having layout patterns that specify transistors formed based on one or more active regions extending along a first direction (e.g., the X direction) and one or more gate structures extending along a second direction (e.g., the Y direction).In some embodiments, each of circuit cells 112, 114 and 116 (and the corresponding layout cells) has a corresponding cell height H1, H2 and H3 that can be measured along the second direction.

[0011] In some embodiments, each of the layout cells of circuit cells 112, 114, and 116 has layout patterns that specify respective conductive traces within one or more metallization layers and electrically connect different transistors of circuit cells 112, 114, and 116. In some embodiments, the semiconductor device 100 defines multiple busbar regions extending along the first direction, which are configured to carry a first supply voltage (e.g., VDD) or a second supply voltage (e.g., VSS or ground). In some embodiments, a circuit cell has a first side extending along one busbar region and a second side extending along another busbar region.In some embodiments, a circuit cell that has no other busbar region between the first and second sides is therefore sometimes referred to as having a standard cell height. In some embodiments, a standard-cell-height circuit cell has up to four or five metallization regions (other than the busbar regions) extending along the first direction in a bottom metallization layer (also called a Mo layer) across the transistors of the circuit cell for a more compact design based on some processing nodes. In some embodiments, each of cell heights H1, H2, and H3 has one standard cell height (e.g., a 1H cell), two standard cell heights (e.g., a 2H cell), or three standard cell heights (e.g., a 3H cell). In some embodiments, a circuit cell in circuit macro 110 corresponds to several standard cell heights or less than one standard cell height (e.g.,a 1 / 2H cell).

[0012] Fig. Figure 2 is a cross-sectional view of a semiconductor device (e.g., semiconductor device 100) in accordance with some embodiments. In some embodiments, the cross-sectional view is a simplified cross-sectional view, with many structural elements simplified or not shown.

[0013] Semiconductor device 100 in Fig. 2 features a substrate 210 with active regions 212 and gate structures 214 that are at least partially formed in substrate 210. In this example, semiconductor device 100 has metal-to-drain / source structures (MD structures 222) coupled to the active regions 212. In this example, semiconductor device 100 has via-to-drain / source structures (VD structures) coupled to MD structures 222 and via-to-gate structures (VG structures) coupled to gate structures 214 on a VD / VG layer above substrate 210 (with respect to a direction Z). In some embodiments, semiconductor device 100 further has multiple metallization layers (e.g., M0, M1, M2, ..., Mn-1 and Mn layers) and multiple via layers (e.g., V0, V1, V2, ..., Vn-2 and Vn-1 layers) above the VD / VG layer and the substrate 210 (where n is a positive (Integer is).In some embodiments, the number of metallization layers over substrate 210 ranges from 8 to 14. In some embodiments, Vn-1 layer refers to the via structures that lie between and connect conductive traces in Mn-1 layer and Mn layer. In some embodiments, Mo layer refers to the first metallization layer over substrate 210. In some embodiments, the multiple metallization layers and the multiple via layers comprise a conductive material containing copper, aluminum, gold, tungsten, a combination thereof, or the like.

[0014] Semiconductor device 100 in Fig. Figure 2 further includes, as a non-restrictive example, conductive structures arranged beneath substrate 210. For example, semiconductor device 100 further includes backside metallization layers BMo and BM1 and backside via layers BVD and BV0. In this example, BVD layer denotes backside via structures that lie between and connect active regions 212 and backside conductive traces in the BMo layer; and BV0 layer denotes backside via structures that lie between and connect backside conductive traces in the BMo layer and the BM1 layer. In some embodiments, BMo layer denotes the first metallization layer beneath substrate 210. In this example, there are two backside metallization layers and corresponding via layers.In some embodiments, the number of backside metallization layers beneath substrate 210 ranges from 2 to 6. In some embodiments, a portion or all of the backside conductive structures (e.g., backside metallization layers BMo and BM1 and backside via layers BVD and BVo) are at least partially embedded in substrate 210. In some embodiments, backside metallization layers BMo and BM1 and backside via layers BVD and BVo contain a conductive material that includes copper, aluminum, gold, tungsten, a combination thereof, or the like. In some other embodiments, a semiconductor device has no backside conductive structures.

[0015] In some embodiments, semiconductor device 100 has one or more redistribution layers and conductive pad structures (not shown in Fig. 2) above one or more redistribution layers. In some embodiments, semiconductor device 100 further comprises conductive connection structures (e.g., conductive bumps, copper pillar bumps, solder medium bumps, or the like, not in Fig. 2) over the conductive pad structures. In some embodiments, semiconductor device 100 also has one or more rear-side redistribution layers and rear-side conductive pad structures (not in Fig. 2) under one or more rear-side redistribution layers. In some embodiments, semiconductor device 100 also has rear-side conductive termination structures (e.g., conductive bumps, copper pillar bumps, solder medium bumps, or the like, not in Fig. 2) under the rear conductive pad structures.

[0016] Fig. Figure 3A is a layout diagram of a first exemplary layout cell 300A in accordance with some embodiments. Fig. 3A shows only a section of the first layout cell 300A as a non-restrictive example. Fig. 3A corresponds to the first layout cell 300A of a first circuit cell and has a cell boundary 302. The first layout cell 300A has metallization regions 312, 314, 322, 324, 326 and 328, which extend along a first direction (e.g. the X direction) and one next to the other along a second direction (e.g. the Y direction) in a bottom metallization layer (e.g. the Mo layer in Fig. 2) are arranged over a substrate (also referred to as a front face of a resulting semiconductor device).

[0017] In some embodiments, layout patterns in metallization regions 312 and 314 specify conductive traces for carrying power supply voltages (e.g., VDD, VSS, or ground). In some embodiments, layout patterns in metallization regions 322, 324, 326, and 328 specify conductive traces for connecting various elements of the first circuit cell. In some embodiments, a power grid based on the fact that it has metallization regions 312 and 314 for power supply at the Mo layer is also referred to as a front-side power grid configuration (FSPDN configuration). Fig. 3A has the first layout cell 300A a first standard cell height Ha along the second direction to accommodate metallization areas 312, 314, 322, 324, 326 and 328.

[0018] Fig. Figure 3B is a layout diagram of a second exemplary layout cell 300B in accordance with some embodiments. Fig. 3B shows only a section of a second layout cell 300B as a non-restrictive example. In Fig. 3B corresponds to the second layout cell 300B of a second circuit cell and has a cell boundary 306. The second layout cell 300A has metallization regions 332, 334, 342, 344, 346, and 348 extending along a first direction (e.g., the X direction). Metallization regions 342, 344, 346, and 348 are adjacent to each other along a second direction (e.g., the Y direction) in a bottom metallization layer (e.g., the Mo layer in Fig. 2) arranged over a substrate (also referred to as a front face of a resulting semiconductor device). In addition, metallization regions 332 and 334 are located in a metallization layer (e.g., the BMo layer in Fig. 2) arranged beneath the substrate (also referred to as a back side of the resulting semiconductor device). In some embodiments, metallization regions 342, 344, 346, and 348 have a conduction width and conduction pitch along the second direction that correspond to those of metallization regions 322, 324, 326, and 328 in Fig. 3A are comparable to or equal to these.

[0019] In some embodiments, layout patterns in metallization regions 332 and 334 specify conductive traces for carrying power supply voltages (e.g., VDD, VSS, or ground). In some embodiments, layout patterns in metallization regions 342, 344, 346, and 348 specify conductive traces for connecting various elements of the second circuit cell. In some embodiments, a power grid based on the fact that it has metallization regions 332 and 334 for power supply at the BMo layer is also referred to as a backside power grid configuration (BSPDN configuration). Fig. The second layout cell 300B has a second standard cell height Hb along the second direction to accommodate metallization regions 342, 344, 346, and 348. Compared to the first layout cell 300A, which has metallization regions 312 and 314 for power supply on the front, the second standard cell height Hb is smaller than the first standard cell height Ha when the metallization regions 332 and 334 for power supply are on the rear. Therefore, a standard cell based on the BSPDN configuration has a smaller cell height and wider rear metallization regions than its counterpart based on the FSPDN configuration.

[0020] Fig. 3C is a layout diagram of a third exemplary layout cell 300C in accordance with some embodiments. Fig. 3C shows only a section of the third layout cell 300C as a non-restrictive example. In Fig. 3C corresponds to the third layout cell 300C, a third circuit cell based on the BSPDN configuration, and the metallization areas on the back for power supply are in Fig. 3C not shown. Fig. Third layout cell 300C has a cell boundary 352 and four metallization regions 354 extending along a first direction (e.g., the X direction) in a bottom metallization layer (e.g., Mo layer). In some embodiments, the third layout cell 300C is also referred to as a layout cell of 4 M0. Furthermore, the third layout cell 300C has gate patterns 356, which specify gate structures within a cell boundary 352, and dummy gate patterns 358, which specify dummy gate structures on the left segment and the right segment (opposite sides with respect to the X direction) of cell boundary 352.

[0021] In Fig. 3C does not overlap any of the metallization regions 354, the upper segment, and the lower segment (opposite sides with respect to the Y direction) of cell boundary 352. As such, the upper side of third layout cell 300C is suitable to abut another layout cell that does not have a metallization region in its lowest metallization layer (e.g., Mo layer) that overlaps the lower segment of the cell boundary of such another layout cell, thus defining a common space along the upper segment of cell boundary 352. Likewise, the lower side of third layout cell 300C is suitable to abut another layout cell that does not have a metallization region in its lowest metallization layer (e.g., Mo layer) that overlaps the upper segment of the cell boundary of such layout cell, thus defining a common space along the lower segment of cell boundary 352.

[0022] Fig. 3D is a layout diagram of a fourth exemplary layout cell 300D in accordance with some embodiments. Fig. 3D shows only a section of the fourth layout cell 300D as a non-restrictive example. Fig. 3D corresponds to the fourth layout cell 300D, a fourth circuit cell based on the BSPDN configuration, and the metallization areas on the back for power supply are in Fig. 3D not shown. Fig. In 3D, the fourth layout cell 300D has a cell boundary 362 and five metallization regions 364 extending along a first direction (e.g., the X direction) in a bottom metallization layer (e.g., Mo layer). In some embodiments, the fourth layout cell 300D is also referred to as a layout cell of 5 M0. Furthermore, the fourth layout cell 300D has gate patterns 366, which specify gate structures within cell boundary 362, and dummy gate patterns 368, which specify dummy gate structures on the left segment and the right segment (opposite sides with respect to the X direction) of cell boundary 362.

[0023] In Fig. 3D, similar to the example in Fig. 3C, no metallization area 364 overlaps the upper and lower segments (opposite sides with respect to the Y direction) of cell boundary 362. As such, the upper side of the fourth layout cell 300D is suitable to abut another layout cell and define a common space along the upper segment of cell boundary 362. Likewise, the lower side of the fourth layout cell 300D is suitable to abut another layout cell and define a common space along the lower segment of cell boundary 362.

[0024] Fig. 3E is a layout diagram of a fifth exemplary layout cell 300E in accordance with some embodiments. Fig. 3E shows only a section of the fifth layout cell 300E as a non-restrictive example. In Fig. 3E corresponds to the fifth layout cell 300E, a fifth circuit cell based on the BSPDN configuration, and the metallization areas on the back for power supply are in Fig. 3E not shown. Fig. The fifth layout cell 300E has a cell boundary 372, four metallization regions 374 extending along a first direction (e.g., the X direction) in a bottom metallization layer (e.g., Mo layer) within cell boundary 372, and a metallization region 375 in the bottom metallization layer extending along a lower segment of cell boundary 372. In some embodiments, the fifth layout cell 300E is also referred to as a layout cell of 4.5 M0. Furthermore, the fifth layout cell 300E has gate patterns 376 specifying gate structures within cell boundary 372, and dummy gate patterns 378 specifying dummy gate structures on the left and right segments (opposite sides with respect to the X direction) of cell boundary 372.

[0025] In Fig. Metallization region 374 does not overlap the upper segment of cell boundary 372. As such, the upper side of fifth layout cell 300E is suitable to abut another layout cell and define a common space along the upper segment of cell boundary 372. However, metallization region 375 overlaps the lower segment of cell boundary 372. As such, the lower side of fifth layout cell 300E is suitable to abut another layout cell that has a metallization region overlapping an upper segment of the cell boundary of such another layout cell, thus defining a common metallization region along the lower segment of cell boundary 372.

[0026] Fig. 4A and Fig. Figure 4B shows layout diagrams of various sections of a first exemplary layout plan 400 in accordance with some embodiments. Layout structures in Fig. 4A and Fig. 4B represents only a section of the first layout plan 400 as non-restrictive examples. Other layout cells and layout structures of the first layout plan 400 are in Fig. 4A and Fig. 4B omitted.

[0027] Fig. 4A contains legends of different types of layout structures, which are in Fig. 4A and Fig. 4B can be used. In Fig. 4A and Fig. 4B The layout structures include layout structures for polysilicon gate patterns (PO structures) that specify polysilicon gate structures. In some embodiments, the polysilicon gate structures are used as functional gate structures, dummy gate structures, or placeholder structures on which functional and dummy structures are formed. In this non-restrictive example, the PO patterns are spaced apart from each other by one contacted poly pitch (1 CPP, also known as gate pitch) along a first direction (e.g., the X-direction).

[0028] In Fig. 4A and Fig. 4B shows the following layout structures: Mo layout structures for conductive traces on a bottommost metallization layer (e.g., Mo layer) above the gate structures; M1 layout structures for conductive traces on a different metallization layer above the bottommost metallization layer (e.g., M1 layer); VD layout structures for via structures connecting drain / source connections to corresponding conductive traces on the Mo layer; VG layout structures for via structures connecting gate structures to corresponding conductive traces on the Mo layer; and Vo layout structures for via structures connecting conductive traces on the Mo layer and corresponding conductive traces on the M1 layer. The legends in Fig. 4A further specifies a CMD layout structure, indicating the removal of materials to define drain / source connections, and a CPO layout structure, indicating the removal of materials to define gate structures, which are in Fig. 4B can be used.

[0029] In Fig. In diagrams 4A-4B, the first layout plan 400 features three layout cells 410, 420, and 430 stacked on top of each other in a second direction (e.g., the Y direction). Each of layout cells 410, 420, and 430 is based on the BSPDN configuration, which has conductive traces on a rear side of the resulting semiconductor device for power supply and conductive traces on the Mo layer (specified by Mo layout structures) on a front side of the resulting semiconductor device within four conductive regions extending along the first direction (e.g., the X direction).

[0030] In Fig. Layout cell 410 is connected to layout cell 420. Layout cell 410 has a conductive conductor structure 412, which specifies a conductive conductor in a metallization region of the Mo layer, and has via patterns (e.g., via pattern 414) that specify via structures below the Mo layer and are configured to connect corresponding drain / source terminals to the conductive conductor specified by conductive conductor structure 412. Layout cell 420 has a conductive conductor structure 422, which specifies a conductive conductor in a metallization region of the Mo layer, and has via structures (e.g., via structure 424) that specify via structures below the Mo layer and are configured to connect corresponding drain / source terminals to the conductive conductor specified by conductive conductor structure 422.In some embodiments, conductive conductor structure 412 and conductive conductor structure 422 are arranged along the second direction based on a metallization pitch (Mo-pitch).

[0031] In Fig. Layout cell 420 is connected to layout cell 430. Layout cell 420 has a conductive conductor structure 425, which specifies a conductive conductor in a different metallization region of the Mo layer; a conductive conductor structure 426, which specifies a conductive conductor in a metallization region of the M1 layer; a via pattern 427, which specifies a via structure between the conductive conductor specified by conductive conductor structure 425 at a corresponding PO pattern; and a via pattern 428, which specifies a via structure between the conductive conductor specified by conductive conductor structure 425 at the Mo layer and the conductive conductor specified by conductive conductor structure 426 at the M1 layer.

[0032] Layout cell 430 has a conductive conductor structure 432, which specifies a conductive conductor in another metallization region of Mo layer, a conductive conductor structure 434, which specifies a conductive conductor in another metallization region of M1 layer, a via pattern 436, which specifies a via structure between the conductive conductor specified by conductive conductor structure 432 at a corresponding PO pattern, and a via pattern 438, which specifies a via structure between the conductive conductor specified by conductive conductor structure 432 at Mo layer and the conductive conductor specified by conductive conductor structure 424 at M1 layer.In some embodiments, conductive conductor structure 425 and conductive conductor structure 432 are arranged based on the same metallization pitch as Mo-pitch between conductive conductor structure 412 and conductive conductor structure 422.

[0033] In this non-restrictive example, via patterns 414 and 424 are opposite each other across a cell boundary between layout cells 410 and 420, are aligned with each other in the second direction (e.g., the Y-direction), and are arranged based on a via pitch (designated and labeled as "VD-Pitch"). In this non-restrictive example, via patterns 427 and 436 are opposite each other across the cell boundary, are aligned with each other in the second direction, and are arranged based on a via pitch (designated and labeled as "VG-Pitch").In this non-restrictive example, via patterns 428 and 434 are located opposite each other across the cell boundary, are aligned with each other in the second direction, and are arranged based on a via pitch (designated and labeled as "Vo-Pitch"). Conductive conductor structure 426 and conductive conductor structure 434 are also separated by an end-to-end gap (designated and labeled as "M1 EtE").

[0034] In the non-restrictive example in Fig. In 4A, based on the BSPDN configuration, there are no metallization areas for power supply at the Mo layer between layout cell 410 and layout cell 420, and between layout cell 420 and layout cell 430. As such, the cell height and / or cell placement density in the second direction (e.g., the Y-direction) is limited by the manufacturing process capacity with respect to the minimum sizes of VD pitch, VG pitch, Vo pitch, and M1 EtE. In this example, the via pitch (VD pitch, VG pitch, or Vo pitch) is equal to the metallization pitch (Mo pitch). In some embodiments, to reduce cell heights, the minimum sizes of VD pitch, VG pitch, Vo pitch, and M1 EtE would be so small (e.g.,smaller than 20 nanometers (nm), that the corresponding structures can be achieved by applying a more complicated lithographic process and / or introducing additional masks, which corresponds to increased manufacturing costs and / or reduced yield.

[0035] In Fig. In 4B, the first layout plan 400 has a CMD structure 442, which is shared by layout cell 410 and layout cell 420, and which specifies the removal of materials to define drain / source connections. Fig. 4B's first layout plan 400 further includes a CPO structure 446, shared by layout cell 420 and layout cell 430, which specifies the removal of materials to define gate structures. In the non-restrictive example in Fig. 4B, based on the BSPDN configuration, the cell height and / or the placement density of cells in the second direction are also limited by the capacity of the removal process with respect to the minimum sizes of the CMD structure width (e.g. width Wcmd) and the CMO structure width (e.g. width Wcpo).

[0036] Fig. 5A-5B are layout diagrams of various sections of a second exemplary layout plan 500 in accordance with some embodiments. Layout structures in Fig. 5A and Fig. 5B represents only one section of the second layout plan 500 as non-restrictive examples. Other layout cells and layout structures of the second layout plan 500 are in Fig. 5A and Fig. 5B omitted. Fig. 5A contains legends of different types of layout structures, which are in Fig. 5A and Fig. 5B are used, which are the same as the legends that are in Fig. 4A are presented, and therefore a detailed description is omitted.

[0037] In Fig. 5A and Fig. In 5B, the second layout plan 500 has three layout cells 510, 520, and 530 stacked on top of each other in a second direction (e.g., the Y direction). In some embodiments, layout cells 510, 520, and 530 correspond to layout cells 410, 420, and 430 in Fig. 4A and Fig. 4B. In this non-restrictive example, layout cell 520 is, compared to the first layout plan 400 in Fig. 4A and Fig. 4B, shifted by 1 CPP in the first direction (e.g. the X direction).

[0038] In Fig. Layout cell 510 and layout cell 520 in 5A have VD structures adjacent to the cell boundary between layout cell 510 and layout cell 520. Since layout cell 520 is offset by 1 CPP relative to layout cell 510, the VD structures adjacent to the cell boundary are located within a first area 542 with a first zigzag structure along the cell boundary. Compared to the first layout plan 400, the VD structures adjacent to the cell boundary have a through-hole pitch (labeled 'VD pitch') that is larger than the metallization pitch (Mo pitch) between two Mo structures adjacent to the cell boundary. In this example, the through-hole pitch (VD-Pitch') is the square root of the sum of (i) the square of the metallization pitch (Mo-Pitch) and (ii) the square of 1 CPP.

[0039] In Fig. Layout cell 520 and layout cell 530 exhibit VG structures adjacent to the cell boundary between layout cell 520 and layout cell 530, and V1 structures adjacent to the cell boundary between layout cell 520 and layout cell 530. Because layout cell 520 is shifted by 1 CPP relative to layout cell 530, the VG structures adjacent to the cell boundary are located within a second area 546 with a second zigzag structure along the cell boundary. Compared to the first layout plan 400, the VG structures adjacent to the cell boundary have a via pitch (labeled 'VG pitch') that is larger than a metallization pitch (Mo pitch). In this example, the through-hole pitch (VG-pitch') is the square root of the sum (i) of the square of the metallization pitch (Mo-pitch) and (ii) of the square of 1 CPP.Similarly, the Vo structures adjacent to the cell boundary have a via pitch (labeled Vo-pitch') that is larger than the metallization pitch (Mo-pitch). In some embodiments, VD-pitch', VG-pitch', and / or Vo-pitch' are one of at least twice the metallization pitch (e.g., Mo-pitch) or at least the gate pitch (e.g., 1 CPP). In some embodiments, M1 structures in Layout Plan 500, oriented along the second direction, are spaced by an end-to-end distance (labeled M1 EtE') that is larger than M1 EtE in [reference missing]. Fig. 4A. In some embodiments, the end-to-end distance (M1 EtE') is also larger than the metallization pitch (Mo-pitch).

[0040] In the non-restrictive example in Fig. Based on the BSPDN configuration, there are no metallization regions for power supply at the Mo layer between layout cell 510 and layout cell 520, and between layout cell 520 and layout cell 530. Based on an arrangement of the VD and / or VG structures along a cell boundary within an area of ​​a zigzag structure, the via pitch of the VD and / or VG structures (VD-Pitch' and VG-Pitch') as well as Vo-Pitch' and / or M1 EtE' are determined according to the example in [reference missing]. Fig. 5A compared to the example in Fig. 4A enlarged. In some embodiments, the enlarged sizes of VD-Pitch', VG-Pitch', Vo-Pitch' and / or M1 EtE' would reduce or eliminate the need to employ a more complicated lithographic process and / or introduce additional masks to achieve the same cell height, resulting in reduced manufacturing costs and / or increased yield compared to the example in Fig. 4A corresponds to this.

[0041] In Fig. In 5B, the second layout plan 500 has a CMD structure 552, which is shared by layout cell 510 and layout cell 520, and which specifies the removal of materials for defining drain / source connections. Fig. In 5B, the second layout plan 500 further features a CPO structure 556, shared by layout cell 520 and layout cell 530, which specifies the removal of materials to define gate structures. By moving VD structures and VG structures as in Fig. In 5A, the widths of CMD structure 552 and CPO structure 556 (Wcmd' and Wcpo') are increased at various sections along the corresponding cell boundaries without affecting the functionality of the corresponding drain / source connections and gate structures. The resulting CMD structure 552 and CPO structure 556 have corresponding zigzag structures along the respective cell boundaries. In the non-restrictive example in Fig. 5B, based on the BSPDN configuration, is the limitation of the cell height and / or the placement density of cells compared to the example in Fig. 4A and Fig. 4B is based on the increased size of the CMD feature width (e.g., width Wcmd') and the CMO feature width (e.g., width Wcpo'). In some embodiments, the CMD feature width (e.g., width Wcmd') and the CMO feature width (e.g., width Wcpo') are larger than the metallization pitch (e.g., Mo pitch) and are the same or within 10% variation.

[0042] Layout plan 500 in Fig. 5A and Fig. Figure 5B illustrates this as a non-restrictive example. In some embodiments, the VD structures and / or the VG structures of adjacent layout cells are placed within corresponding areas of zigzag structure with or without misaligned layout cells, depending on how the layout cells are created as standard cells in the cell library and how the placement sites for placing the layout cells are arranged.

[0043] Therefore, according to one or more embodiments of the present disclosure, a semiconductor device manufactured based on the BSPDN configuration, considering the example of Fig. 5A and Fig. 5B comprises a first circuit cell and a second circuit cell adjacent to the first circuit cell. In some embodiments, the first circuit cell has one or more first conductive conductors in a first metallization conduction region of a first metallization layer. (e.g., Mo layer) and has one or more first via structures below the first metallization layer. In some embodiments, the second circuit cell has one or more second conductive traces in a second metallization conduction region of the first metallization layer (e.g., Mo layer) and has one or more second via structures below the first metallization layer. In some embodiments, the first metallization conduction region and the second metallization conduction region are located along the cell boundary. In some embodiments, based on the fact that the one or more first via structures are located between the first metallization layer and one or more first conductive drain / source structures of the first circuit cell (i.e.,In embodiments based on the first through-hole structures of the VD layer being located between the first metallization layer and one or more second conductive drain / source structures of the second circuit cell (i.e., through-hole structures of the VD layer), the one or more first through-hole structures and the one or more second through-hole structures are located within a first surface (e.g., as specified by first surface 542), with a first zigzag structure along the cell boundary. In some embodiments, based on the one or more first through-hole structures being located in gate structures of the first circuit cell (i.e.,via-hole structures of the VG layer) are located, and that the one or more second via-hole structures are located between the first metallization layer and one or more second gate structures of the second circuit cell (i.e. via-hole structures of the VG layer), the one or more first via-hole structures and the one or more second via-hole structures are located within a second surface (e.g. as specified by second surface 546), with a second zigzag structure along the cell boundary.

[0044] In some embodiments, the cell boundary extends along a first direction (e.g., the X-direction), and the first metallization conduction region and the second metallization conduction region are arranged along a second direction (e.g., the Y-direction) based on a metallization pitch (e.g., Mo-pitch), which differs from the first direction. In some embodiments, the one or more first via structures are located between the first metallization layer and the one or more first conductive drain / source structures of the first circuit cell (i.e., via structures of the VD layer), and the one or more second via structures are located between the first metallization layer and the one or more second conductive drain / source structures of the second circuit cell (i.e.,In embodiments where the via structures of the VD layer are located, the one or more first via structures and the one or more second via structures are arranged based on a first minimum via pitch (e.g., VD pitch') that is larger than the metallization pitch (e.g., Mo pitch). In some embodiments, the one or more first via structures are located between the first metallization layer and the one or more first gate structures of the first circuit cell (i.e., via structures of the VG layer), and the one or more second via structures are located between the first metallization layer and the one or more second gate structures of the second circuit cell (i.e.,The first or second via structures (of the VG layer) are arranged based on a second minimum via pitch (e.g., VG pitch') that is larger than the metallization pitch (e.g., Mo pitch).

[0045] In some embodiments, the first circuit cell further comprises one or more third via structures (i.e., Vo-layer via structures) between the first metallization conduction region and a third metallization conduction region of a second metallization layer above the first metallization layer, and the second circuit cell further comprises one or more fourth via structures (i.e., Vo-layer via structures) between the second metallization conduction region and a fourth metallization conduction region of the second metallization layer. In some embodiments, the one or more third via structures are spaced from the one or more fourth via structures based on at least one third minimum via pitch (e.g., Vo-pitch') that is larger than the metallization pitch (e.g., Mo-pitch').

[0046] In some embodiments, the first circuit cell further comprises a third conductive line of the second metallization layer (e.g., M1 layer), the second circuit cell further comprises a fourth conductive line of the second metallization layer, and the third and fourth conductive lines are aligned along the second direction (e.g., the Y direction). In some embodiments, the third and fourth conductive lines are arranged based on a minimum end-to-end distance (e.g., M1 EtE') that runs along the second direction and is greater than the metallization pitch (e.g., Mo pitch).

[0047] In some embodiments, the one or more first conductive drain / source structures and the one or more second conductive drain / source structures are spaced apart based on a CMD structure (e.g., CMD structure 552) that has a third zigzag structure along the cell boundary. In some embodiments, the one or more first gate structures and the one or more second gate structures are spaced apart based on a CPO structure (e.g., PO structure 556) that has a fourth zigzag structure along the cell boundary.

[0048] Fig. Figure 6 is a diagram of several placement sites 600 of a layout plan for a semiconductor device in accordance with some embodiments. In Fig. 6, each rectangular box bearing the number 1, 2, vertically inverted 1, or vertically inverted 2, represents a placement location of the corresponding placement types. In some embodiments, each of the multiple placement locations of the layout plan has a width along a first direction (e.g., the X-direction) corresponding to a gate pitch (e.g., 1 CPP) of the layout plan and a height along a second direction (e.g., the Y-direction) corresponding to a standard cell height (e.g., 1 H) of the layout plan.

[0049] In Fig. The multiple placement locations have 600 rows of placement locations, such as rows 612, 614, 615, 616, and 617. In this example, rows 612, 614, and 616 have placement locations of a first placement type (labeled with the number 1) and placement locations of a second placement type (labeled with the number 2), arranged alternately along the first direction (e.g., the X direction). These are useful for placing a standard layout cell of the standard cell height in a desired shape (e.g., the orientation stored in a cell library). Rows 615 and 617 also have placement locations of an inverted first placement type (labeled with an inverted 1) and placement locations of an inverted second placement type (labeled with an inverted 2), arranged alternately along the first direction (e.g., the X direction).are arranged in the X direction) and are useful for placing the standard layout cell in an inverted shape that corresponds to a reflection of the desired shape around an axis along the first direction.

[0050] In this example, the placement positions of the first placement type (labeled with the number 1) in one row are located at the placement positions of the inverted second placement type (labeled with an inverted 2) in an adjacent row; and the placement positions of the second placement type (labeled with the number 2) in one row are located at the placement positions of the inverted first placement type (labeled with an inverted 1) in an adjacent row. As such, the multiple placement positions 600 have a first placement type / inverted first placement type and a second placement type / inverted second placement type arranged in a checkerboard pattern.

[0051] In some embodiments, the first placement type specifies the inclusion of a via structure (e.g., VD structure or VG structure) beneath the first metallization layer of the layout plan, adjacent to a reversed second directional side (e.g., also known as the left side in Fig. 6) is arranged at a corresponding placement location. In some embodiments, the second placement type indicates preventing a through-hole structure (e.g., VD structure or VG structure) beneath the first metallization layer of the layout plan, adjacent to the reversed second directional side (e.g., also known as the left side in Fig. 6 specified and shown) is arranged at the corresponding placement location. In the non-restrictive example in Fig. The first placement type and the second placement type are defined based on VD structures.

[0052] In Fig. 6 is used to place a target layout cell 620, which has a cell height of 1 H and a cell width of 5 CPP. A set of placement sites 630, comprising five consecutive placement sites in the same row (e.g., row 614), is identified for placing target layout cell 620. For example, target layout cell 620 has VD structures 622, 624, and 626 at its base in the first, third, and fifth regions, defined by gate structures, and is therefore set up to be placed at five consecutive placement sites with placement type markers [1, 2, 1, 2, 1].

[0053] In some embodiments, each circuit cell has several layout candidate cells associated with it for placement, wherein the leftmost edge location is the first placement type, the reverse of the first placement type, the second placement type, and the reverse of the second placement. In some embodiments, one of the several layout candidate cells associated with the circuit cell is selected as the target layout cell at the set of placement locations based on a placement location type of an edge placement location of the set of placement locations in a reverse first direction (e.g., the leftmost edge location). For example, the target layout cell 620 can be determined based on the leftmost edge placement location of the set of placement locations of the first placement type (labeled with the number 1).Based on the checkerboard arrangement of the multiple placement locations and the pre-designed layout candidate cells, the placement constraints or guidelines are based on zigzag structures for various structural elements, as in . Fig. 5A and Fig. 5B illustrates how it can be integrated into an Electronic Design Automation Tool (EDA Tool) for efficient and / or automated cell placement.

[0054] Fig. 7A-12E correspond to non-restrictive examples of layout candidate cells for various circuit cells. TEs provides one or more other approaches to constructing the layout candidate cells, which, in conjunction with the checkerboard arrangement of the multiple placement sites in Fig. 6 are to be used to understand the restrictions and guidelines in Fig. 5A and Fig. 5B to fulfill. Fig. 7A-7I, 10B-10D and 11B-11C contain legends for various types of layout structures, which are the same as the legends found in Fig. 4A will be presented, and therefore a detailed description is omitted.

[0055] Fig. Figure 7A is a layout diagram of a section of an exemplary layout base cell 700A in accordance with some embodiments. Fig. Layout base cell 700A features PO structures and Mo areas for conductive trace structures at layer M0, as indicated by the legends. In this non-restrictive example, layout base cell 700A has a cell width along a first direction (e.g., the X direction) of 5 CPP and a cell height along a second direction (e.g., the Y direction) of 1 H, where CPP corresponds to a gate pitch and H corresponds to a standard cell height, as illustrated above. In this non-restrictive example, layout base cell 700A occupies five layout areas 701, 702, 703, 704, and 705, defined by adjacent PO structures, where each of the layout areas has a height of 1 H and a width of 1 CPP and a placement location in Fig. 6 corresponds.

[0056] Fig. 7B is a layout diagram of a section of a first exemplary layout cell 700B based on layout base cell 700A from Fig. 7A in accordance with some embodiments. In Fig. 7B features the first layout cell 700B PO structures and Mo areas for conductive conduit structures at the Mo layer, as indicated by the legends. In Fig. Layout area 7B exhibits first layout cell 700B with further VD structure candidates at layout area 701 in both the upper and lower sections; VD structure candidates at layout area 703 in both the upper and lower sections; and VD structure candidates at layout area 705 in both the upper and lower sections. Therefore, each of layout areas 701, 703, and 705 is based on incorporating VD structures adjacent to opposite sides of the layout area, while each of layout areas 702 and 704 is based on preventing any VD structures adjacent to opposite sides of the layout area. In this example, VD structure candidates adjacent to the cell boundary are permitted within surfaces 712, 714, and 716 parallel to the direction of the PO structures. In some embodiments, a complementary counterpart to the example is shown in Fig. 7B is defined based on the first layout cell 700B, such that each of layout areas 701, 703 and 705 is based on preventing any VD structures that border opposite sides of the layout area, while each of layout areas 702 and 704 is based on allowing VD structures that border opposite sides of the layout area.

[0057] Fig. 7C is a layout diagram of a section of an exemplary second layout cell 700C based on layout base cell 700A by Fig. 7A in accordance with some embodiments. In Fig. 7C features a second layout cell, 700C PO structures and M0 areas for conductive trace structures at the Mo layer, as indicated by the legends. Fig. Layout cell 700C further exhibits VD structure candidates at layout regions 701, 703, and 705 adjacent to a top side of the second layout cell 700C; and VD structure candidates at layout regions 702 and 704 adjacent to a bottom side of the second layout cell 700C. Therefore, each of layout regions 701, 703, and 705 is based on acquiring VD structures adjacent to one side of the layout region, while each of layout regions 702 and 704 is based on acquiring VD structures adjacent to the other side of the layout region. In this example, VD structure candidates adjacent to the cell boundary are permitted within area 718, which has a zigzag structure. In some embodiments, a complementary counterpart to the example is shown in Fig. 7C is defined based on vertically flipping the second layout cell 700C.

[0058] Fig. 7D is a layout diagram of a section of an exemplary third layout cell 700D based on layout base cell 700A from Fig. 7A in accordance with some embodiments. In Fig. 7D features third layout cell 700D PO structures and Mo areas for conductive conduit structures at the Mo layer, as indicated by the legends. In Fig. In 7D, the third layout cell 700D has four layout regions 701', 702', 703', and 704' with corresponding PO structures located in their center. In some embodiments, for the purpose of determining placement site types, layout regions 701', 702', 703', and 704' are defined by layout regions 701, 702, 703, and 704, respectively, in Fig. 7A connected.

[0059] In Fig. Layout area 7D further exhibits VG structure candidates at layout area 701' in both the upper and lower sections; and VG structure candidates at layout area 703' in both the upper and lower sections. Therefore, each of layout areas 701' and 703' is based on allowing VG structures adjacent to opposite sides of the layout area, while each of layout areas 702' and 704' is based on preventing any VG structures adjacent to opposite sides of the layout area. In this example, VG structure candidates adjacent to the cell boundary are permitted within areas 722 and 724 parallel to the direction of the PO structures. In some embodiments, a complementary counterpart to the example is shown in Fig. 7D is defined based on the third layout cell 700D, such that each of layout areas 701' and 703' is based on preventing any VG structures that border opposite sides of the layout area, while each of layout areas 702' and 704' is based on allowing VG structures that border opposite sides of the layout area.

[0060] Fig. 7E is a layout diagram of a section of an exemplary fourth layout cell 700E based on layout base cell 700A from Fig. 7A in accordance with some embodiments. In Fig. 7E features the fourth layout cell 700E PO structures and Mo areas for conductive conduit structures at the Mo layer, as indicated by the legends. In Fig. Layout cell 700E further exhibits VG structure candidates at layout regions 701' and 703' adjacent to a lower side of the fourth layout cell 700E; and VG structure candidates at layout regions 702' and 704' adjacent to an upper side of the fourth layout cell 700E. Therefore, each of layout regions 701' and 703' is based on acquiring VG structures adjacent to one side of the layout region, while each of layout regions 702' and 704' is based on acquiring VG structures adjacent to the other side of the layout region. In this example, VG structure candidates adjacent to the cell boundary are permitted within area 728, which has a zigzag structure. In some embodiments, a complementary counterpart to the example is shown in Fig. 7E is defined based on vertically flipping the fourth layout cell 700E.

[0061] Fig. 7F is a layout diagram of a section of an exemplary fifth layout cell 700F based on the layout base cell 700A from Fig. 7A in accordance with some embodiments. In Fig. 7F features the fifth layout cell 700F PO structures and Mo areas for conductive conduit structures at the Mo layer, as indicated by the legends. In Fig. Layout area 7F further exhibits the fifth layout cell 700F with Vo structure candidates at layout area 701 in both the upper and lower sections of layout area 701; and with layout area 703 with Vo structure candidates in both the upper and lower sections of layout area 703. Therefore, each of layout areas 701 and 703 is based on allowing Vo structures adjacent to opposite sides of the layout area, while each of layout areas 702 and 704 is based on preventing any V0 structures adjacent to opposite sides of the layout area. In this example, Vo structure candidates adjacent to the cell boundary are permitted within areas 732 and 736, which are parallel to the direction of the PO structures. In some embodiments, a complementary counterpart to the example is shown in Fig. 7F is defined based on the fifth layout cell 700F, such that each of layout areas 701 and 703 is based on preventing any Vo structures that border opposite sides of the layout area, while each of layout areas 702 and 704 is based on allowing Vo structures that border opposite sides of the layout area.

[0062] Fig. 7G is a layout diagram of a section of an exemplary sixth layout cell 700G based on the layout base cell 700A from Fig. 7A in accordance with some embodiments. In Fig. 7G features the sixth layout cell 700G PO structures and Mo areas for conductive trace structures at the Mo layer, as indicated by the legends. Fig. In 7G, the sixth layout cell 700G further exhibits Vo structure candidates at layout regions 703 and 705 adjacent to a top side of the sixth layout cell 700G; and Vo structure candidates at layout regions 702 and 704 adjacent to a bottom side of the sixth layout cell 700G. Therefore, each of layout regions 703 and 705 is based on acquiring Vo structures adjacent to one side of the layout region, while each of layout regions 702 and 704 is based on acquiring V0 structures adjacent to the other side of the layout region. In this example, Vo structure candidates adjacent to the cell boundary are permitted within area 738, which has a zigzag structure. In some embodiments, a complementary counterpart to the example is shown in Fig. 7G is defined based on vertically flipping the sixth layout cell, 700G.

[0063] Fig. 7H is a layout diagram of a section of an exemplary seventh layout cell 700H based on the layout base cell 700A from Fig. 7A in accordance with some embodiments. In Fig. 7H features the seventh layout cell 700H PO structures and Mo areas for conductive conduit structures at the Mo layer, as indicated by the legends. In Fig. 7H, the upper and lower Mo regions adjacent to the upper and lower cell boundaries are suitable for conductive Mo conduction structures 742 when connecting with the corresponding Vo structures in Fig. 7F to form. In some embodiments, a complementary counterpart of the example in Fig. 7H based on the complementary counterpart of the example in Fig. 7F defined.

[0064] Fig. 7I is a layout diagram of a section of an exemplary eighth layout cell 700I based on the layout base cell 700A from Fig. 7A in accordance with some embodiments. In Fig. 7I features the eighth layout cell 700I PO structures and Mo areas for conductive conduit structures at the Mo layer, as indicated by the legends. In Fig. 7I are the upper and lower Mo regions adjacent to the upper and lower cell boundaries suitable for conductive Mo pathway structures 746 in conjunction with the corresponding Vo structures in Fig. 7G to form. In some embodiments, a complementary counterpart of the example in Fig. 7IH based on the complementary counterpart of the example in Fig. 7G defined.

[0065] In some embodiments, various combinations of restrictions are possible, as illustrated by the examples in Fig. 7B-7I and the corresponding complementary counterpart examples are shown, useful for creating layout candidate cells for a set of placement sites with suitable placement site types of an edge placement site of the set of placement sites in a reverse first direction (e.g., the leftmost edge placement site, corresponding to layout area 701 in Fig. 7A-7I). In some embodiments and as non-limiting examples, a layout candidate cell has a set of placement sites, where a leftmost edge placement site is the first placement type, as in Fig. Figure 6 illustrates a first combination of constraints based on the examples in Fig. 7B, Fig. 7D, Fig. 7F and Fig. 7H, a second combination of restrictions based on the examples in Fig. 7B, Fig. 7E, Fig. 7F and Fig. 7H, a third combination of constraints based on complementary counterpart examples of the examples in Fig. 7C, Fig. 7D, Fig. 7G and Fig. 7I and a fourth combination of constraints based on complementary counterpart examples of the examples in Fig. 7C, Fig. 7E, Fig. 7G and Fig. 7I. Also, in some embodiments and as non-limiting examples, a layout candidate cell has a set of placement sites, wherein a far left edge placement site is the second placement type, as in Fig. Figure 6 illustrates a fifth combination of constraints based on complementary counterpart examples of the examples in Fig. 7B, Fig. 7D, Fig. 7F and Fig. 7H, a sixth combination of constraints based on complementary counterpart examples of the examples in Fig. 7B, Fig. 7E, Fig. 7F and Fig. 7H, a seventh combination of constraints based on the examples in Fig. 7C, Fig. 7D, Fig. 7G and Fig. 7I and an eighth combination of restrictions based on the examples in Fig. 7C, Fig. 7E, Fig. 7G and Fig. 7I on.

[0066] Furthermore, not all inverted variations of a layout candidate cell are usable to meet the constraints and guidelines, as described in Fig. 5A, Fig. 5B and Fig. 6 illustrates how to fulfill this requirement. In this respect, Fig. Figures 8A-8C are simplified layout diagrams of various inverted variations of a layout candidate base cell in accordance with some embodiments. Fig. In 8A-8C, the letter "F" and the triangle in the corners of the layout cells are used to indicate how the layout cells are flipped relative to each other.

[0067] In Fig. 8A has a layout candidate base cell 812 with a cell width of an odd number of CPP (e.g., a cell width of 5 CPP) and is usable for a scenario where the leftmost edge placement location is a specific placement type (e.g., the first placement type, labeled with the number 1, in this example). In some embodiments, the horizontally inverted variation 814 (e.g., inverted with respect to the Y-axis, indicated by the arrow labeled "MY") of layout candidate base cell 812 is still usable for the scenario where the leftmost edge placement location is this specific placement type if VD structures, Vo structures, or Mo path structures are connected to Vo structures adjacent to a bottom side of layout candidate base cell 812, and no VG structures are present adjacent to the bottom side of layout candidate base cell 812.In some embodiments, the horizontally inverted variation 814 is not usable at all if VG structures are present adjacent to the bottom of the layout candidate base cell 812. In some embodiments, there are no restrictions regarding the use of the horizontally inverted variation 814 if no VD structures, Vo structures, Mo-rail structures associated with Vo structures, or VG structures are present adjacent to the bottom of the layout candidate base cell 812.

[0068] In Fig. Layout candidate base cell 822 (8B) has a cell width of an even number of CPP (e.g., a cell width of 6 CPP) and is usable for a scenario where the leftmost edge placement location is a specific placement type (e.g., the first placement type, labeled 1 in this example). In some embodiments, the horizontally inverted variation 824 of layout candidate base cell 822 is usable for the scenario where the leftmost edge placement location is a different placement type (e.g., the second placement type, labeled 2 in this example) if there are VD structures, Vo structures, or Mo path structures connected to Vo structures adjacent to a bottom side of layout candidate base cell 822, and no VG structures adjacent to the bottom side of layout candidate base cell 822.In some embodiments, the horizontally inverted variation 824 of layout candidate base cell 822 is still usable for the scenario where the leftmost edge placement location is this particular placement type (e.g., the first placement type, labeled with the number 1 in this example) when there are no VD structures, Vo structures, or Mo path structures connected to Vo structures adjacent to the bottom of layout candidate base cell 822, and VG structures adjacent to the bottom of layout candidate base cell 822. In some embodiments, the horizontally inverted variation 824 is not usable at all if VD structures, Vo structures or Mo orbital structures are present that are connected to Vo structures adjacent to the bottom of the layout candidate base cell 822, and VG structures are present that adjacent to the bottom of the layout candidate base cell 822.In some embodiments, there are no restrictions regarding the use of the horizontally inverted variation 824 when there are no VD structures, V0 structures, Mo orbit structures connected to Vo structures, or VG structures adjacent to the bottom of the layout candidate base cell 822.

[0069] In Fig. Layout candidate base cell 832, 8C, has a cell height of an even number of standard cell heights (e.g., a cell height of 2H) and is usable for a scenario where the bottom leftmost edge placement location is a specific placement type (e.g., the first placement type, labeled with the number 1 in this example). As such, in this example, with a cell height of 2H, the top leftmost edge placement location would be an inverted version of another placement type (e.g., the inverted second placement type, labeled with the inverted number 2 in this example). In some embodiments, the vertically inverted variation 834 (e.g., inverted with respect to an X-axis, indicated by the arrow labeled "MX") of layout candidate base cell 832 is usable for the scenario where the bottom leftmost edge placement location is the other placement type.

[0070] Fig. 9A is a simplified layout diagram of a section of an exemplary layout plan 900A in accordance with some embodiments. Fig. Layout plan 900A shows several placement locations, similar to those described in relation to Fig. Figure 6 illustrates where each rectangular box containing the number 1, 2, vertically inverted 1, or vertically inverted 2 represents a placement location for different placement types. Various layout cells in Fig. 9A are used as non-restrictive examples of how layout cells and their variations with respect to placement locations can be considered in light of the examples in Fig. 8A-8C will be placed.

[0071] In Fig. 9A is a first layout base cell 910 for a set of placement sets, where the leftmost edge placement location is a first placement type. In this example, the first layout base cell 910 has a cell width of 5 CPP and a cell height of 1 H. In some embodiments, a layout cell 912 based on the first layout base cell 910 is also usable for a scenario where a leftmost edge placement location is the first placement type. In some embodiments, a layout cell 914, based on a vertical inversion of the first layout base cell 910, is usable for a scenario where a leftmost edge placement location is an inverted first placement type. In some embodiments, a layout cell 916, based on a horizontal inversion of the first layout base cell 910, is usable for a scenario where a leftmost edge placement location is the first placement type.In some embodiments, a layout cell 918, based on a vertical inversion of layout cell 916, is also usable for a scenario where a far left edge placement location is an inverted first placement type.

[0072] Furthermore, in this example, a second layout base cell 920 is used for a set of placement sets, where the leftmost edge placement location is a second placement type. In this example, the second layout base cell 920 has a cell width of 5 CPP and a cell height of 1 H. In some embodiments, a layout cell 922, based on a vertical inversion of the second layout base cell 920, is usable for a scenario where a leftmost edge placement location is an inverted second placement type. In some embodiments, layout cells 924 and 926, based on a horizontal inversion of the second layout base cell 920, are usable for a scenario where a leftmost edge placement location is a second placement type.In some embodiments, a layout cell 928, based on a vertical inversion of layout cell 926, is also usable for a scenario where a far left edge placement location is an inverted second placement type.

[0073] In some embodiments according to the example in Fig. 9A The layout candidate cells for a circuit cell with a cell width of 5 CPP and a cell height of 1 H have at least one first layout base cell 910 for the leftmost edge placement location, which is a first placement type, and a second layout base cell 920 for the leftmost edge placement location, which is a second placement type. Incidentally, the horizontally inverted first layout base cell (e.g., layout cell 916) is also usable for the leftmost edge placement location, which is the first placement type; and the horizontally inverted second layout base cell (e.g., layout cell 926) is also usable for the leftmost edge placement location, which is the second placement type. That is to say, in some embodiments, four variants of layout cells for a circuit cell (width: 5 CPP and height: 1 H) are produced, which, in conjunction with the placement locations in Fig. 6 is to be used in order to comply with the restrictions and guidelines set out in the examples in Fig. 5A and Fig. 5B is illustrated.

[0074] Fig. 9B is a simplified layout diagram of a section of an exemplary layout plan 900B in accordance with some embodiments. Fig. Layout plan 900B shows several placement locations, similar to those referenced in Fig. Figure 6 illustrates where each rectangular box containing the number 1, 2, vertically inverted 1, or vertically inverted 2 represents a placement location. Various layout cells in Fig. 9B are used as non-restrictive examples of how layout cells and their variations with respect to placement locations can be considered in light of the examples in Fig. 8A-8C will be placed.

[0075] In Fig. 9B is a layout base cell 960 for a set of placement sets, where the bottom leftmost edge placement location is a first placement type. In this example, layout base cell 960 has a cell width of 9 CPP and a cell height of 2 H. In some embodiments, a layout cell 962 based on layout base cell 960 is also usable for a scenario where a bottom leftmost edge placement location is the first placement type and an upper leftmost edge placement location is an inverted second placement type. In some embodiments, a layout cell 964, based on a vertical inversion of layout base cell 960, is usable for a scenario where a bottom leftmost edge placement location is an inverted second placement type.In some embodiments, a layout cell 976, based on a horizontal inversion of the layout base cell 960, is usable for a scenario where a bottom-left edge placement location is the first placement type. In some embodiments, layout cells 972 and 974, based on a vertical inversion of the layout cell 970, are also usable for a scenario where a bottom-left edge placement location is the second placement type.

[0076] In some embodiments, according to the example in Fig. 9B, the layout candidate cells for a circuit cell with a cell width of 9 CPP and a cell height of 2 H have at least one layout base cell (e.g., layout cell 960) for the bottom leftmost edge placement site, which is a first placement type, and a vertically inverted layout base cell (e.g., layout cell 964) for the bottom leftmost edge placement site, which is a second placement type. That is, in some embodiments, two variants of layout cells for a circuit cell (width: 9 CPP and height: 2 H) are produced, which, in conjunction with the placement sites in Fig. 6 and the examples of restrictions in Fig. 5A and Fig. 5B are to be used.

[0077] Fig. Figure 10A is a circuit diagram of an AND-OR-INVERT logic (AOI logic) 1000A in accordance with some embodiments. Fig. The 10A features AOI logic 1000A with P-transistors 1012, 1014, 1016 and 1018 and N-transistors 1022, 1024, 1026 and 1028. Fig. The first drain / source terminal of P-transistor 1012 is electrically coupled to a first power supply (labeled VDD). A second drain / source terminal of P-transistor 1012 is electrically coupled to a first drain / source terminal of P-transistor 1014. A second drain / source terminal of P-transistor 1014 is electrically coupled to an output terminal ZN of AOI logic 1000A. A first drain / source terminal of P-transistor 1016 is electrically coupled to the first power supply. A second drain / source terminal of P-transistor 1016 is electrically coupled to a first drain / source terminal of P-transistor 1018 and the first drain / source terminal of P-transistor 1014. A second drain / source terminal of P-transistor 1018 is electrically coupled to the output terminal ZN.

[0078] The first drain / source terminal of N-transistor 1022 is electrically coupled to the output terminal ZN. The second drain / source terminal of N-transistor 1022 is electrically coupled to the first drain / source terminal of N-transistor 1024. The second drain / source terminal of N-transistor 1024 is electrically coupled to a second power supply (labeled GND). The first drain / source terminal of N-transistor 1026 is electrically coupled to the output terminal ZN. The second drain / source terminal of N-transistor 1026 is electrically coupled to the first drain / source terminal of N-transistor 1028. The second drain / source terminal of N-transistor 1028 is electrically coupled to the second power supply.

[0079] In Fig. The gate terminals of P-transistor 1014 and N-transistor 1022 are electrically coupled to input terminal A1 of AOI-Logik 1000A. The gate terminals of P-transistor 1018 and N-transistor 1024 are electrically coupled to input terminal A2 of AOI-Logik 1000A. The gate terminals of P-transistor 1012 and N-transistor 1026 are electrically coupled to input terminal B1 of AOI-Logik 1000A. The gate terminals of P-transistor 1016 and N-transistor 1028 are electrically coupled to input terminal B2 of AOI-Logik 1000A. Therefore, AOI-Logik 1000A is configured to perform a logic operation based on the expression ZN = / (A1A2 + B1B2).

[0080] Fig. 10B-10D are layout diagrams of layout candidate cells from AOI logic 1000A in Fig. 10A in accordance with some embodiments. Fig. 10B-10D contain legends for the various types of layout structures used, which are the same as the legends found in Fig. 4A are presented, and therefore a detailed description is omitted. In some embodiments, the layout candidate cells in Fig. 10B-10D restrictions based on different combinations of the examples in Fig. 7B-7E. In some embodiments, multiple layout candidate cells for AOI logic 1000A can be used to have an entire left (or bottom far left) edge placement location that is the first placement type or the second placement type, as in the example in Fig. 6 shown, in view of the examples in Fig. 7A-9B.

[0081] In Fig. In 10B, layout cell 1000B has a cell width of 5 CPP and a cell height of 1 H. Layout cell 1000B conforms to a combination of constraints based on the examples from Fig. 7B and Fig. 7D matches. Layout cell 1000B also matches a combination of constraints based on the examples from Fig. 7B and Fig. 7E. In this example, layout cell 1000B has VG structures 1012, 1014, 1016 and 1018 corresponding to input terminals A1, A2, B1 and B2 in Fig. 10A. In this example, the layout cell 1000B further features an M1 conductive conductor structure 1022 corresponding to the output terminal ZN in Fig. 10A on.

[0082] In Fig. Layout cell 10C, specifically cell 1000B, has a cell width of 3 CPP and a cell height of 2 H. Layout cell 1000C conforms to a combination of constraints based on the examples from Fig. 7C and Fig. 7D. In this example, layout cell 1000C has VG structures 1032, 1034, 1036 and 1038 corresponding to input terminals A1, A2, B1 and B2 in Fig. 10A. In this example, the layout cell 1000C further features a conductive M1 conductor structure 1042 corresponding to output terminal ZN in Fig. 10A on.

[0083] In Fig. Layout cell 1000D (10D) has a cell width of 5 CPP and a cell height of 1 H. Layout cell 1000D conforms to a combination of constraints based on the examples from Fig. 7C and Fig. 7E. In this example, layout cell 1000D has VG structures 1052, 1054, 1056 and 1058 corresponding to input terminals A1, A2, B1 and B2 in Fig. 10A. In this example, the layout cell 1000D further features a conductive M1 conductor structure 1062 corresponding to output terminal ZN in Fig. 10A on.

[0084] Fig. Figure 11A is a circuit diagram of a NAND logic gate 1100A in accordance with some embodiments. Fig. 11A features NAND logic 1100A, P-transistors 1112 and 1114, and N-transistors 1116 and 1118. Fig. The first drain / source terminal of P-transistor 1112 and the first drain / source terminal of P-transistor 1114 are electrically connected to a first power supply (labeled VDD). A second drain / source terminal of P-transistor 1112 and a second drain / source terminal of P-transistor 1114 are electrically connected to an output terminal ZN of NAND logic 1100A. A first drain / source terminal of N-transistor 1116 is electrically connected to output terminal ZN. A second drain / source terminal of N-transistor 1116 is electrically connected to a first drain / source terminal of N-transistor 1118. A second drain / source terminal of N-transistor 1118 is electrically connected to a second power supply (labeled GND).

[0085] In Fig. In NAND logic 1100A, the gate terminals of P-transistor 1112 and N-transistor 1116 are electrically coupled to input terminal A1 of NAND logic 1100A. The gate terminals of P-transistor 1114 and N-transistor 1118 are electrically coupled to input terminal A2 of NAND logic 1100A. Therefore, NAND logic 1100A is configured to perform a logic operation based on the expression ZN = / A1A2.

[0086] Fig. 11B-11C are layout diagrams of layout candidate cells of NAND logic 1100A in Fig. 11A in accordance with some embodiments. Fig. 11B-11C contain legends of the various types of layout structures used therein, which are the same as the legends found in Fig. 4A are presented, and therefore a detailed description is omitted. In some embodiments, the layout candidate cells in Fig. 11B-11C restrictions based on various combinations of the examples in Fig. 7B-7E. In some embodiments, multiple layout candidate cells for NAND logic 1100A can be used to have a far left edge placement location that is the first placement type or the second placement type, as in the example in Fig. 6 illustrates, in view of the examples in Fig. 7A-9B.

[0087] In Fig. Layout cell 11B has a cell width of 3 CPP and a cell height of 1 H. Layout cell 1100B conforms to a combination of constraints based on the examples from Fig. 7B and Fig. 7D, a combination of restrictions based on the examples of Fig. 7B and Fig. 7E or a combination of the restrictions based on the examples from Fig. 7C and Fig. 7D. In this example, layout cell 1100B has VG structures 1122 and 1124 corresponding to input terminals A1 and A2 in Fig. 11A. In this example, the layout cell 1100B further features a conductive Mo line structure 1132 corresponding to output terminal ZN in Fig. 11A on.

[0088] In Fig. Layout cell 11C has a cell width of 3 CPP and a cell height of 1 H. Layout cell 1100C conforms to a combination of constraints based on the examples from Fig. 7C and Fig. 7E. In this example, the layout cell 1100C has VG structures 1142 and 1144 corresponding to the input terminals A1 and A2 in Fig. 11A. In this example, the layout cell 1100C further features a conductive Mo conductor structure 1152 corresponding to output terminal ZN in Fig. 11A on.

[0089] Fig. Figure 12A is a diagram of a simplified exemplary layout plan 1200A in accordance with some embodiments. Fig. In section 12A, the exemplary layout plan 1200A shows several layout cells that contain gate structures and corresponding VD structures (unlabeled). Fig. 12A, based on the placement locations and restrictions in the examples from Fig. 6 and considering the implementation examples in Fig. 7A-11C are VD structures adjacent to a cell boundary within an area 1210 with a zigzag shape arranged along the cell boundary, adhering to the constraints and guidelines as described in Fig. 5A illustrates, fulfill.

[0090] Fig. Figure 12B is a diagram of a simplified exemplary layout plan 1200B in accordance with some embodiments. Fig. In the exemplary layout plan 1200B, section 12B shows several layout cells that contain gate structures and corresponding VG structures (not labeled). Fig. 12B are based on the placement positions and restrictions in the examples from Fig. 6 and considering the implementation examples in Fig. 7A-11C, VG structures adjacent to a cell boundary within an area 1220 arranged in a zigzag shape along the cell boundary, adhering to the constraints and guidelines as described in Fig. 5A illustrates, fulfill.

[0091] Fig. Figure 13 is a flowchart of a method 1300 for creating a layout plan for a semiconductor device in accordance with some embodiments. In some embodiments, different operations of method 1300 correspond to different combinations of the examples in Fig. 6-12B, to meet the restrictions or guidelines based on zigzag structures for various structural elements, as in Fig. 5A and Fig. 5B illustrates this. In some embodiments, method 1300 corresponds to one or more operations that are wholly or partially based on an EDA system 1500, as shown in Fig. 15 illustrated, and / or an IC manufacturing system 1600, as in Fig. 16 illustrates how to carry out the process. As in Fig. 13 comprises procedure 1300 blocks 1310-1330.

[0092] In block 1310, a first layout cell (e.g., layout cell 510 or layout cell 520) is created. Fig. 5A-5B) in the layout plan (e.g., Layout Plan 500). In some embodiments, the first layout cell specifies a first circuit cell, includes one or more first conductive trace structures that specify one or more first conductive traces in a first metallization trace region of a first metallization layer (e.g., Mo traces for the Mo layer), and includes one or more first via trace structures that specify one or more first via traces below the first metallization layer (e.g., VD traces for the VD layer or VG traces for the VG layer).

[0093] Block 1320 contains a second layout cell (e.g., layout cell 520 or layout cell 530). Fig. 5A-5B) in the layout plan (e.g., Layout Plan 500). In some embodiments, the second layout cell specifies a second circuit cell and is located at an intermediate cell boundary with the first layout cell. In some embodiments, the second layout cell has one or more second conductive trace structures specifying one or more second conductive traces in a second metallization trace region of the first metallization layer (e.g., Mo trace structures for the Mo layer), and has one or more second via trace structures specifying one or more second via trace structures below the first metallization layer (e.g., VD trace structures for the VD layer or VG trace structures for the VG layer). In some embodiments, the first metallization trace region and the second metallization trace region are spaced apart by a common space and extend along the cell boundary.

[0094] In some embodiments, based on the fact that the one or more first via structures and the one or more second via structures belong to a first via layer between the first metallization layer and a conductive drain / source layer of the layout plan (e.g., VD structures for the VD layer), the one or more first via structures and the one or more second via structures are located within a first surface (e.g., first surface 542 in Fig. 5A) with a first zigzag structure along the cell boundary. In some embodiments, based on the fact that the one or more first via structures and the one or more second via structures belong to a second via layer between the first metallization layer and a gate layer of the layout plan (e.g., VG structures for the VG layer), the one or more first via structures and the one or more second via structures are located within a second surface with a second zigzag structure along the cell boundary (e.g., second surface 546 in Fig. 5A).

[0095] In block 1330, the layout plan, which includes the first layout cell and the second layout cell, is stored in a memory of a processing device (e.g., EDA system 1500 in Fig. 15).

[0096] In some embodiments, the cell boundary extends along a first direction, and the first metallization conduction region and the second metallization conduction region are based on a metallization pitch (e.g., Mo-pitch in Fig. 5A) along a second direction that differs from the first direction. In some embodiments, based on the fact that the one or more first via structures and the one or more second via structures belong to a first via layer between the first metallization layer and a conductive drain / source layer of the layout plan (e.g., VD structures for the VD layer), the one or more first via structures and the one or more second via structures are arranged based on a first minimum via pitch (e.g., VD pitch' in Fig. 5A) arranged, which is larger than the metallization pitch. In some embodiments, based on the fact that the one or more first via structures and the one or more second via structures belong to a second via layer between the first metallization layer and the gate layer of the layout plan (e.g., VG structures for the VG layer), the one or more first via structures and the one or more second via structures are based on a second minimum via pitch (e.g., VG pitch in ). Fig. 5A) arranged, which is larger than the metallization pitch.

[0097] In some embodiments, one or more gate structures (e.g., PO structures in) are used. Fig. 5A) in the gate layer of the layout plan based on a gate pitch (e.g. 1 CPP in Fig. 5A) along the first direction. In some embodiments, the first minimum via pitch (e.g., VD Pitch') is in Fig. 5A) one of at least twice the metallization pitch or at least the gate pitch. In some embodiments, the second minimum via pitch (e.g., VG pitch) is Fig. 5A) one of at least twice the metallization pitch or at least the gate pitch.

[0098] In some embodiments, the first layout cell further features one or more third via structures (e.g., Vo structures of layout cell 520 in Fig. 5A), which belong to a third via layer between the first metallization conduction area and a third metallization conduction area of ​​a second metallization layer (e.g., M1 layer) above the first metallization layer (e.g., Mo layer); and the second layout cell further features one or more fourth via structures (e.g., Vo structures of layout cell 530 in Fig. 5A) belonging to the third via layer. In some embodiments, the one or more third via structures are separated from the one or more fourth via structures based on at least one third minimum via pitch (e.g., Vo-pitch' in Fig. 5A) spaced apart, which is larger than the metallization pitch. In some embodiments, the third minimum via pitch is one of at least twice the metallization pitch or at least the gate pitch.

[0099] In some embodiments, the first layout cell further features a third conductive conductor structure (e.g., an M1 structure of cell 520 in Fig. 5A) of the second metallization layer (e.g., M1 layer), the second layout cell further features a fourth conductive conductor structure (e.g., an M1 structure of cell 530 in Fig. 5A) of the second metallization layer, and the third conductive conductor structure and the fourth conductive conductor structure are aligned along a second direction. In some embodiments, the third conductive conductor structure and the fourth conductive conductor structure are based on a minimal end-to-end distance (e.g., M1 EtE' in Fig. 5A) arranged, which extends along the second direction and is larger than the metallization pitch.

[0100] In some embodiments, the first layout cell and the second layout cell have sections of a CMD structure (e.g., CMD structure 552 in Fig. 5B) to define one or more first conductive drain / source structures of the first circuit cell and one or more second conductive drain / source structures of the second circuit cell. In some embodiments, the CMD structure has a third zigzag structure along the cell boundary. In some embodiments, the first layout cell and the second layout cell have sections of a CPO structure (e.g., CPO structure 556 in Fig. 5B) to define one or more first gate structures of the first circuit cell and one or more second gate structures of the second circuit cell. In some embodiments, the CPO structure has a fourth zigzag structure along the cell boundary.

[0101] Fig. Figure 14 is a flowchart of a method 1400 for creating a layout plan for a semiconductor device in accordance with some embodiments. In some embodiments, different operations of method 1400 correspond to different combinations of the examples in Fig. 6-12B, to meet the restrictions or guidelines based on zigzag structures for various structural elements, as in Fig. 5A and Fig. 5B illustrates this. In some embodiments, method 1400 corresponds to one or more operations that are wholly or partly based on an EDA system 1500, as shown in Fig. 15 illustrated, and / or an IC manufacturing system 1600, as in Fig. 16 illustrates how to carry out the process. As in Fig. 14 comprises procedure 1400 blocks 1410-1430.

[0102] Block 1410 contains a set of placement positions (e.g., the set of placement positions 630 in Fig. 6) from several placement sites (e.g. the several placement sites 600 in Fig. 6) of the layout plan for a target layout cell, which specifies a target circuit cell. In some embodiments, each of the multiple placement locations of the layout plan has a width along a first direction corresponding to a gate pitch (e.g., 1 CPP in Fig. 6) of the layout plan and a height along a second direction corresponding to a standard cell height (e.g. 1 H in Fig. 6) of the layout plan. In some embodiments, the multiple placement locations include a first row of placement locations (e.g., row 612, 614, or 616) comprising first placement locations of a first placement type and second placement locations of a second placement type, arranged alternately along the first direction and usable for placing a standard layout cell of standard cell height in a target shape. In some embodiments, the multiple placement locations include a second row of placement locations (e.g., row 615 or 617) comprising third placement locations of an inverted first placement type and fourth placement locations of an inverted second placement type, arranged alternately along the first direction and usable for placing the standard layout cell in an inverted shape, which corresponds to a mirror image of the target shape about an axis along the first direction.In some embodiments, the target layout cell has a cell height equal to the standard cell height, or the target layout cell has twice the cell height of the standard cell height.

[0103] In some embodiments, as based on the examples in Fig. 5A and Fig. As illustrated in Figure 5B, a shared space is defined along a boundary between the first row and the second row, where the shared space is free of layout structures in a first metallization layer of the layout plan. In some embodiments, such as the non-restrictive example in Fig. As shown in Figure 6, the first placement sites of the first row of placement sites are located at the fourth placement sites of the second row of placement sites. In some embodiments, such as the non-restrictive example in Fig. As shown in Figure 6, the second placement sites of the first row of placement sites are located adjacent to the third placement sites of the second row of placement sites. In some embodiments, the first placement type indicates the inclusion of a via structure beneath the first metallization layer of the layout plan, located adjacent to a side in the reverse second direction of a corresponding placement site. In some embodiments, the second placement type indicates the exclusion of a via structure beneath the first metallization layer of the layout plan, located adjacent to a side in the reverse second direction of the corresponding placement site.

[0104] In block 1420, one of several layout candidate cells connected to the target circuit cell is placed as the target layout cell in the set of placement locations based on a placement location type of an edge placement location of the set of placement locations in a reverse first direction (e.g., the leftmost edge placement location), as in the non-restrictive example in Fig. 6 is described, where layout candidate cells are considered in light of the examples in Fig. 7A-11C are manufactured.

[0105] In some embodiments, the multiple layout candidate cells connected to the target circuit cell include a layout candidate cell having one or more first layout regions and one or more second layout regions arranged alternately along the first direction, and each of the one or more first layout regions and one or more second layout regions corresponds to a respective placement site.

[0106] In some embodiments, each of the one or more first layout regions is based on acquiring via structures under the first metallization layer of the layout plan, which is adjacent to opposite sides of the layout candidate cell with respect to the second direction, and each of the one or more second layout regions is based on preventing any via structures under the first metallization layer of the layout plan, which is adjacent to opposite sides of the layout candidate cell with respect to the second direction.

[0107] In some embodiments, each of the one or more first layout regions is based on incorporating a first via structure under the first metallization layer of the layout plan, which is adjacent to a first side of the layout candidate cell, and preventing any via structures under the first metallization layer of the layout plan that are adjacent to a second side of the layout candidate cell. In some embodiments, each of the one or more second layout regions is based on incorporating a second via structure under the first metallization layer of the layout plan, which is adjacent to the second side of the layout candidate cell, and preventing any via structures under the first metallization layer of the layout plan that are adjacent to the first side of the layout candidate cell.In some embodiments, the first side of the layout candidate cell and the second side of the layout candidate cell are opposite sides with respect to the second direction.

[0108] In some embodiments, the via structures are located between the first metallization layer and one or more first conductive drain / source layers of the layout plan (e.g., VD structures in Fig. 5A). In some embodiments, the via structures are located between the first metallization layer and one or more first gate layers of the layout plan (e.g., VG structures in Fig. 5A).

[0109] In block 1430, the layout plan, which includes the layout cell, is stored in a memory of a processing device (e.g., EDA system 1500 in Fig. 15) saved.

[0110] Fig. Figure 15 is a block diagram of an EDA system 1500 in accordance with some embodiments. In some embodiments, the EDA system 1500 includes an automatic placement and routing (APR) system. Methods described here relating to the placement of layout cells can, for example, be implemented using the EDA system 1500 in accordance with some embodiments.

[0111] In some embodiments, the EDA system 1500 is a general-purpose computing device comprising a hardware processor 1502 and a memory 1504, which has a non-transient, computer-readable storage medium. Memory 1504 is, among other things, encoded with, i.e., stores, computer program code 1506, i.e., a set of executable instructions. Execution of instructions 1506 by the hardware processor 1502 provides (at least in part) an EDA tool that implements some or all of the procedures described herein in accordance with one or more embodiments (hereinafter, the specified processes and / or procedures).

[0112] Processor 1502 is electrically connected to memory 1504 via a bus 1508. Processor 1502 is also electrically connected to an I / O interface 1510 via bus 1508. A network interface 1512 is also electrically connected to processor 1502 via bus 1508. Network interface 1512 is connected to a network 1514, enabling processor 1502 and memory 1504 to communicate with external elements via network 1514. Processor 1502 is configured to execute computer program code 1506, which is encoded in memory 1504, to cause system 1500 to be usable for carrying out some or all of the specified processes and / or procedures. In one or more embodiments, processor 1502 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application-specific integrated circuit (ASIC) and / or a suitable processing unit.

[0113] In one or more embodiments, Memory 1504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, Memory 1504 comprises semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or video disk. In one or more embodiments utilizing video disks, Memory 1504 comprises a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disc (DVD).

[0114] In one or more embodiments, memory 1504 stores computer program code 1506 configured to cause the system 1500 (where such an embodiment is (at least partially) the EDA tool) to be usable for carrying out part or all of the specified processes and / or procedures. In one or more embodiments, memory 1504 also stores information that facilitates carrying out part or all of the specified processes and / or procedures. In one or more embodiments, memory 1504 stores a standard cell library 1507 of standard cells, containing such standard cells as disclosed herein. In one or more embodiments, memory 1504 stores one or more layout diagrams 1509 corresponding to one or more layouts disclosed herein.

[0115] The EDA system 1500 has an I / O interface 1510. The I / O interface 1510 is coupled to an external circuit. In one or more embodiments, the I / O interface 1510 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or pointer keys for communicating information and commands to the processor 1502.

[0116] EDA System 1500 also features a network interface 1512, which is coupled to processor 1502. Network interface 1512 enables System 1500 to communicate with network 1514, to which one or more other computer systems are connected. Network interface 1512 includes wireless network interfaces such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or wired network interfaces such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the specified processes and / or procedures are implemented in two or more Systems 1500.

[0117] System 1500 is configured to receive information through I / O interface 1510. The information received through I / O interface 1510 contains one or more instructions, data, design rules, libraries of standard cells, and / or other parameters for processing by processor 1502. The information is transmitted to processor 1502 via bus 1508. EDA system 1500 is also configured to receive information through I / O interface 1510 that relates to a user interface (UI). This information is stored in memory 1504 as user interface (UI) 1542.

[0118] In some embodiments, some or all of the specified processes and / or procedures are implemented as a standalone software application for execution by a processor. In some embodiments, some or all of the specified processes and / or procedures are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the specified processes and / or procedures are implemented as a plug-in to a software application. In some embodiments, at least one of the specified processes and / or procedures is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the specified processes and / or procedures are implemented as a software application used by the EDA System 1500.In some embodiments, a layout diagram containing standard cells is created using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout creation tool.

[0119] In some embodiments, the processes are executed as functions of a program stored in a non-transitory, computer-readable recording medium. Examples of a non-transitory, computer-readable recording medium include, but are not limited to, external / removable and / or internal / built-in mass storage or memory unit, such as one or more video disks like a DVD, magnetic disks like a hard disk, semiconductor memory such as a ROM, RAM, memory card, and the like.

[0120] Fig. Figure 16 is a block diagram of an IC fabrication system 1600 and an associated IC fabrication process in accordance with some embodiments. In some embodiments based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor IC is fabricated using fabrication system 1600.

[0121] In Fig. System 1660 comprises IC manufacturing system 1600 units, such as a design house 1620, a mask house 1630, and an IC manufacturer / fabricator (fab) 1650, which interact in the design, development, and manufacturing cycles and / or services related to the manufacture of an IC device 1660. The units in system 1600 are connected by a communication network. In some embodiments, the communication network is a single network. In other embodiments, the communication network is a set of different networks, such as an intranet and the internet. The communication network includes wired and / or wireless communication channels. Each unit interacts with one or more of the other units, providing and / or receiving services to one or more of the other units. In some embodiments, two or more design houses 1620, mask houses 1630, and IC fabs 1650 belong to a single larger company.In some embodiments, two or more of Design House 1620, Mask House 1630 and IC fab 1650 exist together in a common facility and use common resources.

[0122] Design House (or Design Team) 1620 creates an IC design layout diagram 1622. IC design layout diagram 1622 shows various geometric structures designed for an IC device 1660. The geometric structures correspond to structures of metal, oxide, or semiconductor layers that form the various components of IC device 1660 to be manufactured. The different layers are combined to form various IC structural elements. For example, a section of IC design layout diagram 1622 shows various IC structural elements, such as an active region, gate electrode, source and drain, metal traces or vias of an interlayer interconnect, and openings for bonding pads to be formed in a semiconductor substrate (such as a silicon wafer), and various material layers arranged on the semiconductor substrate.Design House 1620 implements a suitable design procedure to create IC design layout diagram 1622. The design procedure includes one or more logic design, physical design, or placement and routing steps. IC design layout diagram 1622 is presented in one or more data files containing information about the geometric structures. For example, IC design layout diagram 1622 can be expressed in a GDSII or DFII file format.

[0123] Mask House 1630 comprises Data Generation 1632 and Mask Fabrication 1644. Mask House 1630 uses IC Design Layout Diagram 1622 to fabricate one or more masks 1645, which are to be used to fabricate the various layers of IC Device 1660 according to the IC Design Layout Diagram 1622. Mask House 1630 performs Mask Data Generation 1632, where the IC Design Layout Diagram 1622 is translated into a Representative Data File (RDF). Mask Data Generation 1632 provides the RDF to Mask Fabrication 1644. Mask Fabrication 1644 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reticule) 1645 or a semiconductor wafer 1653. The design layout diagram 1622 is manipulated by mask data creation 1632 to meet certain properties of the mask writer and / or requirements of IC fab 1650. In Fig.Figure 16 illustrates mask data creation 1632 and mask production 1644 as separate elements. In some embodiments, mask data creation 1632 and mask production 1644 can be referred to collectively as mask data creation.

[0124] In some embodiments, mask data creation 1632 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image defects such as those that may arise from diffraction, interference, or other process effects, and the like. OPC adapts the IC design layout diagram 1622. In some embodiments, mask data creation 1632 further includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary structure elements, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0125] In some embodiments, mask data creation 1632 includes a mask rule checker (MRC) that checks the IC design layout diagram 1622, which has undergone processes in OPC, against a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient leeway to accommodate variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout diagram 1622 to compensate for photolithographic implementation effects during mask fabrication 1644, which may undo some of the modifications made by OPC to satisfy mask creation rules.

[0126] In some embodiments, mask data creation 1632 includes lithography process checking (LPC), which simulates the processing implemented by the IC fab 1650 to manufacture IC fixture 1660. LPC simulates this processing based on the IC design layout diagram 1622 to generate a simulated manufactured fixture such as IC fixture 1660. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, after a simulated fabricated device has been created by LPC, OPC and / or MRC are repeated to further refine the IC design layout diagram 1622 if the shape of the simulated device is not close enough to the design rules.

[0127] It should be clear that the above description of a mask data creation process 1632 has been simplified for clarity. In some embodiments, data creation 1632 includes additional structural elements such as a logic operation (LOP) to modify the IC design layout diagram 1622 according to manufacturing rules. Additionally, the processes applied to the IC design layout diagram 1622 during data creation 1632 can be executed in numerous different sequences.

[0128] Following mask data creation 1632 and during mask fabrication 1644, a mask 1645 or a group of masks 1645 is fabricated based on the modified IC design layout diagram 1622. In some embodiments, mask fabrication 1644 includes performing one or more lithographic exposures based on the IC design layout diagram 1622. In some embodiments, an electron beam (E-beam) or a mechanism consisting of multiple E-beams is used to form a structure on a mask (photomask or reticulum) 1645 based on the modified IC design layout diagram 1622. The mask 1645 can be formed using various technologies. In some embodiments, the mask 1645 is formed using binary technology. In some embodiments, a mask structure has opaque and transparent regions.A radiation beam, such as an ultraviolet (UV) beam, used to expose the image-sensitive material layer (e.g., photoresist) applied to a wafer, is blocked by the opaque region and passes through the transparent regions. In one example, a binary mask version of Mask 1645 has a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chromium) applied to the opaque regions of the binary mask. In another example, Mask 1645 is formed using a phase-shift technology. In a phase-shift mask (PSM) version of Mask 1645, various structural elements in the structure formed on the phase-shift mask are arranged to have a suitable phase difference to improve resolution and image quality.In various examples, the phase-shift mask can be a weakened PSM or an alternating PSM. The mask(s) produced by mask fabrication 1644 are used in numerous processes. For example, such a mask is used in an ion implantation process to create differently doped regions in the semiconductor wafer 1653, in an etching process to create different etched regions in the semiconductor wafer 1653, and / or in other suitable processes.

[0129] IC Fab 1650 is an IC manufacturing company that has one or more manufacturing facilities for producing numerous different IC products. In some configurations, IC Fab 1650 is a semiconductor factory. For example, there may be one manufacturing facility for the front-end manufacturing of several IC products (front-end-of-line manufacturing (FEOL manufacturing)), while a second manufacturing facility may provide the back-end manufacturing for interconnection and packaging of the IC products (back-end-of-line manufacturing (BEOL manufacturing)), and a third manufacturing facility may provide other services for the factory.

[0130] IC fab 1650 comprises manufacturing tools 1652 configured to perform various manufacturing operations on semiconductor wafers 1653, such that IC device 1660 is manufactured according to the mask(s), e.g., mask 1645. In various embodiments, manufacturing tools 1652 comprise one or more wafer steppers, ion implanters, photoresist coaters, process chambers (e.g., CVD chambers or LPCVD furnaces), CMP systems, plasma etching systems, wafer cleaning systems, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0131] IC fab 1650 uses mask(s) 1645, manufactured by mask house 1630, to fabricate IC device 1660. Thus, IC fab 1650 uses, at least indirectly, the IC design layout diagram 1622 to fabricate IC device 1660. In some embodiments, semiconductor wafer 1653 is fabricated by IC fab 1650 using mask(s) 1645 to form IC device 1660. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based, at least indirectly, on the IC design layout diagram 1622. Semiconductor wafer 1653 has a silicon substrate or other suitable substrate with material layers formed on it. Semiconductor wafer 1653 further features one or more differently doped regions, dielectric structural elements, multi-layer interconnects and the like (which are formed in the following manufacturing steps).

[0132] In some aspects, a semiconductor device comprises a first circuit cell that includes one or more first conductive traces in a first metallization conduction region of a first metallization layer and one or more first vias beneath the first metallization layer. The semiconductor device further comprises a second circuit cell adjacent to the first circuit cell at an intermediate cell boundary, wherein the second circuit cell includes one or more second conductive traces in a second metallization conduction region of the first metallization layer and one or more second vias beneath the first metallization layer. The first metallization conduction region and the second metallization conduction region are spaced apart by a common space and extend along the cell boundary.Based on the fact that the one or more first via structures are located between the first metallization layer and one or more first conductive drain / source structures of the first circuit cell, and the one or more second via structures are located between the first metallization layer and one or more second conductive drain / source structures of the second circuit cell, the one or more first via structures and the one or more second via structures are located within a first area with a first zigzag structure along the cell boundary.Based on the fact that the one or more first via structures are located between the first metallization layer and one or more first gate structures of the first circuit cell, and the one or more second via structures are located between the first metallization layer and one or more second gate structures of the second circuit cell, the one or more first via structures and the one or more second via structures are located within a second area with a second zigzag structure along the cell boundary.

[0133] In some aspects, a procedure for creating a layout plan for a semiconductor device involves placing a first layout cell in the layout plan and placing a second layout cell in the layout plan. The first layout cell specifies a first circuit cell, includes one or more first conductive trace structures, which specify one or more first conductive traces in a first metallization trace region of a first metallization layer, and includes one or more first via structures, which specify one or more first vias below the first metallization layer.The second layout cell specifies a second circuit cell, is located adjacent to the first layout cell at an intermediate cell boundary, has one or more second conductive trace structures specifying one or more second conductive traces in a second metallization trace region of the first metallization layer, and has one or more second via structures specifying one or more second via structures below the first metallization layer. The method further includes storing, in a memory of a processing device, the layout plan containing the first layout cell and the second layout cell. The first metallization trace region and the second metallization trace region are spaced apart by a common space and extend along the cell boundary.Based on the assumption that the one or more first via structures and the one or more second via structures belong to a first via layer between the first metallization layer and a conductive drain / source layer of the layout plan, the one or more first via structures and the one or more second via structures are located within a first surface with a first zigzag structure along the cell boundary.Based on the fact that the one or more first via structures and the one or more second via structures belong to a second via layer between the first metallization layer and a gate layer of the layout plan, the one or more first via structures and the one or more second via structures are located within a second surface with a second zigzag structure along the cell boundary.

[0134] In some aspects, a method for creating a layout plan for a semiconductor device involves obtaining a set of placement sites from multiple placement sites of the layout plan for a target layout cell, specifying a target circuit cell. Each of the multiple placement sites of the layout plan has a width along a first direction corresponding to a gate pitch of the layout plan and a height along a second direction corresponding to a standard cell height of the layout plan. The multiple placement sites have a first row of placement sites, comprising first placement sites of a first placement type and second placement sites of a second placement type, arranged alternately along the first direction and usable for placing a standard layout cell of standard cell height in a desired shape.The multiple placement locations include a second row of placement locations, a third row of placement locations of an inverted first placement type, and a fourth row of placement locations of an inverted second placement type, arranged alternately along the first direction and usable for placing the standard layout cell in an inverted form, corresponding to a mirror image of the intended shape about an axis along the first direction. A shared space is defined along a boundary between the first and second rows, the shared space being free of any layout structures in a first metallization layer of the layout plan.The first placement sites of the first row of placement sites are adjacent to the fourth placement sites of the second row of placement sites, and the second placement sites of the first row of placement sites are adjacent to the third placement sites of the second row of placement sites. The first placement type specifies the inclusion of a via structure beneath the first metallization layer of the layout plan, adjacent to a side in the reverse second direction of a corresponding placement site. The second placement type specifies the prevention of any via structure beneath the first metallization layer of the layout plan, adjacent to a side in the reverse second direction of the corresponding placement site.The procedure involves placing several candidate layout cells, connected to the target layout cell, at the set of placement sites based on a placement site type of an edge placement site of the set of placement sites in a reverse first direction. The procedure further involves storing the layout plan, which includes the layout cell, in a memory of a processing device.

[0135] The foregoing outlines features of some embodiments or examples so that those skilled in the art will better understand the aspects of this disclosure. Those skilled in the art will appreciate that they can already use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same benefits as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent designs do not deviate from the nature and scope of this disclosure, and that they can make various changes, substitutions, and modifications herein without deviating from the nature and scope of this disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 703,782

[0001]

Claims

[1] Semiconductor device comprising: a first circuit cell comprising one or more first conductive conductors in a first metallization conduction region of a first metallization layer and comprising one or more first via structures below the first metallization layer; and a second circuit cell which is adjacent to the first circuit cell at an intermediate cell boundary, wherein the second circuit cell has one or more second conductive conductors in a second metallization conduction area of ​​the first metallization layer and has one or more second via structures below the first metallization layer, where: the first metallization conduction area and the second metallization conduction area are separated from each other by a common space extending along the cell boundary, based on the fact that the one or more first via structures are located between the first metallization layer and one or more first conductive drain / source structures of the first circuit cell, and that the one or more second via structures are located between the first metallization layer and one or more second conductive drain / source structures of the second circuit cell, the one or more first via structures and the one or more second via structures are located within a first region with a first zigzag structure along the cell boundary, and based on the fact that the one or more first via structures are located between the first metallization layer and one or more first gate structures of the first circuit cell, and that the one or more second via structures are located between the first metallization layer and one or more second gate structures of the second circuit cell, wherein the one or more first via structures and the one or more second via structures are located within a second region with a second zigzag structure along the cell boundary. [2] Semiconductor device according to claim 1, wherein: the cell boundary extends along a first direction, the first metallization conduit area and the second metallization conduit area are arranged based on a metallization pitch along a second direction that differs from the first direction, based on the fact that the one or more first via structures are located between the first metallization layer and the one or more first conductive drain / source structures of the first circuit cell, and the one or more second via structures are located between the first metallization layer and the one or more second conductive drain / source structures of the second circuit cell, the one or more first via structures and the one or more second via structures are arranged based on a first minimum via pitch that is larger than the metallization pitch, and based on the fact that the one or more first via structures are located between the first metallization layer and the one or more first gate structures of the first circuit cell, and the one or more second via structures are located between the first metallization layer and the one or more second gate structures of the second circuit cell, the one or more first via structures and the one or more second via structures are arranged based on a second minimum via pitch that is larger than the metallization pitch. [3] Semiconductor device according to claim 2, wherein: the one or more first gate structures and the one or more second gate structures are arranged based on a gate pitch along the first direction, the first minimum via pitch is at least twice the metallization pitch and / or at least the gate pitch and the second minimum via pitch is at least twice the metallization pitch and / or at least the gate pitch. [4] Semiconductor device according to claim 2 or 3, wherein: the first circuit cell further comprises one or more third via structures between the first metallization conduction area and a third metallization conduction area of ​​a second metallization layer above the first metallization layer, the second circuit cell further features one or more fourth via structures between the second metallization conduction area and a fourth metallization conduction area of ​​the second metallization layer and the one or more third via structures are spaced from the one or more fourth via structures based on at least a third minimum via pitch that is larger than the metallization pitch. [5] Semiconductor device according to claim 4, wherein the third minimum via pitch is at least twice the metallization pitch and / or at least the gate pitch. [6] Semiconductor device according to claim 4 or 5, wherein: the first circuit cell further exhibits a third conductive line of the second metallization layer, the second circuit cell further has a fourth conductive conductor of the second metallization layer, the third conductive line and the fourth conductive line are aligned along the second direction and the third conductive line and the fourth conductive line are arranged based on a minimum end-to-end distance extending along the second direction and greater than the metallization pitch. [7] Semiconductor device according to any one of the preceding claims, wherein: the one or more first conductive drain / source structures and the one or more second conductive drain / source structures based on a cut metal-on-diffusion (CMD) structure are spaced apart and The CMD structure exhibits a third zigzag structure along the cell boundary. [8] Semiconductor device according to any one of the preceding claims, wherein: the one or more first gate structures and the one or more second gate structures are spaced apart based on a cut poly structure (CPO structure) and The CPO structure exhibits a fourth zigzag structure along the cell boundary. [9] Method for creating a layout plan for a semiconductor device, comprising: Placing a first layout cell in the layout plan, wherein the first layout cell specifies a first circuit cell and has one or more first conductive lines patterns that specify one or more first conductive lines in a first metallization line area of ​​a first metallization layer, and has one or more first via patterns that specify one or more first via structures below the first metallization layer; Placing a second layout cell in the layout plan, wherein the second layout cell specifies a second circuit cell and is adjacent to the first layout cell at an intermediate cell boundary, wherein the second layout cell has one or more second conductive trace patterns specifying one or more second conductive traces in a second metallization trace area of ​​the first metallization layer, and has one or more second via patterns specifying one or more second via structures below the first metallization layer; and Storing, in a memory of a processing device, the layout plan, which has the first layout cell and the second layout cell, where: the first metallization conduction area and the second metallization conduction area are separated from each other by a common space extending along the cell boundary, based on the fact that the one or more first via patterns and the one or more second via patterns belong to a first via layer between the first metallization layer and a conductive drain / source layer of the layout plan, wherein the one or more first via patterns and the one or more second via patterns are located within a first region with a first zigzag structure along the cell boundary, and based on the fact that the one or more first via patterns and the one or more second via patterns belong to a second via layer between the first metallization layer and a gate layer of the layout plan, the one or more first via patterns and the one or more second via patterns are located within a second area with a second zigzag structure along the cell boundary. [10] Method according to claim 9, wherein: the cell boundary extends along a first direction, the first metallization conduit area and the second metallization conduit area are arranged based on a metallization pitch along a second direction that differs from the first direction, based on the fact that the one or more first via patterns and the one or more second via patterns belong to a first via layer between the first metallization layer and a conductive drain / source layer of the layout plan, and that the one or more first via patterns and the one or more second via patterns are arranged based on a first minimum via pitch that is larger than the metallization pitch and based on the fact that the one or more first via patterns and the one or more second via patterns belong to a second via layer between the first metallization layer and the gate layer of the layout plan, the one or more first via patterns and the one or more second via patterns are arranged based on a second minimum via pitch that is larger than the metallization pitch. [11] Method according to claim 10, wherein: one or more gate structures are arranged in the gate layer of the layout plan based on a gate pitch along the first direction, the first minimum via pitch is at least twice the metallization pitch and / or at least the gate pitch and the second minimum via pitch is at least twice the metallization pitch and / or at least the gate pitch. [12] Method according to claim 10 or 11, wherein: the first layout cell further features one or more third via patterns belonging to a third via layer between the first metallization conduction area and a third metallization conduction area of ​​a second metallization layer above the first metallization layer, the second layout cell further features one or more fourth via patterns belonging to the third via layer, and the one or more third via patterns are spaced from the one or more fourth via patterns based on at least a third minimum via pitch that is larger than the metallization pitch. [13] Method according to claim 12, wherein the third minimum via pitch is at least twice the metallization pitch and / or at least the gate pitch. [14] Method according to claim 12 or 13, wherein: the first layout cell further exhibits a third conductive conduction pattern of the second metallization layer, the second layout cell further exhibits a fourth conductive conduction pattern of the second metallization layer, the third conductive pattern and the fourth conductive pattern are aligned along a second direction and The third conductive conduction pattern and the fourth conductive conduction pattern are arranged based on a minimum end-to-end distance extending along the second direction and greater than the metallization pitch. [15] Method according to any one of claims 9 to 14, wherein: The first layout cell and the second layout cell have sections of a cut metal-on-diffusion (CMD) structure to define one or more first conductive drain / source structures of the first circuit cell and one or more second conductive drain / source structures of the second circuit cell. The CMD structure exhibits a third zigzag structure along the cell boundary. [16] Method according to any one of claims 9 to 15, wherein: The first layout cell and the second layout cell have sections of a cut poly structure (CPO structure) for defining one or more first gate structures of the first circuit cell and one or more second gate structures of the second circuit cell and The CPO structure exhibits a fourth zigzag structure along the cell boundary. [17] Method for creating a layout plan for a semiconductor device, comprising: Obtaining a set of placement locations from multiple placement locations of the layout plan for a target layout cell, specifying a target circuit cell, wherein each of the multiple placement locations of the layout plan has a width along a first direction corresponding to a gate pitch of the layout plan and a height along a second direction corresponding to a standard cell height of the layout plan, wherein the multiple placement locations: a first row of placement sites, comprising first placement sites of a first placement type and second placement sites of a second placement type, arranged alternately along the first direction and usable for placing a standard layout cell of standard cell height in a target shape, and a second row of placement locations, which includes third placement locations of an inverted first placement type and fourth placement locations of an inverted second placement type, arranged alternately along the first direction and usable for placing the standard layout cell in an inverted shape that corresponds to a reflection of the desired shape about an axis along the first direction, wherein a shared space is defined along a boundary between the first row and the second row, wherein the shared space is free of any layout structures in a first metallization layer of the layout plan, the first placement positions of the first row of placement positions are located at the fourth placement positions of the second row of placement positions, the second placement positions of the first row of placement positions are located at the third placement positions of the second row of placement positions, the first placement type indicates the inclusion of a via structure below the first metallization layer of the layout plan, which is adjacent to a side in the reverse second direction of a corresponding placement site, and the second placement type specifies a prevention of any through-hole structure under the first metallization layer of the layout plan, which is adjacent to the side in the reverse second direction of the corresponding placement location; Placing one of several layout candidate cells connected to the target circuit cell, as the target layout cell, at the set of placement sites based on a placement site type of an edge placement site of the set of placement sites in a reverse first direction; and Storing, in a memory of a processing device, the layout plan, which has the layout cell. [18] Method according to claim 17, wherein: the multiple layout candidate cells connected to the target circuit cell, each having a layout candidate cell that has one or more first layout areas and one or more second layout areas arranged alternately along the first direction, each of the one or more first layout areas and of the one or more second layout areas corresponding to a respective placement site, each of the one or more first layout areas is based on the recording of via patterns under the first metallization layer of the layout plan, which is placed adjacent to opposite sides of the layout candidate cell with respect to the second direction, and Each of the one or more second layout areas is based on preventing any through-hole plating patterns under the first metallization layer of the layout plan, which are adjacent to opposite sides of the layout candidate cell with respect to the second direction. [19] Method according to claim 17, wherein: the multiple layout candidate cells connected to the target circuit cell, each having a layout candidate cell that has one or more first layout areas and one or more second layout areas arranged alternately along the first direction, each of the one or more first layout areas and of the one or more second layout areas corresponding to a respective placement site, each of the one or more first layout areas is based on the inclusion of a first via pattern under the first metallization layer of the layout plan, which is adjacent to a first side of the layout candidate cell, and on the prevention of any via patterns under the first metallization layer of the layout plan, which are adjacent to a second side of the layout candidate cell, each of the one or more second layout areas is based on the inclusion of a second via pattern under the first metallization layer of the layout plan, which is adjacent to the second side of the layout candidate cell, and on preventing any via patterns under the first metallization layer of the layout plan that are adjacent to the first side of the layout candidate cell. The first side of the layout candidate cell and the second side of the layout candidate cell are opposite sides with respect to the second direction. [20] Method according to any one of claims 17 to 19, wherein: the target layout cell has a cell height of the standard cell height or The target layout cell has twice the cell height of the standard cell height.

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