OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING AN OPTOELECTRONIC SEMICONDUCTOR CHIP

Abstract

Optoelectronic semiconductor chip (23) with - a semiconductor body (22) comprising a first semiconductor region (3), a second semiconductor region (5) and an active zone (4) arranged between the first and second semiconductor regions (3, 5), - an electrically conductive contact layer (7) which is arranged on a side of the first semiconductor region (3) facing away from the second semiconductor region (5), - an electrically conductive mirror layer (6) arranged between the first semiconductor region (3) and the electrically conductive contact layer (7) and laterally overlaid at the edge by the first semiconductor region (3) and the electrically conductive contact layer (7), so that a space (8) is located between the first semiconductor region (3) and the electrically conductive contact layer (7), in which a protective layer (9) is arranged to protect the mirror layer (6), wherein - the electrically conductive contact layer (7) extends laterally to an edge of the first semiconductor region (3), - the electrically conductive contact layer (7) consists of Ni, and - a connecting layer is arranged between the electrically conductive mirror layer (6) and the electrically conductive contact layer (7), which is formed from a transparent electrically conductive oxide.

Description

[0001] An optoelectronic semiconductor chip is described, comprising a semiconductor body with an active zone particularly suitable for generating electromagnetic radiation. Furthermore, a method for manufacturing an optoelectronic semiconductor chip is described.

[0002] Optoelectronic semiconductor chips and methods for manufacturing an optoelectronic semiconductor chip are known from the documents US 2012 / 0098016A1, DE 102007022947A1, US 9231163B2 and US 2003 / 0075723A1.

[0003] Optoelectronic semiconductor chips are known that feature a mirror layer on the semiconductor body to reflect the electromagnetic radiation emitted by the active zone. One possible method for manufacturing such a semiconductor chip involves applying a relatively thick protective layer of SiO2 to the mirror layer during the structuring of the semiconductor body. This protective layer then serves as an etching mask for structuring the semiconductor body. A disadvantage of this method is that the selectivity of the etching mask is limited, meaning that the semiconductor body cannot be etched to an arbitrarily deep depth.Another disadvantage is that the mirror layer, which is intended in particular for electrical contacting the semiconductor body, is covered with an electrically insulating layer, so that an opening step is necessary for contacting, which either impairs the adhesion of the protective layer around this opening and / or reduces the quality of the mirror layer.

[0004] One problem to be solved is to specify an optoelectronic semiconductor chip with improved quality with regard to the mirror layer. This problem is solved by an optoelectronic semiconductor chip with the features of the independent product claim.

[0005] Another problem to be solved is to specify an improved method for manufacturing such a semiconductor chip. This problem is solved by a method with the features of the independent method claim.

[0006] The process for manufacturing an optoelectronic semiconductor chip comprises the following steps: - Providing a substrate, - Deposition of a semiconductor layer sequence comprising a first semiconductor region, an active zone on a side of the first semiconductor region facing the substrate, and a second semiconductor region on a side of the active zone facing away from the first semiconductor region, - Applying an electrically conductive mirror layer and an electrically conductive contact layer to the first semiconductor region, wherein the electrically conductive mirror layer is positioned between the first semiconductor region and the electrically conductive contact layer, - Structuring of the electrically conductive contact layer, - Structuring of the electrically conductive mirror layer by means of the structured electrically conductive contact layer, - Structuring of the semiconductor layer sequence using the structured electrically conductive contact layer.

[0007] Preferably, the above-mentioned process steps are carried out in the specified order.

[0008] According to a preferred embodiment, the substrate is a growth substrate on which the first and second semiconductor regions are epitaxially deposited. In this context, "epitaxially deposited on the growth substrate" means that the growth substrate serves for the deposition and / or growth of the first and second semiconductor regions. For example, the second semiconductor region is in direct contact with the growth substrate. The growth substrate can be removed after the growth of the first and second semiconductor regions or remain in the finished semiconductor chip, in the latter case forming part of a semiconductor body.

[0009] The electrically conductive mirror layer and contact layer deposited on the semiconductor layer sequence or the first semiconductor region have, in particular, two main lateral directions of extension, both of which are perpendicular to a vertical direction in which the first and second semiconductor regions are arranged one above the other. The extent of the two layers along the main lateral directions of extension is preferably greater than in the vertical direction. The thickness of the mirror layer and contact layer is determined along the vertical direction.

[0010] In the structuring of the mirror layer, a concave groove is formed within it. This means that the mirror layer is slightly recessed beneath the contact layer. In the context of this application, "slightly" is understood to mean a lateral projection of the contact layer beyond the mirror layer of at most 1 µm. The resulting concave groove causes the mirror layer to project laterally beyond the edge of the first semiconductor region and the electrically conductive contact layer, creating a gap between the first semiconductor region and the electrically conductive contact layer. In particular, "lateral" refers to an arrangement in or parallel to a principal plane defined by the two principal lateral extension directions.

[0011] In a preferred embodiment, a photolithographic process is used to structure the contact layer. In particular, an image of a mask is created in the contact layer. The contact layer can then be structured, for example, by wet chemical etching, whereby areas of the contact layer to be removed are etched away, for example, using hydrochloric acid. The remaining areas of the contact layer then serve as a mask for structuring the mirror layer and the semiconductor layer sequence. Thicknesses between 100 nm and 200 nm are suitable for the contact layer. Preferably, the electrically conductive contact layer is made of nickel. One advantage of an electrically conductive material like nickel is that, compared to a conventional etching mask made of an electrically insulating material like SiO2, no opening step is required for contacting the mirror layer.Rather, the mirror layer can be electrically contacted via the electrically conductive contact layer.

[0012] According to at least one embodiment of the method, the reflective layer can also be structured by wet chemical etching. In this process, the structured, electrically conductive contact layer serves as an etching mask, through which the structure of the reflective layer is determined. Preferably, an etching agent is used that acts selectively against the material of the contact layer and leads to a slight undercutting of the contact layer. Preferably, the reflective layer is formed from silver or an silver-based material.

[0013] A bonding layer consisting of a transparent, electrically conductive oxide is placed between the mirror layer and the contact layer. Transparent conductive oxides (TCOs) are transparent, conductive materials, typically metal oxides such as zinc oxide, tin oxide, cadmium oxide, titanium oxide, indium oxide, or indium tin oxide (ITO). Besides binary metal-oxygen compounds, such as ZnO, SnO₂, or In₂O₃, ternary metal-oxygen compounds, such as Zn₂SnO₄, CdSnO₃, ZnSnO₃, MgIn₂O₄, GaInO₃, Zn₂In₂O₅, or In₄Sn₃O₁₂, or mixtures of different transparent conductive oxides, also belong to the group of TCOs. Furthermore, TCOs do not necessarily have a stoichiometric composition and can also be p- or n-doped.

[0014] According to at least one embodiment of the method, a protective layer is arranged in the space between the mirror layers to protect the mirror layer. In particular, the protective layer prevents further erosion of the mirror layer during subsequent structuring steps, especially during the etching of the semiconductor layer sequence. Electrically weakly conductive or insulating materials and / or one of the materials SiO2 or Al2O3 are suitable for the protective layer. In the finished semiconductor chip, the protective layer at least partially fills the space. Preferably, the protective layer does not project laterally beyond the contact layer in the finished semiconductor chip. Furthermore, the protective layer is advantageously completely covered by the contact layer. This means, in particular, that an area of ​​the protective layer facing the contact layer is completely covered by the contact layer.In the fabrication of the protective layer, the material used for the protective layer, for example TEOS (tetraethyl orthosilicate), can initially be applied in a gaseous state to areas of the first semiconductor region that lie outside the gap. Through a removal process, particularly using a dry etching method such as reactive ion etching (RIE), the material is then structured so that the areas of the first semiconductor region outside the gap are not covered by the protective layer. The structured contact layer can largely, and preferably completely, prevent the removal of the protective layer beneath it. Fluorine can be used as the etching agent. Alternatively, the protective layer material can also be applied to the first semiconductor region by atomic layer deposition (ALD). Al₂O₃ is particularly suitable as a material for the protective layer in this process.

[0015] After the protective layer is applied, the semiconductor layer sequence is structured. The semiconductor layer sequence is structured using the structured, electrically conductive contact layer; that is, the electrically conductive contact layer serves as a shaping mask. Here, too, a dry etching process, preferably reactive ion etching, is used. Chlorine can be used as the etching agent.

[0016] Materials based on nitride compound semiconductors are preferably considered for the semiconductor layer sequence or the first and second semiconductor regions of the semiconductor body. In this context, "based on nitride compound semiconductors" means that at least one layer of the semiconductor layer sequence is a nitride III / V compound semiconductor material, preferably Al. n Ga m In 1-n-mN comprises, where 0 ≤ n ≤ 1, 0 ≤ m ≤ 1, and n+m ≤ 1. This material does not necessarily have to have a mathematically exact composition according to the formula above. Rather, it can contain one or more dopants as well as additional components that impart the characteristic physical properties of the aluminum. n Ga m In 1-n-m The N-materials remain essentially unchanged. For the sake of simplicity, however, the above formula only includes the essential components of the crystal lattice (Al, Ga, In, N), even though these may be partially replaced by small amounts of other substances. Preferably, the first semiconductor region is a p-type region. Furthermore, the second semiconductor region is, in particular, an n-type region.

[0017] Advantageously, the method described here achieves a comparatively high selectivity of 20:1 to 50:1 between the semiconductor layer sequence and the electrically conductive contact layer. This enables etching depths that are advantageously greater than 2 µm.

[0018] In particular, the second semiconductor region has a connection layer, wherein the second semiconductor region is structured up to a lower edge of the connection layer. A residual region of the second semiconductor region, located between the connection layer and the substrate, thus projects laterally beyond the structured semiconductor layer sequence. The connection layer is preferably a highly doped semiconductor layer of the second semiconductor region. In particular, the connection layer can have the highest doping concentration in the semiconductor layer sequence. In other words, the connection layer can be so highly doped, at least in certain areas, that it has a higher doping concentration than all other regions of the semiconductor layer sequence.

[0019] According to at least one embodiment, a mesa shape is formed during the structuring of the semiconductor layer sequence. In other words, after structuring, the semiconductor layer sequence can exhibit a cross-sectional shape that widens from the first semiconductor region to the second. The vertical extent or height of the mesa-shaped region corresponds to the etching depth.

[0020] According to at least one embodiment, the electrically conductive mirror layer and contact layer are provided with an opening. Preferably, the opening is created using wet chemical processes. Advantageously, the opening extends vertically through the contact layer and mirror layer to the first semiconductor region. In particular, the opening is arranged in a central region of the contact layer and mirror layer. Alternatively, this step can be omitted. This means that the mirror layer and the contact layer can be continuous. In particular, the mirror layer and the contact layer are then also continuous in the finished semiconductor chip.

[0021] According to at least one embodiment of the method, an outer surface of a composite, which comprises the substrate, the semiconductor layer sequence, and further layers arranged on the semiconductor layer sequence, in particular the mirror layer and the contact layer, and which faces away from the substrate, is covered with an encapsulation. Furthermore, the opening in the mirror and contact layers can be filled with the encapsulation. Preferably, weakly conductive or insulating materials such as SiO2 are used for the encapsulation. The encapsulation can be applied by means of the aforementioned atomic layer deposition.

[0022] According to at least one embodiment of the method, a further reflective layer is applied to the composite, which now additionally includes the encapsulation. The application of this further reflective layer can be carried out by sputtering. In particular, the further reflective layer is applied to the encapsulation. Preferably, the further reflective layer is arranged such that it partially covers the contact layer on a side facing away from the first semiconductor region and is also arranged on side surfaces of the first and second semiconductor regions. In a preferred embodiment, the further reflective layer is formed from a metallic material, for example, aluminum or rhramide. The further reflective layer is provided, particularly in the region of the contact layer, with at least one opening in which a contact element can later be arranged for electrical contacting of the contact layer.

[0023] According to at least one embodiment of the method, the composite, which now additionally comprises the further mirror layer, is provided with a planarization that covers the side surfaces of the first and second semiconductor regions and fills at least one opening of the further mirror layer. Furthermore, the planarization preferably covers the remaining area of ​​the second semiconductor region and is laterally flush with it. Preferably, weakly conductive or insulating materials such as SiO2 are used for the planarization.

[0024] According to at least one embodiment of the method, an insulating layer is arranged on an outer surface of the composite, which is located on a side of the first semiconductor region facing away from the substrate. Preferably, electrically insulating materials such as SiO2 are used for the insulating layer.

[0025] According to at least one embodiment of the method, a further opening is created through the at least one opening in the further mirror layer. This further opening has a smaller diameter than the existing opening and extends through all layers, in particular the insulating layer, the planarization layer, and the encapsulation layer, to the contact layer. For example, the further opening can be created using a dry etching process such as reactive ion etching. Fluorine is used as the etchant in this process.

[0026] According to at least one embodiment of the method, a contact element is formed in the at least one further opening. The contact element is preferably formed from at least one electrically conductive material, in particular from a metal or a metal compound. For example, the contact element can be formed from two different materials, such as Rh and Ni, or from a Ni alloy such as NiSn instead of Ni.

[0027] According to at least one embodiment of the method, a support is applied to a side of the composite facing away from the substrate. Silicon, for example, is a suitable material for the support. It exhibits particularly good thermal conductivity.

[0028] The substrate on which the semiconductor layer sequence is arranged preferably contains or consists of a semiconductor material. Suitable materials include, for example, sapphire, SiC, and / or GaN. A sapphire substrate is transparent to short-wavelength visible radiation, particularly in the blue to green range. Since the wavelength of the radiation emitted by the active zone lies primarily within this wavelength range, such a growth substrate is transparent to the radiation emitted by the active zone.

[0029] In a preferred embodiment, the substrate can remain in the finished semiconductor chip. This is particularly the case if the substrate is transparent to the generated radiation and the semiconductor chip is a flip chip, in which the generated radiation is coupled out of the semiconductor chip through the substrate.

[0030] According to an alternative embodiment, the substrate is detached from the semiconductor layer sequence. For example, the substrate can be removed from the semiconductor layer sequence using laser lift-off. A semiconductor chip in which the substrate has been detached is called a thin-film semiconductor chip.

[0031] According to at least one embodiment, the substrate is detached, and after detachment, the second semiconductor region is thinned. This is done, in particular, up to the lower edge of the termination layer. Preferably, the remaining area of ​​the second semiconductor region is removed by means of a dry etching process such as reactive ion etching. An output coupling structure can be arranged on the termination layer, which improves the radiation extraction from the semiconductor body. In particular, the output coupling structure is formed from a low-absorbing material such as TiO2 or Nb2O5. Preferably, a passivation layer, which is formed, in particular, from SiO2, is arranged between the second semiconductor region and the output coupling structure.

[0032] According to an alternative embodiment, the remaining area of ​​the second semiconductor region is not removed. In particular, the remaining area is structured such that an output coupling structure is formed, which improves the radiation extraction from the semiconductor body. For example, the remaining area is roughened. This can be done using a dry etching process such as reactive ion etching. Preferably, a passivation layer, preferably made of SiO2 or Al2O3, is applied to the output coupling structure.

[0033] There are various possibilities for electrically contacting the semiconductor chip or for injecting current into the semiconductor chip.

[0034] According to a first embodiment, a connection element for current induction can be provided on the second semiconductor region. This element is preferably arranged centrally and covers only a small portion of the second semiconductor region. In this embodiment, the reflective layer and the contact layer, which are intended for current induction into the first semiconductor region, are preferably provided with an opening located in a central area, as already mentioned above. In particular, the connection element and the opening are arranged vertically one above the other. Furthermore, the opening is preferably filled with an electrically insulating material, especially the encapsulation. In the described arrangement, there is no direct current path between the connection element and the reflective layer during operation. Instead, the current paths are widened laterally.

[0035] According to a second variant, a contact layer for current induction can be applied to the second semiconductor region, covering most of it. In this variant, the reflective layer and the contact layer, which are intended for current induction into the first semiconductor region, are preferably formed continuously. In the described arrangement, direct current paths exist between the reflective layer and the contact layer during operation.

[0036] According to at least one embodiment of an optoelectronic semiconductor chip, the chip comprises a semiconductor body having a first semiconductor region, a second semiconductor region, and an active zone arranged between the first and second semiconductor regions. Furthermore, the optoelectronic semiconductor chip includes an electrically conductive contact layer arranged on the side of the first semiconductor region facing away from the second semiconductor region. The electrically conductive contact layer preferably extends laterally to an edge of the first semiconductor region. Additionally, an electrically conductive mirror layer is arranged between the first semiconductor region and the electrically conductive contact layer, and this mirror layer is laterally overridden by the electrically conductive contact layer at its edge. Simultaneously, the electrically conductive mirror layer is laterally overridden by the edge of the first semiconductor region.This creates a gap between the first semiconductor layer and the electrically conductive contact layer. A protective layer is placed in this gap to protect the mirror layer.

[0037] Preferably, the optoelectronic semiconductor chip is manufactured according to one of the methods described above. This allows the optoelectronic semiconductor chip to exhibit all the features mentioned in connection with the method.

[0038] According to at least one embodiment, the active zone of the semiconductor body is designed to generate electromagnetic radiation. In this context, "electromagnetic radiation" refers in particular to infrared, visible, and / or ultraviolet electromagnetic radiation. During operation, preferably a large proportion of the generated radiation is emitted from a radiation-emitting side of the semiconductor chip located on a side of the second semiconductor region facing away from the first. A rear side of the semiconductor chip is located on a side of the first semiconductor region facing away from the second semiconductor region.

[0039] The optoelectronic semiconductor chip has an electrically conductive contact layer made of nickel. Furthermore, the electrically conductive mirror layer may contain or consist of silver. In particular, the mirror layer is designed to reflect a large portion of the incident radiation towards the radiation-emitting side.

[0040] Furthermore, the optoelectronic semiconductor chip may have a protective layer made of a weakly conductive or insulating material and / or containing one of the materials SiO2, Al2O3.

[0041] According to at least one embodiment, a connecting layer, formed from a transparent, electrically conductive oxide, is arranged between the mirror layer and the contact layer. For example, the connecting layer can contain ZnO. The contact resistance between the contact layer and the mirror layer can be increased by means of the connecting layer, so that the current flow or current induction can be adjusted as desired.

[0042] According to at least one embodiment, the optoelectronic semiconductor chip has a further reflective layer arranged on a side of the electrically conductive contact layer facing away from the semiconductor body. This further reflective layer extends laterally beyond the contact layer and covers side surfaces of the semiconductor body. The proportion of radiation reflected towards the radiation emission side can be further increased by means of this additional reflective layer. Preferably, the additional reflective layer is an electrically conductive, and in particular metallic, layer. For example, the reflective layer can be made of aluminum or rhrhodium.

[0043] According to at least one embodiment, the encapsulation is arranged between the semiconductor body and the further mirror layer. Furthermore, the semiconductor body, the mirror layer, and the contact layer are laterally enclosed by the planarization. The further mirror layer is also laterally surrounded by the planarization.

[0044] In a preferred embodiment, the additional mirror layer is electrically insulated. In particular, the additional mirror layer is electrically insulated by means of the surrounding layers, which include, for example, the encapsulation and the planarization.

[0045] According to at least one embodiment, the optoelectronic semiconductor chip has at least one contact element for electrically contacting the contact layer, wherein the contact element is arranged in an opening of the further mirror layer. The contact element preferably contains at least one electrically conductive material, in particular a metal or a metal compound. For example, rh and nickel, or instead of pure nickel, a nickel alloy such as NiSn, can be used for the contact element. The at least one contact element can be a via extending vertically from a front face of the substrate facing the semiconductor body to the contact layer. Alternatively, the contact element can be a contact frame. This preferably extends along the side edges of the substrate when viewed from above.

[0046] According to at least one embodiment, the second semiconductor region comprises a connection layer that has the highest doping concentration in the semiconductor body. In other words, the connection layer can be so highly doped, at least in certain areas, that it has a higher doping concentration than all other regions of the semiconductor body. Preferably, the connection layer delimits the semiconductor body on the side of the second semiconductor region facing away from the first semiconductor region. That is, the connection layer forms a terminating layer of the semiconductor body on the side of the second semiconductor region facing away from the first semiconductor region.

[0047] According to at least one embodiment, the semiconductor body has a cross-sectional shape that widens from the first semiconductor region to the second semiconductor region. In other words, the semiconductor body has an inverted mesa shape in cross-section.

[0048] Using the method described above, it is possible to manufacture relatively small semiconductor chips. For example, a semiconductor chip as described here can have side lengths of no more than 150 µm.

[0049] Further advantages, advantageous embodiments and further developments result from the following in conjunction with the Fig. 1 to 20 described embodiments.

[0050] They show: Fig. 1 to 17 different steps of a method for manufacturing an optoelectronic semiconductor chip according to a first embodiment and Fig. 17 an optoelectronic semiconductor chip according to a first embodiment, Fig. 1 to 13 and 18 to 20 different steps of a method for manufacturing an optoelectronic semiconductor chip according to a second embodiment and Fig. 20 an optoelectronic semiconductor chip according to a second embodiment.

[0051] Fig. Figure 1 shows a step of a process for manufacturing an optoelectronic semiconductor chip, in which a substrate 1 is provided and a semiconductor layer sequence 2 is deposited on it. First, an n-type second semiconductor region 5 is arranged on the substrate 1, and then a p-type first semiconductor region 3 is arranged on the n-type semiconductor region 5. An active zone 4 is formed between the first and second semiconductor regions 3, 5. In other words, the semiconductor layer sequence 2 comprises a first semiconductor region 3, an active zone 4 on a side of the first semiconductor region 3 facing the substrate 1, and a second semiconductor region 5 on a side of the active zone 4 facing away from the first semiconductor region 3. Materials based on nitride compound semiconductors, in particular GaN, are preferably suitable for the semiconductor layer sequence 2 and the first and second semiconductor regions 3, 5.Preferably, the first semiconductor region 3 is epitaxially deposited on the second semiconductor region 5, and the second semiconductor region 5 is epitaxially deposited on the substrate 1, for example, by metal-organic vapor deposition. In particular, the second semiconductor region 5 is thicker than the first semiconductor region 3. For example, the first semiconductor region 3 can have a thickness of 130 nm, and the second semiconductor region can have a thickness of 6 µm. Deviations of 10% are acceptable.

[0052] Fig. Figure 2 shows a further process step in which a mirror layer 6 is applied to the first semiconductor region 3. Furthermore, a contact layer 7 is applied to the first semiconductor region 3 or to the mirror layer 6. Preferably, the mirror layer 6 is formed from an electrically conductive material, in particular a metal such as Ag. The contact layer 7 can be formed from an electrically conductive material, in particular a metal such as Ni.

[0053] In a preferred embodiment of the method, a compound layer is arranged on the mirror layer 6 before the contact layer 7 is applied (not shown). The electrical conductivity of the mirror layer 6 can be modified by means of the compound layer.

[0054] For example, the bonding layer can be formed from a transparent, electrically conductive oxide. The bonding layer can be used to increase the contact resistance of the mirror layer 6.

[0055] Fig. Figure 3 shows further steps of the process. First, the electrically conductive contact layer 7 is structured. Preferably, a photolithographic process is used for structuring the contact layer 7. In particular, the image of a mask is created in the contact layer 7. Subsequently, the contact layer 7 can be structured, for example, by wet chemical etching, whereby areas of the contact layer 7 to be removed are etched away, for example, using hydrochloric acid. The remaining areas of the contact layer 7 that are not removed then serve as a mask for structuring the mirror layer 6 and the semiconductor layer sequence 2. Thicknesses between 100 nm and 200 nm are suitable for the contact layer 7.

[0056] Subsequently, the mirror layer 6 is structured using the structured contact layer 7. This can be achieved by wet chemical etching. In particular, an etching agent is used that acts selectively against the material of the contact layer 7, resulting in a slight undercutting of the contact layer 7. This creates a concave area in the mirror layer 6, such that the mirror layer 6 is laterally overlaid at its edges by the first semiconductor region 3 and the electrically conductive contact layer 7, forming a gap 8 between the first semiconductor region 3 and the electrically conductive contact layer 7. The gap 8 has a lateral dimension d of at most 1 µm. In other words, the lateral overhang of the contact layer 7 over the mirror layer 6 is at most 1 µm.

[0057] Fig. Figure 4 shows a further process step in which a protective layer 9 is created in the space 8. The material used for the protective layer 8 can initially also be applied to areas of the first semiconductor region 3 that lie outside the space 8. By a removal process, in particular by means of a dry etching process such as reactive ion etching (RIE), the material is then structured so that the areas of the first semiconductor region 3 that lie outside the space 8 are not covered by the protective layer 9. The protective layer 9 at least partially fills the space 8. The structured contact layer 7 can largely, preferably completely, prevent the removal of the protective layer 9 below the contact layer 7. Fluorine can be used as the etching agent. Electrically weakly conductive or insulating materials and / or one of the materials SiO2 or Al2O3 are suitable for the protective layer 9.For example, TEOS (tetraethyl orthosilicate) can be used as a starting material for SiO2, deposited at low pressure and low flow rate with a thickness between 50 nm and 400 nm. Alternatively, the material can be deposited by atomic layer deposition (ALD). In particular, the protective layer 9 prevents the mirror layer 6 from being attacked during further structuring steps, especially during the etching of the semiconductor layer sequence 2.

[0058] Fig. Figure 5 shows a further process step in which the semiconductor layer sequence 2 is structured. The semiconductor layer sequence 2 is structured by means of the structured contact layer 7, i.e., the structured contact layer 7 serves as a shaping mask. In particular, a dry etching process, preferably reactive ion etching, is used here. Chlorine can be used as the etchant.

[0059] Advantageously, the method described here achieves a comparatively high selectivity of 20:1 to 50:1 between the semiconductor layer sequence 2 and the structured contact layer 7. This enables etch depths T that are advantageously greater than 2 µm. In particular, the second semiconductor region 5 has a connection layer 5A, wherein the second semiconductor region 5 is structured up to a lower edge of the connection layer 5A. A residual region 5B of the second semiconductor region 5, located between the connection layer 5A and the substrate 1, thus projects laterally beyond the structured semiconductor layer sequence. The connection layer 5A is preferably a highly doped semiconductor layer of the second semiconductor region 5. In particular, the connection layer 5A can have the highest doping concentration in the semiconductor layer sequence 2.The structured semiconductor layer sequence has a mesa shape whose vertical extent or height is identical to the etch depth T. In cross-section, the structured semiconductor layer sequence has a shape that widens from the first semiconductor region 3 to the second semiconductor region 5.

[0060] Fig. Figure 6 shows a further possible process step in which the mirror layer 6 and the contact layer 7 are provided with an opening 10. Preferably, the contact layer 7 is first opened, for example by wet chemical means using HCl. Subsequently, the opening in the mirror layer 6 can be created by means of the opening in the contact layer 7, for example also by wet chemical means. Alternatively, this step can be omitted. This means that the mirror layer 6 and the contact layer 7 can be formed without interruption.

[0061] Fig. Figure 7 shows a further process step in which a composite consisting of the substrate 1, the semiconductor layer sequence 2, and further layers 6, 7, 9 arranged on the semiconductor layer sequence 2 is provided with an encapsulation 11. In particular, an outer surface of the composite is covered with the encapsulation 11. Preferably, weakly conductive or insulating materials such as SiO2 are used for the encapsulation 11. The encapsulation 11 can be applied by means of the aforementioned atomic layer deposition.

[0062] Fig. Figure 8 shows a further process step in which another reflective layer 12 is applied to the encapsulation 11. The reflective layer 12 can first be applied over its entire surface to a surface of the encapsulation 11 facing away from the semiconductor layer sequence 2, so that it completely covers the surface. For example, the reflective layer 12 can be sputtered on. Metals such as aluminum or rhrhodium are particularly suitable materials for the reflective layer 12. Subsequently, the reflective layer 12 can be structured so that it only covers certain areas of the surface. The structuring, i.e., the selective removal of the reflective layer 12, can be carried out, for example, using wet chemical methods. Phosphoric acid (H3PO4) can be used as an etching agent.

[0063] Preferably, at least one opening 13 is created in the mirror layer 12, which is arranged vertically downstream of the contact layer 7 from the semiconductor layer sequence 2. The opening 13 later serves to connect the contact layer 7. In particular, as shown, two further openings 13 are created. Alternatively, a frame-shaped recess can be formed, which has a cross-sectional shape corresponding to the openings 13.

[0064] Fig. Figure 9 shows a further process step in which the composite is provided with a planarization layer 14. In particular, the material of the planarization layer 14 is first applied to an outer surface of the composite facing away from the substrate 1. The planarization layer 14 is formed such that it covers side surfaces 222 of the first and second semiconductor regions 3, 5, respectively, and fills the at least one opening 13 of the further mirror layer 12. Furthermore, the planarization layer 14 preferably covers the remaining area 5B of the second semiconductor region 5 and is laterally flush with it. Preferably, weakly conductive or insulating materials such as SiO2 are used for the planarization layer 14. By means of the planarization layer 14, the composite consisting of substrate 1, semiconductor layer sequence 2, and the further layers 6, 7, 9, 11, 12, 14 has a rectangular cross-sectional shape.

[0065] Fig. Figure 10 shows a further process step in which an insulating layer 15 is arranged on an outer surface of the composite. Preferably, electrically insulating materials such as SiO2 are used for the insulating layer 15. Advantageously, the insulating layer 15 covers the remaining exposed areas of the mirror layer 12. By means of the encapsulation 11, the planarization 14, and the insulating layer 15, the mirror layer 12 is preferably embedded in electrically insulating material. Thus, the mirror layer 12 is electrically insulated.

[0066] Fig. Figure 11 shows a further process step in which a further opening 16 is created through the at least one opening 13 of the further mirror layer 12. This further opening 16 has a smaller diameter than the existing opening 13 and extends through all layers 11, 14, 15 to the contact layer 7. For example, the further opening 16 can be created using a dry etching process such as reactive ion etching. In particular, fluorine is used as the etchant. Preferably, as shown, two further openings 16 are created. Alternatively, a frame-shaped recess can be formed, which has a cross-sectional shape corresponding to the openings 16.

[0067] Fig. Figure 12 shows a further process step in which a contact element 17 is formed in the at least one further opening 16. The contact element 17 is preferably formed from at least one electrically conductive material, in particular from a metal or a metal compound. For example, rh and nickel, or instead of nickel, a nickel alloy such as NiSn, can be used for the contact element 17. Furthermore, a support 18 is applied to a side of the composite facing away from the substrate 1. The support 18 preferably contains a material with comparatively high thermal conductivity. For example, silicon is suitable as a material for the support 18.

[0068] Fig. Figure 13 shows a further process step in which the substrate 1 is removed. For example, the substrate 1 can be removed from the semiconductor layer sequence 2 by means of laser lift-off.

[0069] The Fig. Figures 14 to 17 show further process steps of a method according to a first embodiment.

[0070] At the in Fig. In the process step shown in Figure 14, the second semiconductor region 5 is thinned down to a lower edge of the connection layer 5A. The remaining region 5B is thus completely removed. Preferably, the remaining region 5B of the second semiconductor region 5 is removed by means of a dry etching process such as reactive ion etching.

[0071] Fig. Figure 15 shows a further process step in which a passivation layer 19 is applied to the outer surface of the composite facing away from the support 18. The passivation layer 19 is advantageously formed from a weakly or non-conductive material such as SiO2. It can be produced by atomic layer deposition.

[0072] Fig. Figure 16 shows a further process step in which the passivation 19 is opened in a central area. This can be done using dry or wet chemical methods. A connection element 20 is formed in the opening thus created. Transparent, electrically conductive oxides are particularly suitable materials for the connection element 20.

[0073] Fig. Figure 17 shows a further process step in which a coupling structure 21 is arranged on the connection layer 5A or passivation 19. In particular, the coupling structure 21 is formed from a low-absorbing material such as TiO2 or Nb2O5. First, the material for the coupling structure 21 can be applied in a homogeneous layer and then provided with protrusions and depressions, resulting in the desired coupling structure 21.

[0074] Fig. Figure 17 shows an optoelectronic semiconductor chip 23, which has a semiconductor body 22 with a first semiconductor region 3, a second semiconductor region 5 and an active zone 4 arranged between the first and second semiconductor regions 3, 5. Furthermore, the optoelectronic semiconductor chip 23 includes an electrically conductive contact layer 7, which is arranged on a side of the first semiconductor region 3 facing away from the second semiconductor region 5.Furthermore, the optoelectronic semiconductor chip 23 comprises an electrically conductive mirror layer 6, which is arranged between the first semiconductor region 3 and the electrically conductive contact layer 7 and is laterally overlaid by the first semiconductor region 3 and the electrically conductive contact layer 7, so that there is a space 8 between the first semiconductor region 3 and the electrically conductive contact layer 7, in which a protective layer 9 is arranged to protect the mirror layer, the electrically conductive contact layer 7 extending laterally to an edge of the first semiconductor region 3.

[0075] The optoelectronic semiconductor chip 23 has a further mirror layer 12, which is arranged on a side of the electrically conductive contact layer 7 facing away from the semiconductor body 22, wherein the further mirror layer 12 extends laterally beyond the contact layer 7 and covers side surfaces 222 of the semiconductor body 23.

[0076] Furthermore, the optoelectronic semiconductor chip 23 has at least one contact element 17 or a contact frame for electrical contacting the contact layer 7, wherein the contact element 17 is arranged in an opening 13 of the further mirror layer 12.

[0077] Although the semiconductor body 22 has a cross-sectional shape that widens from the first semiconductor region 3 to the second semiconductor region 5, the semiconductor chip 23 nevertheless has a rectangular cross-sectional shape. This can be achieved by means of the planarization 14, which laterally surrounds the semiconductor body 22, the mirror layer 12, and the contact layer 7.

[0078] The second semiconductor region 5 comprises a connection layer 5A, which has the highest doping concentration in the semiconductor body 22. The connection layer 5A delimits the semiconductor body 22 on the side of the second semiconductor region 5 facing away from the first semiconductor region 3.

[0079] During operation, a large proportion of the radiation generated in the active zone 4 preferably exits at a radiation exit side of the semiconductor chip 23, which is located on a side of the second semiconductor area 5 facing away from the first semiconductor area 3. The output coupling structure 21, which improves the radiation extraction from the semiconductor body 22, is located at the radiation exit side.

[0080] In the optoelectronic semiconductor chip 23, the substrate is detached. It is therefore a thin-film chip. The lateral dimensions of the semiconductor chip 23 are determined primarily by the substrate or support and are at most L = 150 µm.

[0081] In connection with the Fig. Figures 1 to 13 and 18 to 20 describe a method according to a second embodiment. Here, the output coupling structure 21 is produced by structuring the second semiconductor region 5, in particular the remaining region 5B (see Figures 1 to 13 and 18 to 20). Fig. 18). For example, the second semiconductor region 5 or the remaining region 5B is roughened. This can be done using a dry etching process such as reactive ion etching. Subsequently, a passivation 24 and encapsulation 25 can be applied, covering the composite on a side facing away from the support 18 (compare Fig. 19). For example, the passivation 24 can be formed from Al2O3 by atomic layer deposition. The encapsulation can be formed from SiO2 by vapor deposition. The passivation 24 and encapsulation 25 can be opened in a central area. This can be done using dry or wet chemical processes. A connection element 20 is formed in the opening thus created (compare Fig. 20). For the connecting element 20, transparent electrically conductive oxides are particularly suitable as materials.

[0082] Fig. Figure 20 also shows an optoelectronic semiconductor chip 23. This is similar to the one in connection with Fig. The semiconductor chip described in 17 differs, however, with regard to the coupling structure 21 as in connection with the Fig. 18 and Fig. 19 has already been described. Reference symbol list 1 substrate 2 Semiconductor layer sequence 3 first semiconductor area 4 active zones 5 second semiconductor area 5A connection layer 5B Remaining area of ​​the second semiconductor region 6, 12 Mirror layer 7 Contact layer 8 spaces 9 Protective layer 10, 13, 16 Opening 11, 25 Encapsulation 14 Planarization 15 Insulation layer 17 Contact element 18 carriers 19, 24 Passivation 20 connection element 21 Coupling structure 22 Semiconductor bodies 23 Optoelectronic semiconductor chip 222 side surface d lateral dimension T Etching depth V vertical direction L lateral dimension

Claims

[1] Optoelectronic semiconductor chip (23) with - a semiconductor body (22) comprising a first semiconductor region (3), a second semiconductor region (5) and an active zone (4) arranged between the first and second semiconductor regions (3, 5), - an electrically conductive contact layer (7) arranged on a side of the first semiconductor region (3) facing away from the second semiconductor region (5), - an electrically conductive mirror layer (6) which is arranged between the first semiconductor region (3) and the electrically conductive contact layer (7) and is laterally projected over at the edge by the first semiconductor region (3) and the electrically conductive contact layer (7), so that there is an intermediate space (8) between the first semiconductor region (3) and the electrically conductive contact layer (7), in which intermediate space a protective layer (9) is arranged to protect the mirror layer (6), wherein - the electrically conductive contact layer (7) extends laterally to an edge of the first semiconductor region (3), - the electrically conductive contact layer (7) consists of Ni, and - a connecting layer formed from a transparent electrically conductive oxide is arranged between the electrically conductive mirror layer (6) and the electrically conductive contact layer (7). [2] Optoelectronic semiconductor chip (23) according to the preceding claim, wherein the electrically conductive mirror layer (6) contains Ag or consists of Ag. [3] Optoelectronic semiconductor chip (23) according to one of the preceding claims, wherein the protective layer (9) at least partially fills the intermediate space (8) and does not protrude laterally beyond the contact layer (7). [4] Optoelectronic semiconductor chip (23) according to one of the preceding claims, wherein the protective layer (9) is formed from an electrically weakly conductive or insulating material and / or contains one of the materials SiO2, Al2O3. [5] Optoelectronic semiconductor chip (23) according to one of the preceding claims, which has a further mirror layer (12) which is arranged on a side of the electrically conductive contact layer (7) facing away from the semiconductor body (22), wherein the further mirror layer (12) extends laterally beyond the electrically conductive contact layer (7) and covers at least one side surface (222) of the semiconductor body (22). [6] Optoelectronic semiconductor chip (23) according to the preceding claim, which has at least one contact element (17) for electrically contacting the electrically conductive contact layer (7), wherein the contact element (17) is arranged in an opening (13) of the further mirror layer (12). [7] Optoelectronic semiconductor chip (23) according to one of the preceding claims, in which a planarization (14) laterally surrounds the semiconductor body (22), the electrically conductive mirror layer (6) and the electrically conductive contact layer (7). [8] Optoelectronic semiconductor chip (23) according to one of the preceding claims, wherein the semiconductor body (22) has a shape in cross section which widens from the first semiconductor region (3) to the second semiconductor region (5). [9] Optoelectronic semiconductor chip (23) according to one of the preceding claims, wherein the second semiconductor region (5) has a connection layer (5A) which delimits the semiconductor body (22) on its side of the second semiconductor region (5) facing away from the first semiconductor region (3) and has a highest doping in the semiconductor body (22). [10] Method for producing an optoelectronic semiconductor chip (23) comprising the following steps: - Providing a substrate (1), - applying a semiconductor layer sequence (2) comprising a first semiconductor region (3), an active zone (4) on a side of the first semiconductor region (3) facing the substrate (1) and a second semiconductor region (5) on a side of the active zone (4) facing away from the first semiconductor region (3), - applying an electrically conductive mirror layer (6) and an electrically conductive contact layer (7) to the first semiconductor region (3), wherein the electrically conductive mirror layer (6) is arranged between the first semiconductor region (3) and the electrically conductive contact layer (7), - Structuring of the electrically conductive contact layer (7), - Structuring the electrically conductive mirror layer (6) by means of the structured electrically conductive contact layer (7), wherein a hollow groove is formed in the electrically conductive mirror layer (6) so that the mirror layer (6) projects laterally beyond the edge of the first semiconductor region (3) and the electrically conductive contact layer (7) and a gap (8) is formed between the first semiconductor region (3) and the electrically conductive contact layer (7), - Structuring the semiconductor layer sequence (2) by means of the structured electrically conductive contact layer (7). [11] Method according to the preceding claim, wherein the electrically conductive contact layer (7) is formed from Ni. [12] Method according to one of the preceding claims, wherein the electrically conductive mirror layer (6) is formed from Ag. [13] Method according to one of the preceding claims, wherein the second semiconductor region (5) has a connection layer (5A), and a structuring of the second semiconductor region (5) takes place up to a lower edge of the connection layer (5A). [14] Method according to one of the preceding claims, wherein a protective layer (9) is arranged in the intermediate space (8) to protect the electrically conductive mirror layer (6). [15] Method according to one of the preceding claims, wherein a connecting layer formed from a transparent electrically conductive oxide is arranged between the electrically conductive mirror layer (6) and the electrically conductive contact layer (7).

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