Systems and methods for qubit state readout field

Abstract

A method of reading out a state of a flux qubit in a quantum processor after performing a computation on the quantum processor with the flux qubit in an energy basis resulting in a final state of the flux qubit in the energy basis is discussed. A flux bias is applied to the body loop of the flux qubit to transform the final state of the flux qubit from the energy basis to the flux basis. A control signal is applied to latch the final state of the flux qubit, and the final state of the flux qubit is copied to a shift register. The final state of the flux qubit is transmitted through the shift register off the quantum processor.

Description

[0001] SYSTEMS AND METHODS FOR QUBIT STATE READOUT FIELD

[0002] This disclosure generally relates to quantum computing, and in particular, to systems and methods for readout of flux qubit states after quantum computation.

[0003] CROSS-REFERENCE TO RELATED APPLICATION

[0004] This patent application claims priority of U.S. Patent Application No. 63 / 448,537, filed on February 27, 2023, the entire disclosure of which is hereby incorporated by reference herein for all purposes.

[0005] BACKGROUND

[0006] Quantum Computation

[0007] A quantum computer is a system that makes direct use of at least one quantummechanical phenomenon, such as superposition, tunneling, and entanglement, to perform operations on data. The elements of a quantum computer are qubits. Quantum computers can provide speedup for certain classes of computational problems such as computational problems simulating quantum physics.

[0008] Hybrid Computing System Comprising a Quantum Processor

[0009] A hybrid computing system can include a digital computer communicatively coupled to an analog computer. In some implementations, the analog computer is a quantum computer, and the digital computer is also referred to as a classical computer.

[0010] The digital computer can include a digital processor that can be used to perform classical digital processing tasks described in the present systems and methods. The digital computer can include at least one system memory which can be used to store various sets of computer- or processor-readable instructions, application programs and / or data.

[0011] The quantum computer can include a quantum processor that includes programmable elements such as qubits, couplers, and other devices. The qubits can be read out via a readout system, and the results communicated to the digital computer. The qubits and the couplers can be controlled by a qubit control system and a coupler control system, respectively. In some implementations, the qubit and the coupler control systems can be used to implement quantum annealing on the analog computer.

[0012] Quantum Processor

[0013] A quantum processor may take the form of a superconducting quantum processor. A superconducting quantum processor may include a number of superconducting qubits and associated local bias devices. A superconducting quantum processor may also include couplers (also known as coupling devices) that selectively provide communicative coupling between qubits.

[0014] The foregoing examples of the related art and limitations related thereto are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.

[0015] BRIEF SUMMARY

[0016] According to an aspect, there is provided a method of reading out a state of a flux qubit in a quantum processor after performing a computation using the quantum processor with the flux qubit in an energy basis, the computation resulting in a final state of the flux qubit in the energy basis, the flux qubit comprising a body loop interrupted by a compound Josephson junction (CJJ), the method comprising: applying a flux bias to the body loop of the flux qubit to transform the final state of the flux qubit from the energy basis to a flux basis, applying a first control signal to latch the final state of the flux qubit in the flux basis, copying the final state of the flux qubit in the flux basis to a shift register, and transmitting the final state of the flux qubit through the shift register and off of the quantum processor.

[0017] According to other aspects, applying a first control signal to latch the final state of the flux qubit in the flux basis may comprise applying the first control signal to the CJJ of the flux qubit, copying the final state of the flux qubit in the flux basis to a shift register may comprise applying a second control signal to raise a tunnel barrier of a CJJ of a first stage of the shift register, the method may further comprise, after transmitting the final state of the flux qubit through the shift register and off of the quantum processor: removing the flux bias from the body loop of the flux qubit, removing the first control signal from the CJJ of the flux qubit, and removing the second control signal latching the state of the first stage of the shift register, applying a first control signal to latch the final state of the flux qubit in the flux basis may comprise applying a first control signal through an analog line, applying a first control signal to latch the final state of the flux qubit may comprise applying a first control signal by a control device on the quantum processor, copying the final state of the flux qubit in the flux basis to a shift register may comprise copying the final state of the flux qubit in the flux basis to a shift register via a latching quantum flux parametron (QFP), the latching QFP at least one of magnetically and galvanically coupled to the flux qubit, applying a first control signal to latch the final state of the flux qubit in the flux basis may comprise applying a first control signal to a CJJ of the latching QFP, copying the final state of the flux qubit in the flux basis to a shift register may comprise applying a second control signal to raise a tunnel barrier of a first stage of the shift register, and the method may further comprise, after transmitting the final state of the flux qubit through the shift register and off of the quantum processor: removing the flux bias from the body loop of the flux qubit, removing the first control signal latching the state of the latching QFP, and removing the second control signal latching the state of the first stage of the shift register.

[0018] According to an aspect, there is provided a method of solving a computational problem on a hybrid computing system, the hybrid computing system comprising a digital processor in communication with a quantum processor, the quantum processor comprising a flux qubit comprising a body loop interrupted by a compound Josephson junction (CJJ), the method comprising: applying one or more programming control signals to the flux qubit by the digital processor to program the quantum processor based on the computational problem, the flux qubit being programmed in an energy basis, instructing the quantum processor to evolve to a processor final state by the digital processor, the processor final state comprising the flux qubit in a qubit final state in the energy basis, applying a first control signal by one of the digital processor and the quantum processor to transmit a flux bias to the body loop of the flux qubit to transform the qubit final state of the flux qubit from the energy basis to a flux basis, applying a second control signal by one of the digital processor and the quantum processor to latch the qubit final state of the flux qubit, applying a third control signal by one of the digital processor and the quantum processor to copy the qubit final state of the flux qubit to a shift register, applying one or more fourth control signals by one of the digital processor and the quantum processor to transmit the qubit final state of the flux qubit through the shift register, and receiving the qubit final state by the digital processor.

[0019] According to other aspects, applying a third control signal by one of the digital processor and the quantum processor to copy the qubit final state of the flux qubit to a shift register may comprise applying a third control signal by one of the digital processor and the quantum processor to copy the qubit final state of the flux qubit to a shift register via a latching quantum flux parametron (QFP), the latching QFP at least one of magnetically and galvanically coupled to the flux qubit, applying a second control signal by one of the digital processor and the quantum processor to latch the qubit final state of the flux qubit may comprise applying a second control signal by one of the digital processor and the quantum processor to the CJJ of the flux qubit, applying a third control signal by one of the digital processor and the quantum processor to copy the qubit final state of the flux qubit to a shift register may comprise applying a third control signal by one of the digital processor and the quantum processor to raise a tunnel barrier of a first stage of the shift register, the method may further comprise: removing the first control signal by one of the digital processor and the quantum processor from the body loop of the flux qubit, removing the second control signal by one of the digital processor and the quantum processor latching the qubit final state of the flux qubit, and removing the third control signal latching the qubit final state of a first stage of the shift register, applying a second control signal by one of the digital processor and the quantum processor to latch the qubit final state of the flux qubit may comprise applying a second control signal by one of the digital processor and the quantum processor to a CJJ of a latching QFP coupled to the flux qubit, applying a third control signal by one of the digital processor and the quantum processor to copy the qubit final state of the flux qubit to a shift register may comprise applying a third control signal by one of the digital processor and the quantum processor to raise a tunnel barrier of a first stage of the shift register, the method may further comprise removing the first control signal by one of the digital processor and the quantum processor, removing the second control signal by one of the digital processor and the quantum processor, and removing the third control signal by one of the digital processor and the quantum processor, applying a second control signal to latch the qubit final state of the flux qubit may comprise applying a second control signal through an analog line, applying a second control signal to latch the qubit final state of the flux qubit may comprise instructing an on-chip control device to apply a second control signal, and applying one or more programming control signals to the flux qubit by the digital processor to program the quantum processor based on the computational problem may comprise applying one or more programming control signals to the flux qubit by the digital processor to program the quantum processor based on a surface code problem.

[0020] In other aspects, the features described above may be combined together in any reasonable combination as will be recognized by those skilled in the art.

[0021] BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

[0022] In the drawings, identical reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles are not necessarily drawn to scale, and some of these elements may be arbitrarily enlarged and positioned to improve drawing legibility. Further, the particular shapes of the elements as drawn, are not necessarily intended to convey any information regarding the actual shape of the particular elements, and may have been solely selected for ease of recognition in the drawings.

[0023] Figure 1 is a schematic diagram of a hybrid computing system including a digital computer coupled to an analog computer, in accordance with the present systems, devices, and methods.

[0024] Figure 2 is a schematic diagram of an example flux qubit that can be employed in accordance with the present systems, devices, and methods.

[0025] Figure 3 is a graph of a qubit potential energy landscape showing an example of tilting of the qubit potential in accordance with the present systems, devices, and methods. Figure 4A and Figure 4B are graphs of qubit potential energy landscapes showing an example of latching of the qubit potential in accordance with the present systems, devices, and methods.

[0026] Figure 5 is a schematic diagram of an example circuit for reading out a qubit in accordance with the present systems, devices, and methods.

[0027] Figure 6 is a flowchart of an example method for reading out a state of a flux qubit in a quantum processor that can be employed in accordance with the present systems, devices, and methods.

[0028] Figure 7 is an example graph of an instantaneous eigenspectrum versus time for tilting and latching by raising the qubit's barrier in accordance with the present systems, devices, and methods.

[0029] Figure 8 is an example graph of instantaneous eigenspectrum versus time for tilting and latching by raising the QFP's barrier for a coupled qubit and QFP system in accordance with the present systems, devices, and methods.

[0030] Figure 9 is an example graph of an instantaneous eigenspectrum versus time for reading and resetting the qubit in accordance with the present systems, devices, and methods.

[0031] Figure 10 is a flowchart of an example method for solving a computational problem on a hybrid computing system that can be employed in accordance with the present systems, devices, and methods.

[0032] DETAILED DESCRIPTION

[0033] In the following description, certain specific details are set forth in order to provide a thorough understanding of various disclosed implementations. However, one skilled in the relevant art will recognize that implementations may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well- known structures associated with computer systems, server computers, and / or communications networks have not been shown or described in detail to avoid unnecessarily obscuring descriptions of the implementations.

[0034] Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprising” is synonymous with “including,” and is inclusive or open-ended (i.e., does not exclude additional, unrecited elements or method acts).

[0035] Reference throughout this specification to “one implementation” or “an implementation” means that a particular feature, structure, or characteristic described in connection with the implementation is included in at least one implementation. Thus, the appearances of the phrases “in one implementation” or “in an implementation” in various places throughout this specification are not necessarily all referring to the same implementation. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more implementations.

[0036] As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its sense including “and / or” unless the context clearly dictates otherwise.

[0037] The headings and Abstract of the Disclosure provided herein are for convenience only and do not interpret the scope or meaning of the implementations.

[0038] Figure 1 illustrates a computing system 100 comprising a digital computer 102. The example digital computer 102 includes one or more digital processors 106 that may be used to perform classical digital processing tasks. Digital computer 102 may further include at least one system memory 122, and at least one system bus 120 that couples various system components, including system memory 122 to digital processor(s) 106. System memory 122 may store one or more sets of processor-executable instructions, which may be referred to as modules 124.

[0039] The digital processor(s) 106 may be any logic processing unit or circuitry (for example, integrated circuits), such as one or more central processing units ("CPUs"), graphics processing units ("GPUs"), digital signal processors ("DSPs"), application-specific integrated circuits ("ASICs"), programmable gate arrays ("FPGAs"), programmable logic controllers (“PUCs”), etc., and / or combinations of the same.

[0040] In some implementations, computing system 100 comprises an analog computer 104, which may include one or more quantum processors 126. Quantum processor 126 may include at least one superconducting integrated circuit. Digital computer 102 may communicate with analog computer 104 via, for instance, a controller 118. Certain computations may be performed by analog computer 104 at the instruction of digital computer 102, as described in greater detail herein. As computing system 100 comprises a digital computer 102 and an analog computer 104, the computing system 100 can be referred to as a hybrid computing system.

[0041] Digital computer 102 may include a user input / output subsystem 108. In some implementations, the user input / output subsystem includes one or more user input / output components such as a display 110, a mouse 112, and / or a keyboard 114.

[0042] System bus 120 may employ any known bus structures or architectures, including a memory bus with a memory controller, a peripheral bus, and a local bus. System memory 122 may include non-volatile memory, such as read-only memory ("ROM"), static random-access memory (“SRAM”), Flash NAND; and volatile memory such as random-access memory ("RAM") (not shown).

[0043] Digital computer 102 may also include other non-transitory computer- or processor- readable storage media or non-volatile memory 116. Non-volatile memory 116 may take a variety of forms, including: a hard disk drive for reading from and writing to a hard disk (for example, a magnetic disk), an optical disk drive for reading from and writing to removable optical disks, and / or a solid state drive (SSD) for reading from and writing to solid state media (for example NAND-based Flash memory). Non-volatile memory 116 may communicate with digital processor(s) via system bus 120 and may include appropriate interfaces or controllers 118 coupled to system bus 120. Non-volatile memory 116 may serve as long-term storage for processor- or computer-readable instructions, data structures, or other data (sometimes called program modules or modules 124) for digital computer 102.

[0044] Although digital computer 102 has been described as employing hard disks, optical disks and / or solid-state storage media, those skilled in the relevant art will appreciate that other types of nontransitory and non-volatile computer-readable media may be employed. Those skilled in the relevant art will appreciate that some computer architectures employ nontransitory volatile memory and nontransitory non-volatile memory. For example, data in volatile memory may be cached to non-volatile memory or a solid-state disk that employs integrated circuits to provide non-volatile memory.

[0045] Various processor- or computer-readable and / or executable instructions, data structures, or other data may be stored in system memory 122. For example, system memory 122 may store instructions for communicating with remote clients and scheduling use of resources including resources on the digital computer 102 and analog computer 104. Also, for example, system memory 122 may store at least one of processor executable instructions or data that, when executed by at least one processor, causes the at least one processor to execute the various algorithms to execute instructions. In some implementations system memory 122 may store processor- or computer-readable calculation instructions and / or data to perform pre-processing, co-processing, and post-processing to analog computer 104. System memory 122 may store a set of analog computer interface instructions to interact with analog computer 104. For example, the system memory 122 may store processor- or computer-readable instructions, data structures, or other data which, when executed by a processor or computer causes the processor(s) or computer(s) to execute one, more or all of the acts of method 600 of Figure 6.

[0046] Analog computer 104 may include at least one analog processor such as quantum processor 126. Analog computer 104 may be provided in an isolated environment, for example, in an isolated environment that shields the internal elements of the quantum computer from heat, magnetic field, and other external noise. The isolated environment may include a refrigerator, for instance a dilution refrigerator, operable to cryogenically cool the analog processor, for example to temperature below approximately 1 K.

[0047] Analog computer 104 may include programmable elements such as qubits, couplers, and other devices (also referred to herein as controllable devices). Qubits may be read out via on chip readout and readout control system 128. Readout results may be sent to other computer- or processor-readable instructions of digital computer 102. Qubits may be controlled via a qubit control system 130. Qubit control system 130 may include on-chip Digital to Analog Converters (DACs) and analog lines that are operable to apply a bias to a target device. Couplers that couple qubits may be controlled via a coupler control system 132. Coupler control system 132 may include tuning elements such as on-chip DACs and analog lines. Qubit control system 130 and coupler control system 132 may be used to implement a quantum annealing schedule as described herein on quantum processor 126. Programmable elements may be included in quantum processor 126 in the form of an integrated circuit. Qubits and couplers may be positioned in layers of the integrated circuit that comprise a first material. Other devices, such as readout control system 128, may be positioned in other layers of the integrated circuit that comprise a second material. In accordance with the present disclosure, a quantum processor, such as quantum processor 126, may be designed to perform quantum annealing and / or adiabatic quantum computation or may be designed to perform gate or circuit model quantum computation. Example implementations of quantum processors are described in U.S. Patent No. 7,533,068 and U.S. Provisional Patent Application No. 63 / 356,663.

[0048] Figure 2 is a schematic diagram of an example implementation of a superconducting qubit 200 that can be employed in accordance with the present systems, devices, and methods. In some implementations, quantum processor 126 of computing system 100 can include a plurality of superconducting qubits 200. In Figure 2, solid lines represent superconducting metal and crosses (X) represent Josephson junctions (see, for example, U.S. Patent No. 9,768,371). Superconducting qubit 200 comprises a Josephson junction structure 201 with Josephson junctions 204 and 205 and a superconducting loop 203 with an inductor 202. A superconducting material refers to a material having a critical temperature at and below which that superconducting material exhibits superconducting behavior. Examples of superconducting metals include aluminum, niobium, and tantalum. A superconducting order parameter phase difference (p exists across Josephson junction structure 201, as discussed below with respect to Figures 3, 4A, and 4B. Josephson junction structure 201 can include a single Josephson junction, a pair of Josephson junctions as illustrated herein, or other possible combinations of Josephson junctions in series or parallel. The parallel combination of two Josephson junctions is known as a compound Josephson junction (CJJ) (see, for example, U.S. Patent No. 8,536,566). Qubits having layouts with the inductor connected in parallel with the Josephson junction structure, are generally known as flux qubits (see, for example, U.S. Patent No. 8,536,566, International Patent Application No. PCT / US2022 / 37457).

[0049] Variants of the flux qubit include the fluxonium qubit, which is characterized by a very large body inductance created by a series connection of multiple large Josephson junctions. For a discussion of fluxonium qubits see Manucharyan, Vladimir E., et al. Fluxonium: Single cooperpair circuit free of charge offsets, Science 326.5949 (2009): 113-116 and U.S. Provisional Patent Application No. 63 / 223,686. Alternatively, a fluxonium-like qubit possessing a very large body inductance can be formed by using superconducting wire made from a kinetic inductor such as: Niobium Nitride (NbN), Niobium Titanium Nitride (NbTiN), or Titanium Nitride (TiN) (see, for example, International Patent Application No. PCT / US2022 / 37457). As used herein, the term flux qubit encompasses any superconducting qubits formed by connecting an inductance in parallel with a Josephson junction structure as illustrated in Figure 2.

[0050] Current flowing through a metal material in principle stores energy both in the magnetic field of that metal and in the kinetic energy of the charge carriers (e.g., the electrons or Cooper pairs). In non-superconducting metals, the charge carriers collide frequently with the lattice and lose their kinetic energy as Joule heating. This is also referred to as scattering, and quickly releases energy. However, in superconducting materials, scattering is substantially reduced, as the charge carriers are Cooper pairs which are protected against dissipation through scattering, which allows for superconducting materials to store energy in the form of kinetic inductance. This phenomenon allows kinetic inductance to efficiently store energy within the superconducting metal. Kinetic inductance is at least in part determined by the inertial mass of the charge carriers of a given material and increases as carrier density decreases. As the carrier density decreases, a smaller number of carriers must have a proportionally greater velocity in order to produce the same current. Materials that have high kinetic inductance for a given area (as defined below) are referred to as “kinetic inductors”, “kinetic inductance materials”, or “high kinetic inductance materials”.

[0051] Kinetic inductance materials are those that have a high normal-state resistivity and / or a small superconducting energy gap, resulting in a larger kinetic inductance per unit of area. In general, total inductance L of a superconducting material is given by L = LK+ LG, where LGis the geometric inductance and LKis the kinetic inductance. The kinetic inductance of a superconducting film in near-zero temperatures is proportional to the effective penetration depth eff . In particular, for a film with a given thickness t, the kinetic inductance of the film is proportional to the ratio of the length of the film L to the width of the film W . where length is in the direction of the current and width is orthogonal to length (note that both width and length are orthogonal to the dimension in which thickness is measured). That is, LI(~Ae^ for a superconducting film with a given thickness. The kinetic inductance fraction of a material is characterized as a = LgL+kL . A material considered to have high kinetic inductance would typically have a in the range of 0.1 < a < 1. Materials with less than 10% of the energy stored as kinetic inductance would be considered traditional magnetic storage inductors with a small correction.

[0052] Flux qubit 200 can be controlled by the application of magnetic flux through the closed inductive loop formed by inductor 202 in parallel with Josephson junction structure 201 (also referred to herein as the “qubit body” or “body loop”), represented as , and magnetic flux through the closed inductive loop formed by Josephson junction structure 201, represented as the equations below.

[0053] When discussing states of a flux qubit, two different representations of those states can be considered. Figure 3 is a graph 300 of an example energy landscape of a flux qubit. Graph 300 includes wavefunctions 302 and 304 of the two lowest energy states of the flux qubit as a function of superconducting phase drop <p across the Josephson junction structure (e.g., a CJJ) when the qubit is biased such that its potential energy landscape is a symmetric double-well 306. In some implementations, graph 300 can depict energy of flux qubit 200 as a function of superconducting phase drop across Josephson junction structure 201.

[0054] Graph 300 shows the energy landscape at a special value of . which is referred to as the degeneracy point. Quantum mechanical wavefunction 302 representing the lowest energy, or ground, state of the qubit |0) is a symmetric superposition of a pair of approximately Gaussian wavefunctions centered on the left well |0L) and the right well |0R) and is given by: |0) = | OR) + 10L) (without considering normalization of the wavefunctions). Wavefunction 304 representing an excited state of the qubit |1) is an antisymmetric superposition of those same approximately Gaussian wavefunctions and is given by: | 1) = | OR) — |0L) (without considering normalization of the wavefunctions). The set of states [|0), 11)] define the energy basis for the qubit.

[0055] The set of states [ 10L), | OR)] define the flux basis for the qubit. The states of the flux basis correspond to distinct magnetic moments that can be attributed to a dissipationless electrical current flowing across a closed loop of a flux qubit body formed, for example, by Josephson junction structure 201 in parallel with inductor 202 of flux qubit 200 in Figure 2. For example, 10L) can represent a macroscopic amount of magnetic flux threading the flux qubit body due to a counter-clockwise current flow and | OR) can represent a macroscopic amount of magnetic flux threading the flux qubit body due to a clockwise current flow.

[0056] Either the flux basis or the energy basis can be used when performing quantum computation, however the details of implementing a particular model of quantum computation will typically make one choice more advantageous in practice. For example, quantum annealing (QA) is a model of quantum computation that is suited for solving classical binary optimization problems that readily map onto the physics of the transverse field Ising model (Kadowaki, Tadashi, and Hidetoshi Nishimori, Quantum annealing in the transverse Ising model, Physical Review E 58.5 (1998): 5355). Within this model, qubits only access superposition states of the form a 10) + b 11), where a and b are real numbers. There is a natural mapping of QA onto the flux basis for flux qubits as described in Kaminsky, William M., and Seth Lloyd, Scalable architecture for adiabatic quantum computing of NP -hard problems, Quantum computing and quantum bits in mesoscopic systems (2004): 229-236. On the other hand, gate model quantum computation (GMQC) is suited for solving quantum mechanical problems, in which qubits access superposition states with complex coefficients a and b . Such states are more naturally encoded in the energy basis within a rotating frame of reference for flux qubits. The computation may, for example, be a 2D surface code computation as discussed in U.S. Provisional Patent Application Nos. 63 / 356663 and 63 / 390185, or other forms of gate model computations with flux qubits. Other models of quantum computation may likewise be more readily implemented in one basis versus the other. In the discussion below, it has been assumed that the quantum computation of interest is performed in the energy basis.

[0057] When performing computations with quantum processors, the states of qubits reflect the results of a computation or of some intermediate result such as an error-syndrome measurement in error-corrected quantum computing. A readout system is required to move information from the quantum processor to a digital computer or other user interface (also referred to as “off-chip”). In some implementations, a readout system can move state information of qubits, such as flux qubit 200, from quantum processor 126 to digital computer 102 based on signals provided by readout control system 128.

[0058] A first category of readout methods that is appropriate for reading out states of flux qubits in the energy basis is dispersive readout. To perform dispersive readout, a qubit is coupled to a resonator and the energy eigenstate occupied by the qubit influences the resonant frequency of the resonator in the low photon number limit. Dispersive readout may be used to read flux qubits in the energy basis as discussed, for example, in Wallraff, Andreas, et al. Strong coupling of a single photon to a superconducting qubit using circuit quantum electrodynamics, Nature 431.7005 (2004): 162-167 and Manucharyan, Vladimir E., et al. Fluxonium: Single cooper-pair circuit free of charge offsets, Science 326.5949 (2009): 113-116. Dispersive readout can provide high readout fidelity. However, dispersive readout is typically slow, and difficult to design, manufacture, and operate. Dispersive readout of a large-scale quantum processor would require many high bandwidth microwave transmission lines to achieve acceptable data rates. Use of high bandwidth microwave transmission lines may increase an amount of noise in the quantum processor and therefore decrease the fidelity of the computation. An alternative readout method that provides both high fidelity and high data rates with minimal bandwidth on the control lines would be beneficial. As discussed herein, a second category of readout methods appropriate for reading out states of flux qubits in the energy basis involves transferring information from the energy basis to the flux basis and then reading the state in the flux basis. Transfer of information from the energy basis to the flux basis is realized by applying a flux bias to the qubit body to alter or “tilt” the potential energy landscape. For an appropriate tilt amplitude and tilt rate, an approximate transform can be realized that changes 10) -> |0R) and |l) -> |0L). A small tilt amplitude can result in low readout fidelity, as the qubit states will have non-negligible probability in both wells, while a large tilt amplitude can transfer all probability into the lowest well regardless of an initial state of the qubit. A beneficial range of tilt amplitudes provide near-unity probability of transforming or projecting onto one of the flux bases for each of the qubit states, and can be determined based on qubit parameters and calibrated for individual quantum processors.

[0059] Figure 4A is an example implementation of a graph 400a of a qubit potential energy landscape after a tilt operation is performed. That is, a flux bias has been applied to change the energy landscape from what is shown in Figure 3 to what is shown in Figure 4A. Graph 400a includes a ground state 402a, a first excited state 404a, and a potential energy landscape 406a. After the tilt, the qubit state can be fully projected onto the easily distinguished states |0L) and | OR) in a process referred to as latching. In some implementations, a flux qubit can be latched by coupling the magnetic flux generated by the qubit in a flux basis state to a non-hysteretic direct current superconducting quantum interference device (DC SQUID) that is then interrogated using a classical electric current (see Chiorescu et al., Coherent Quantum Dynamics of a Superconducting Flux Qubit, arXiv:cond-mat / 0305461vl, May 20, 2002, and Ozfidan et al., Demonstration of nonstoquastic Hamiltonian in coupled superconducting flux qubits, arXiv: 1903.06139v3, Nov 8, 2019). Alternatively, latching can be realized by ramping a CJJ flux bias to raise the barrier within the potential energy landscape of the qubit to stop quantum tunneling.

[0060] Figure 4B is an example implementation of a graph 400b of a qubit potential energy landscape after such a latch operation. Graph 400b includes ground state 402b and first excited state 404b. In yet another implementation, discussed in further detail below, a latching quantum flux parametron (QFP) is magnetically (also referred to as inductively) and / or galvanically coupled to the qubit, and the CJJ flux bias of the latching QFP is ramped to stop the quantum tunneling of the coupled qubit and latching QFP system. In this implementation, the latching QFP possesses a final classical state in its own flux basis that can be passed to a superconducting QFP shift register, for example, as described in U.S. Patent No. 10,528,886. A QFP-based readout method is described in more detail below. Also described below is a reset method for the combined flux qubit and readout system. Figure 5 is a schematic diagram of an example circuit 500 having a flux qubit 502 and a QFP readout circuit 504. Example circuit 500 may be formed from one or more superconducting materials. Qubit 502 has a Josephson junction structure 506 interrupting a body loop 508. In the example implementation of Figure 5, Josephson junction structure 506 is a CJJ. However, in other implementations Josephson junction structure 506 may be a single Josephson junction or other combinations of Josephson junctions in series or in parallel. A first control line 510 is communicatively coupled to flux qubit 502 to apply a flux bias to Josephson junction structure 506, and a second control line 512 is communicatively coupled to flux qubit 502 to apply a flux bias to body loop 508. In some implementations, flux qubit 502 may be flux qubit 200 of Figure 2.

[0061] QFP readout circuit 504 has a latching QFP 514 coupled to a first shift register stage 516 of a QFP shift register. QFP shift registers for readout of quantum annealing processors are described in U.S. Patent No. 10,528,886. While similar principles to those discussed in the referenced patent apply herein to transfer data through the QFP shift register, different techniques are required for reading the state of a flux qubit in the energy basis and transferring that state into the QFP shift register, as will be discussed herein. Flux qubit 502 is inductively coupled to latching QFP 514 at interface 518. In some implementations, coupling between flux qubit 502 and latching QFP 514 at interface 518 may be entirely magnetic / inductive as shown, may be partially galvanic, or interface 518 may be replaced with an entirely galvanic coupling. Galvanic coupling may beneficially decrease the space and wiring used in coupling, but may, in some implementations, increase noise and / or crosstalk within a processor chip. Latching QFP 514 has a body loop 520 interrupted by a CJJ 522. CJJ 522 is communicatively coupled to a control line 524, which selectively transmits a signal to bias CJJ 522.

[0062] Latching QFP 514 is inductively coupled to first shift register stage 516 at an interface 526. First shift register stage 516 has a CJJ 528 communicatively coupled a control line 530, which selectively transmits a flux bias signal to bias CJJ 528. The QFP shift register of QFP readout circuit 504 can also include additional shift register stages coupled to first shift register stage 516 at 532.

[0063] It will be understood that the coupling structures shown in Figure 5, such as the inductors, may be distinct elements, or the coupling structures may be an undifferentiated portion of the wiring that acts as a distributed inductor.

[0064] In some implementations, latching of latching QFP 514 is a dynamic part of the readout process. A bias line 524 can provide a flux bias signal to body loop 520 that can be used to calibrate the bistable point of latching QFP 514, similar to the calibration of the operating point for the qubit provided by second control line 512 in communication with body loop 508. The flux bias signal may be provided by an off-chip control line or by an on-chip control device such as a flux bias DAC.

[0065] Figure 6 is a flowchart of an example method 600 to read out a state of a flux qubit in the energy basis that can be employed in accordance with the present systems, devices, and methods. Method 600 can, in some implementations, follow performance of a computation on a gate model quantum processor with the flux qubit in an energy basis resulting in a final state of the flux qubit in the energy basis. Method 600 can, for example, be used with example circuit 500 of Figure 5. In some implementations, method 600 may be executed on a hybrid computing system comprising at least one digital or classical processor and at least one quantum processor. For example, method 600 may be performed by computing system 100 of Figure 1. The digital or classical processor may provide control signals or instructions to the quantum processor to execute the method.

[0066] Method 600 comprises evenly numbered acts 602 to 608; however, a person skilled in the art will understand that the number of acts illustrated is an example, and, in some implementations, certain acts may be omitted, further acts may be added, and / or the order of the acts may be changed.

[0067] Method 600 starts, for example in response to a call or invocation from another routine. Method 600 will typically start after performing a computation on the quantum processor with a flux qubit in its energy basis.

[0068] At 602, a flux bias tilt is applied to the body loop of the flux qubit to transform a state of the qubit from the energy basis to the flux basis. In the example implementation of Figure 5, a flux bias tilt may be applied through control line 512 to body loop 508 of flux qubit 502. Details of flux bias tilt are discussed in further detail below with respect to Figure 7, Figure 8, and Figure 9.

[0069] At 604, a latching control signal is applied to latch the state of the flux qubit after the transformation from the energy basis to the flux basis. In some implementations, the latching control signal may be applied to the CJJ of the qubit. In the example implementation of Figure 5, the latching control signal may be applied through control line 510. In other implementations, the combined qubit-latching QFP system can be latched by applying a control signal through control line 524 to CJJ 522 of latching QFP 514. In some implementations, the latching of latching QFP 514 beneficially increases a latching speed of the state of the coupled qubit (i.e., flux qubit 502) and latching QFP system in comparison to a latching speed of the state of the flux qubit in isolation.

[0070] At 606, a final state of the flux qubit is copied to a shift register. In the example implementation of Figure 5, the final state is copied from latching QFP 514 to first shift register stage 516 of the QFP shift register, and then may be copied to additional stages at 532. Data representing qubit state information can be copied through the QFP shift register by applying signals to control lines coupled to CJJs, for example, control line 530 coupled to CJJ 528.

[0071] At 608, the final state is transmitted off the quantum processor. As used herein, transmitting off the quantum processor refers to transferring the data through signal lines beyond the quantum processor chip, to a device external to the quantum processor. In contrast, “on-chip” refers to devices that form part of the quantum processor. It will be understood that “on-chip” includes devices formed on physically distinct chips that are interconnected to form a quantum processor. The final state may, for example, be passed to a classical digital processor, where the result is displayed to a user. The final state may also be provided to an algorithm such as, for example, a classical post processing or error correction algorithm performed by the digital computer. Referring to Figure 1, the final state may be transmitted from a shift register located on-chip in quantum processor 126 through readout control system 128 and to digital computer 102.

[0072] After act 608, method 600 terminates, until it is, for example, invoked again. Method 600 may be performed simultaneously or nearly simultaneously for a plurality of qubits in a quantum processor, and may also be repeated iteratively to provide a plurality of solutions to a computation.

[0073] One or more of the control signals provided through control lines 510, 512, 524, and 530 to one of flux qubit 502 and QFP readout circuit 504 as discussed above with reference to Figure 5 and method 600 may be provided by an analog signal line, such as a microwave line. The analog line may be controlled by the digital processor and provide control signals from a device (e.g., controller 118 of Figure 1) at room temperature. In other implementations, one or more of the control signals provided through control lines 510, 512, 524, and 530 may be provided by an on-chip control device. For example, an on-chip control device may be a single flux quantum source such as the on-chip control device described in U.S. Patent Application Publication No. 2021 / 0248506, or the on-chip control device described in U.S. Provisional Patent Application No. 63 / 265605, in which a pulse source is described that could be used to apply the above described tilt signal (e.g., the signal through second control line 512) or the latch signal (e.g., the signal through one of control lines 510 and 524). As discussed in U.S. Provisional Patent Application No. 63 / 265605, the pulse source may be arranged to provide a relatively fast control pulse to a plurality of qubits simultaneously or substantially simultaneously. Such a pulse source could be used to tilt and / or latch all of the qubits on a quantum processor, or a subset thereof, simultaneously, or substantially simultaneously. In some implementations, an on-chip multiplexed set of pulse sources may be used to provide control signals to subsets of qubits at different times. In some implementations, control signals from a source located at room temperature, such as through analog control lines, might not provide sufficiently fast signals, or may increase the noise on the quantum processor. In these cases, it may be beneficial to provide on-chip control sources. The latching timescale used for latching readout may harness either diabatic or adiabatic evolution, and a range of timescales may be used.

[0074] Figure 7 is an example graph 700 showing an example calculation using flux qubit parameters consistent with a fluxonium-like device. Graph 700 plots the instantaneous energy spectrum of the qubit alone (measured in GHz) as a function of time (measured in ns), visualizing the tilt-and-latch readout procedure in the case of latching by ramping the tunnel barrier of the qubit. That is, Figure 7 provides the energy spectrum for a self-latching qubit that is not coupled to a latching QFP. The qubit starts at the degeneracy point at time t=0. Two lowest energy states 702 and 704 respectively correspond to |0) = 0L + OR and |1) = 0L - OR as illustrated in Figure 3. There are additional higher excited states, for example, state 706, separated from the qubit manifold by a large energy gap. These additional states can be written using higher-order flux bases [| IL), | jR)] where i > 1. The tilt is instantiated by a Gaussian-smoothed step-edge bias applied to the qubit body that ends at t= 4 ns, indicated by 708 on graph 700. At that point in time, the states |0) and 11) have smoothly transformed into | OR ) and |0L) respectively, at least approximately. The latch is instantiated by a Gaussian-smoothed step-edge bias applied to the CJJ of the qubit that ends at t=l 5 ns, indicated by 710 on graph 710. This smooth evolution ensures, or at least increases the likelihood, that the lowest lying states (702, 704) are transformed into | OR) and 10L) with certainty or at least high probability. The two lowest lying states (702, 704) are well separated from the higher excited states (706) throughout the evolution. Time domain simulations of the evolution depicted in Figure 7 have confirmed that a qubit initialized in |0) = \0L) + |0R) finishes in the state |0R) and that a qubit initialized in | 1) = \0L) — |0R) finishes in the state 10L) . The tilt and self-latching of the qubit can therefore be described as an adiabatic transformation from the energy basis at the degeneracy point to the flux basis.

[0075] Figure 8 is an example graph 800 showing an example tilt-and-latch readout procedure in the case of a qubit that is coupled to a latching QFP. Graph 800 plots the instantaneous energy spectrum of the coupled qubit and latching QFP system (in GHz) as a function of time (in ns) using realistic example device parameters. The coupled qubit and latching QFP system may be qubit 502 and latching QFP 514 of Figure 5. In graph 800, system states are labelled as product states of the form | qubit state > ® | latching QFP state >. Independent flux bases can be defined for both the qubit and latching QFP. At 802, corresponding with t=0, the qubit and latching QFP are decoupled, the qubit is at a degeneracy point, and the tunnel barrier of the latching QFP is suppressed. For this initial condition, the states of the system are strictly product states, that is, there is no entanglement between the states of the qubit and the latching QFP. The mutual inductance between the qubit and latching QFP is fully turned on at t=6 ns, indicated at 804. In this implementation, the energy spectrum only changes slightly with the activation of the coupling as the magnetic moment of the latching QFP is negligible when its tunnel barrier is suppressed, and therefore the interaction energy between the qubit and latching QFP is also negligible. Next, the tilt is instantiated by a Gaussian-smoothed step-edge bias applied to the qubit body that ends at t= 12 ns, indicated at 806. At that point in time, the states 10) ® 10) and | 1) ® |0) have smoothly transformed into | OR)® 10) and |0L)®|0), respectively, at least approximately. Finally, the latch is instantiated by a Gaussian-smoothed step-edge bias applied to the CJJ of the latching QFP that ends at t=24 ns. The lowest lying states map onto |0R)® |0L) and 107,)® | OR). In this implementation, the states of the qubit and latching QFP are anticorrelated due to the assumed antiferromagnetic coupling between those devices. Thus, reading the final state of the latching QFP provides equivalent information to reading the state of the qubit directly. In contrast with the qubit self-latching discussed with respect to Figure 7, the QFP latching of Figure 8 results in the near approach of higher excited states to the low energy manifold as the tunnel barrier of the QFP is raised. The point of closest approach is at t=21 ns (808). Time domain simulations of the evolution depicted in Figure 8 have confirmed that a system initialized in |0) ® |0) finishes in the state |0R)® |0L) with certainty and that the system initialized in |1) ® |0) finishes in the state |0L)® |0R) with high probability. However, there is also leakage into the second excited state 107?)® 107?) with a very small probability. This leakage is due to non-adiabatic passage through the point of minimum spectral gap at t=21 ns. This leakage channel does not necessarily constitute a readout error because the final state of the latching QFP is still anticorrelated with the initial state of the qubit.

[0076] Once the state of the qubit has been latched, the bit of qubit state information can be moved and / or copied to a readout device. Thereafter, the states of the qubit and the latching QFP can be reset. It can be beneficial to reduce the local energy dissipation in the region of the qubit as much as possible. In the example implementation described herein, the bit of qubit state information can be copied from the latching QFP to a first shift register stage (SRS). In the example of Figure 5, state information from latching QFP 514 can be copied to first shift register stage 516. Once the bit has been copied to the SRS, the qubit and latching QFP may be adiabatically reset. The reset procedure proceeds with the tilt bias being removed first, lowering the tunnel barrier of the QFP second, and lowering the first stage shift register tunnel barrier third. In implementations where the latch bias is applied directly to the qubit, the control signal can be removed from the CJJ of the flux qubit as a second act of the reset procedure.

[0077] Figure 9 is an example implementation of an instantaneous eigenspectrum (measured in GHz) versus time (measured in ns) for reading and resetting the qubit. Both an eigenspectrum graph 900 and an illustration 902 showing bit transmission of qubit state information are shown. In graph 900, states are labeled using the compact notation | qubit, QFP, SRS) . In illustration 902, solid dots indicate the presence of a bit and hollow dots represent devices that have been reset.

[0078] The evolution in Figure 9 begins at t=0 indicated at 904, with the qubit at a degeneracy point and the tunnel barriers suppressed in CJJs of both the latching QFP and the first SRS. As in graph 800 of Figure 8, the tilt is fully applied to the qubit at t= 12 ns, indicated at 906, and the QFP is latched at t=24 ns, indicated at 908. The first SRS is latched at t=36 ns, indicated at 910. As indicated in graph 900, |0, 0, 0) in the energy basis has been mapped to | OR, 0L, OR) in the flux basis and |1, 0, 0) in the energy basis has been mapped to 10L, OR, 0L) in the flux basis at 910. Moreover, as shown in illustration 902, the state of the qubit has been copied into all three devices at t=36 ns. The bit of information describing the state of the qubit can be copied to subsequent SRS in the same manner as described herein to move the datum an arbitrary distance away from the qubit. For the sake of simplicity, the sequence shown in Figure 9 has been limited to a single SRS. All of the actions between t=0 and t=36 ns can be considered as copy / move operations because there has been no erasing of information.

[0079] The act of resetting the system begins at t=39 ns, indicated by 912, by undoing the tilt- and-latch procedure in the same time ordering of events. The reset procedure begins with the removal of the tilt applied to the qubit. If the system was in either | OR, 0L, OR) or 10L, OR, 0L) at the beginning of the reset, then the system will be found in its ground state after removal of the tilt, which resets the state of the qubit. Removing the latching QFP tunnel barrier starting at t=45 ns, indicated at 914, brings two additional states into the low energy manifold, but those states do not hybridize with the degenerate ground state and therefore do not move the system out of the ground state. This resets the state of the latching QFP. Since the magnetic moment of the latching QFP has been suppressed, the latching QFP has decoupled from the first SRS, and the qubit is once again isolated from the readout circuit. The resultant low energy spectrum is identical to that found at t=0 except that it is doubly-degenerate due to the two degenerate flux bases of the first SRS.

[0080] Up to the lowering of the latching QFP tunnel barrier, there has been no erasure of information because a copy of the bit continues to exist in the first SRS. Lowering the tunnel barrier of the first SRS will result in erasure of qubit state information and will be accompanied by dissipation per Landauer’s principle. With that lowering of the tunnel barrier starting at t=57 ns, indicated at 916, a marked change occurs in the low energy eigenspectrum. In graph 900 a pair of small gap anticrossings are observed at t=58 ns, indicated at 918, due to the lifting of the degeneracy of the low energy manifold. If the system was in the state 10L, OR, 0L) prior to reset, then the system will make a non-adiabatic passage through these anticrossings. Subsequent to those anticrossings, the system will be found in the state |0, 0, 1) with nonzero probability. This state rises in energy rapidly with time. Eventually there will be a relaxation event |0, 0, 1) -> 10, 0, 0) that returns the entire system to the ground state. Provided there is a reservoir near the first SRS into which the first SRS can deposit a photon, then the energy dissipation will be localized away from the qubit. Those skilled in the art will appreciate that it is possible to construct a long chain of QFP shift register stages to adiabatically move the bit far from the qubit before erasure. In some implementations, energy dissipation by the last SRS could also be moved elsewhere by using feedback from the final measurement device to appropriately flux bias the final SRS as its tunnel barrier is suppressed.

[0081] In discussing the tilt-and-latch procedure illustrated in Figure 8, it was noted that a diabatic evolution from an initial state 11, 0) to a latched state | OR, OR) need not constitute a readout error. However, such a diabatic evolution could be problematic for reset, as illustrated by the location of the analogous state for the qubit-QFP-SRS system | OR, OR, 0L) at t=36 ns (910). Reaching this state would involve passing through multiple small gap anticrossings as the QFP and SRS tunnel barriers are raised. Additional small gap anticrossings will be encountered as the QFP tunnel barrier is suppressed. In the best-case scenario, the state of the system will reach 11, 0, OR) or 11, 0, 0L) after the QFP barrier is suppressed. Diabatically passing through the smallgap anticrossings at t=58 ns (918) will bring the system to 11, 0, 0) after suppressing the SRS tunnel barrier. In this scenario the system can only reach the ground state via relaxation of the qubit 11, 0, 0) -> 10, 0, 0) . In the worst-case scenario, the qubit does not relax in time for the next operation and a reset error will be incurred. For this reason, it is beneficial for the tilt-and-latch procedure to be adiabatic. This can be engineered by modifying the time -dependent control sequence as needed. In some implementations, modifying the time-dependent control sequence can involve lengthening one or more of the time periods shown in Figure 9. For example, in some implementations lengthening the time period between 906 and 908 may decrease the likelihood of exciting the system, which may reduce the risks later in the evolution as well.

[0082] Figure 10 is a flowchart of an example method 1000 of solving a computational problem on a hybrid computing system that can be employed in accordance with the present systems, devices, and methods. Method 1000 can, for example, be used with example circuit 500 of Figure 5. In some implementations, method 1000 may be executed on a hybrid computing system comprising at least one digital or classical processor in communication with at least one quantum processor. For example, method 1000 may be performed by computing system 100 of Figure 1. The quantum processor may, for example, include a flux qubit comprising a body loop interrupted by a compound Josephson junction (CJJ), such as flux qubit 200 of Figure 2 and flux qubit 502 of Figure 5. The digital or classical processor may provide control signals or instructions to the quantum processor to execute the method.

[0083] Method 1000 comprises evenly numbered acts 1002 to 1014; however, a person skilled in the art will understand that the number of acts illustrated is an example, and, in some implementations, certain acts may be omitted, further acts may be added, and / or the order of the acts may be changed.

[0084] Method 1000 starts, for example in response to a call or invocation from another routine.

[0085] At 1002, one or more programming control signals are applied to the flux qubit by the digital processor to program the quantum processor based on the computational problem, the flux qubit being programmed in an energy basis. In some implementations, the computational problem, can, for example, be a surface code problem or another gate model computation.

[0086] At 1004, the quantum processor is instructed to evolve to a processor final state by the digital processor, the processor final state comprising the flux qubit in a qubit final state in the energy basis.

[0087] At 1006, a first control signal is applied by one of the digital processor and the quantum processor to transmit a flux bias to the body loop of the flux qubit to transform the qubit final state of the flux qubit from the energy basis to a flux basis.

[0088] At 1008, a second control signal is applied by one of the digital processor and the quantum processor to latch the qubit final state of the flux qubit. In some implementations the second control signal can be applied to the CJJ of the flux qubit, such as CJJ 506 of qubit 502 in the example implementation of Figure 5. In other implementations the second control signal can be applied to a CJJ of a latching QFP coupled to the flux qubit, such as latching QFP 514 coupled to qubit 502 as discussed above. As discussed above, control signals may be applied through analog lines from room temperature or by on-chip control devices.

[0089] At 1010, a third control signal is applied by one of the digital processor and the quantum processor to copy the qubit final state of the flux qubit to a shift register. In some implementations the third control signal may be applied via a latching quantum flux parametron (QFP), the latching QFP at least one of magnetically and galvanically coupled to the flux qubit, as in the example implementation of Figure 5 with qubit 502 and latching QFP 514. In some implementations the third control signal raises a tunnel barrier of a first stage of the shift register.

[0090] At 1012, one or more fourth control signals are applied by one of the digital processor and the quantum processor to transmit the qubit final state of the flux qubit through the shift register.

[0091] At 1014, the qubit final state is received by the digital processor. The qubit final state may, for example, represent a solution to the computational problem, one variable value within a solution to the computational problem, or a value that may be post processed or transformed to provide a value within a solution to the computational problem, such as a value for a sub problem or clustering problem.

[0092] After 1014, method 1000 terminates, until it is, for example, invoked again. Method 1000 may be iterated or performed simultaneously with respect to a plurality of qubits in a quantum processor to provide one or more sample solutions, and may also be repeated iteratively to provide a plurality of sample solutions to a computational problem. In some implementations method 1000 may also include removing the control signals.

[0093] The above described method(s), process(es), or technique(s) could be implemented by a series of processor readable instructions stored on one or more nontransitory processor-readable media. Some examples of the above described method(s), process(es), or technique(s) method are performed in part by a specialized device such as an adiabatic quantum computer or a quantum annealer, a gate, or circuit, model quantum computer, or a system to program or otherwise control operation of an adiabatic quantum computer, a quantum annealer, or a gate, or circuit, model quantum computer, for instance a computer that includes at least one digital processor. The above described method(s), process(es), or technique(s) may include various acts, though those of skill in the art will appreciate that in alternative examples certain acts may be omitted and / or additional acts may be added. Those of skill in the art will appreciate that the illustrated order of the acts is shown for example purposes only and may change in alternative examples. Some of the example acts or operations of the above described method(s), process(es), or technique(s) are performed iteratively. Some acts of the above described method(s), process(es), or technique(s) can be performed during each iteration, after a plurality of iterations, or at the end of all the iterations.

[0094] The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Although specific implementations of and examples are described herein for illustrative purposes, various equivalent modifications can be made without departing from the spirit and scope of the disclosure, as will be recognized by those skilled in the relevant art. The teachings provided herein of the various implementations can be applied to other methods of quantum computation, not necessarily the example methods for quantum computation generally described above.

[0095] The various implementations described above can be combined to provide further implementations. All of the commonly assigned U.S. patent application publications, U.S. patent applications, foreign patents, and foreign patent applications referred to in this specification and / or listed in the Application Data Sheet are incorporated herein by reference, in their entirety, including but not limited to:

[0096] International Patent Application No. PCT / US2022 / 37457 (Kineon qubit)

[0097] U.S. Provisional Patent Application Nos. 63 / 356663 (Surface code 1); 63 / 390185 (Surface code 2); 63 / 265605 (cold control)

[0098] U.S. Patent Application Publication No. 2021 / 0248506 (Projective source)

[0099] U.S. Patent No. 10,528,886 (QFP shift registers); 9,768,371 (Josephson junction fab); 8,536,566 (CCJJs) These and other changes can be made to the implementations in light of the abovedetailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific implementations disclosed in the specification and the claims, but should be construed to include all possible implementations along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Claims

CLAIMS1 . A method of reading out a state of a flux qubit in a quantum processor after performing a computation using the quantum processor with the flux qubit in an energy basis, the computation resulting in a final state of the flux qubit in the energy basis, the flux qubit comprising a body loop interrupted by a compound Josephson junction (CJJ), the method comprising: applying a flux bias to the body loop of the flux qubit to transform the final state of the flux qubit from the energy basis to a flux basis; applying a first control signal to latch the final state of the flux qubit in the flux basis; copying the final state of the flux qubit in the flux basis to a shift register; and transmitting the final state of the flux qubit through the shift register and off of the quantum processor.

2. The method of claim 1, wherein applying a first control signal to latch the final state of the flux qubit in the flux basis comprises applying the first control signal to the CJJ of the flux qubit.

3. The method of claim 2, wherein copying the final state of the flux qubit in the flux basis to a shift register comprises applying a second control signal to raise a tunnel barrier of a CJJ of a first stage of the shift register.

4. The method of claim 3, further comprising, after transmitting the final state of the flux qubit through the shift register and off of the quantum processor: removing the flux bias from the body loop of the flux qubit; removing the first control signal from the CJJ of the flux qubit; and removing the second control signal latching the state of the first stage of the shift register.

5. The method of any one of claims 1 through 4, wherein applying a first control signal to latch the final state of the flux qubit in the flux basis comprises applying a first control signal through an analog line.

6. The method of any one of claims 1 through 4, wherein applying a first control signal to latch the final state of the flux qubit comprises applying a first control signal by a control device on the quantum processor.

7. The method of claim 1, wherein copying the final state of the flux qubit in the flux basis to a shift register comprises copying the final state of the flux qubit in the flux basis to a shift register via a latching quantum flux parametron (QFP), the latching QFP at least one of magnetically and galvanically coupled to the flux qubit.

8. The method of claim 7, wherein applying a first control signal to latch the final state of the flux qubit in the flux basis comprises applying a first control signal to a CJJ of the latching QFP.

9. The method of claim 8, wherein copying the final state of the flux qubit in the flux basis to a shift register comprises applying a second control signal to raise a tunnel barrier of a first stage of the shift register.

10. The method of claim 9, further comprising, after transmitting the final state of the flux qubit through the shift register and off of the quantum processor: removing the flux bias from the body loop of the flux qubit; removing the first control signal latching the state of the latching QFP; and removing the second control signal latching the state of the first stage of the shift register.

11. A method of solving a computational problem on a hybrid computing system, the hybrid computing system comprising a digital processor in communication with a quantum processor, the quantum processor comprising a flux qubit comprising a body loop interrupted by a compound Josephson junction (CJJ), the method comprising: applying one or more programming control signals to the flux qubit by the digital processor to program the quantum processor based on the computational problem, the flux qubit being programmed in an energy basis; instructing the quantum processor to evolve to a processor final state by the digital processor, the processor final state comprising the flux qubit in a qubit final state in the energy basis; applying a first control signal by one of the digital processor and the quantum processor to transmit a flux bias to the body loop of the flux qubit to transform the qubit final state of the flux qubit from the energy basis to a flux basis; applying a second control signal by one of the digital processor and the quantum processor to latch the qubit final state of the flux qubit; applying a third control signal by one of the digital processor and the quantum processor to copy the qubit final state of the flux qubit to a shift register;applying one or more fourth control signals by one of the digital processor and the quantum processor to transmit the qubit final state of the flux qubit through the shift register; and receiving the qubit final state by the digital processor.

12. The method of claim 11, wherein applying a third control signal by one of the digital processor and the quantum processor to copy the qubit final state of the flux qubit to a shift register comprises applying a third control signal by one of the digital processor and the quantum processor to copy the qubit final state of the flux qubit to a shift register via a latching quantum flux parametron (QFP), the latching QFP at least one of magnetically and galvanically coupled to the flux qubit.

13. The method of claim 11, wherein applying a second control signal by one of the digital processor and the quantum processor to latch the qubit final state of the flux qubit comprises applying a second control signal by one of the digital processor and the quantum processor to the CJJ of the flux qubit.

14. The method of claim 12, wherein applying a third control signal by one of the digital processor and the quantum processor to copy the qubit final state of the flux qubit to a shift register comprises applying a third control signal by one of the digital processor and the quantum processor to raise a tunnel barrier of a first stage of the shift register.

15. The method of claim 13, further comprising: removing the first control signal by one of the digital processor and the quantum processor from the body loop of the flux qubit; removing the second control signal by one of the digital processor and the quantum processor latching the qubit final state of the flux qubit; and removing the third control signal latching the qubit final state of a first stage of the shift register.

16. The method of claim 11, wherein applying a second control signal by one of the digital processor and the quantum processor to latch the qubit final state of the flux qubit comprises applying a second control signal by one of the digital processor and the quantum processor to a CJJ of a latching QFP coupled to the flux qubit.

17. The method of claim 15, wherein applying a third control signal by one of the digital processor and the quantum processor to copy the qubit final state of the flux qubit to a shiftregister comprises applying a third control signal by one of the digital processor and the quantum processor to raise a tunnel barrier of a first stage of the shift register.

18. The method of claim 16, further comprising: removing the first control signal by one of the digital processor and the quantum processor; removing the second control signal by one of the digital processor and the quantum processor; and removing the third control signal by one of the digital processor and the quantum processor.

19. The method of any one of claims 11 through 18, wherein applying a second control signal to latch the qubit final state of the flux qubit comprises applying a second control signal through an analog line.

20. The method of any one of claims 11 through 18, wherein applying a second control signal to latch the qubit final state of the flux qubit comprises instructing an on-chip control device to apply a second control signal.21 . The method of any one of claims 11 through 18, wherein applying one or more programming control signals to the flux qubit by the digital processor to program the quantum processor based on the computational problem comprises applying one or more programming control signals to the flux qubit by the digital processor to program the quantum processor based on a surface code problem.

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