Avalanche photodiode pixel

Abstract

Avalanche photodiode pixel The present description relates to an avalanche photodiode pixel (201) comprising: - a transistor (118) adapted to be controlled by an activation signal (EN) having a first state for controlling the activation of the pixel and a second state for controlling the deactivation of the pixel, the transistor being configured to connect an avalanche photodiode (114) of the pixel to a node for applying a substrate voltage (VSUB) when the activation signal is in the first state; and - an output circuit (210) adapted to be controlled by the activation signal and configured to provide an output signal of the pixel (152) when the activation signal is in the first state and to block the output signal of the pixel when the activation signal is in the second state. Figure for abstract: Fig. 2

Description

Title of the invention: Avalanche photodiode pixel Technical field

[0001] The present description relates generally to the field of APD (Avalanche PhotoDiode) pixel matrices and in particular SPAD (Single-Photon Avalanche Diode) pixel matrices. Prior art

[0002] A SPAD, like an APD, exploits the current of an avalanche triggered by photons from a reverse-biased PN junction to detect incident radiation. The essential difference between a SPAD and an APD is that a SPAD is specifically designed to operate with a reverse-bias voltage higher than the breakdown voltage, whereas an APD operates at a bias lower than the breakdown voltage. In a SPAD, a single photogenerated carrier can trigger an avalanche in the deserted area by impact ionization effect. The SPAD is then in the Geiger state, or Geiger mode. In a SPAD or an APD, each time a photon is absorbed by an active region of the photodiode, a fast discharge is triggered. The discharges are counted using one (or a plurality of) counters.

[0003] Avalanche photodiodes are generally incorporated into electronic devices. An electronic device may include a plurality of pixels, each comprising at least one avalanche photodiode. For example, an image sensor may include an array of pixels, each comprising at least one avalanche photodiode, which enables the image sensor to obtain an image of a scene at a given time. The image generally consists of an array of pixels, each pixel comprising at least one avalanche photodiode.

[0004] Such a pixel array can be used for a multitude of applications, including for example telemetry (in English "ranging"), 2D or 3D imaging, depth mapping, or laser remote sensing (LiDAR, for "light detection and ranging").

[0005] An electronic device for such applications may include a light source for emitting a light pulse into the image scene. Light reflected back from any object in the image scene is detected by the photodiodes in the pixels, and used to determine the time of flight of the light pulse. The distance from the object to the electronic device can then be deduced based on this time of flight. The detection by the photodiodes of the pulse The return light pulse can be based on a discharge count. In particular, each photodiode can provide a discharge count when a photon is detected, and by monitoring the discharge counts, the arrival time of the return light pulse can be estimated.

[0006] Large arrays of avalanche photodiodes may include many more, for example, on the order of ten times or even a hundred times more, pixels than counters. The pixels of an array may be divided into different subsets (or subregions) of pixels, each subset (or subregion) to be connected to a common counter, for example by means of an OR tree, and the pixels of the subset may be activated one after the other to have only one pixel connected to the same counter at a time, while the other pixels of the subset should preferably be deactivated. Summary of the invention

[0007] There is a need to be able to deactivate each pixel with certainty, for example to avoid compromising the counting in a subset (or sub-region) of pixels by a counter which is common to all the pixels in the subset.

[0008] One embodiment overcomes all or part of the drawbacks of known avalanche photodiode pixels.

[0009] One embodiment provides an avalanche photodiode pixel comprising: - a transistor adapted to be controlled by an activation signal having a first state for controlling the activation of the pixel and a second state for controlling the deactivation of the pixel, the transistor being configured to connect an avalanche photodiode of the pixel to a node for applying a substrate voltage when the activation signal is in the first state; and - an output circuit adapted to be controlled by the activation signal and configured to provide an output signal of the pixel when the activation signal is in the first state and to block the output signal of the pixel when the activation signal is in the second state.

[0010] According to one embodiment, the activation signal is an activation voltage.

[0011] According to one embodiment, the avalanche photodiode pixel further comprises a detection circuit connected to the avalanche photodiode and configured to generate the pixel output signal.

[0012] According to one embodiment, the detection circuit comprises an inverter, for example configured to convert an analog signal generated by the avalanche photodiode into a digital signal to generate the output signal of the pixel.

[0013] According to one embodiment, the output circuit comprises an output AND gate comprising a first input node to which the output signal of the pixel is adapted. be applied, a second input node to which the activation signal is adapted to be applied, the output node of the output AND gate being connected to, or corresponding to, an output node of the pixel.

[0014] According to one embodiment, the first input node of the output AND gate is connected, for example, to an output node of the inverter.

[0015] According to one embodiment, the inverter is adapted to be powered by a dedicated supply voltage.

[0016] According to one embodiment, the output circuit comprises the inverter, the inverter being adapted to be controlled by the activation signal, for example the activation signal being applied to a node for applying a supply voltage of the inverter.

[0017] According to one embodiment, an output node of the inverter is connected to, or corresponds to, an output node of the pixel.

[0018] According to one embodiment, the output circuit is connected, for example connected, to a counter, for example the counter being configured to integrate the output signal of the pixel when the activation signal is in the first state.

[0019] According to one embodiment, the avalanche photodiode pixel further comprises another inverter between the inverter and the output node of the detection circuit.

[0020] According to one embodiment, the avalanche photodiode pixel further comprises a buffer adapted to increase the power of the activation signal.

[0021] One embodiment provides a pixel array comprising a plurality of avalanche photodiode pixels such as the avalanche photodiode pixels described above, wherein the avalanche photodiode pixels are organized into different avalanche photodiode pixel subregions, with avalanche photodiode pixels in the same subregion being connected to a common counter.

[0022] According to one embodiment, the matrix further comprises a selection circuit configured to selectively address the activation signal to an avalanche photodiode pixel among the avalanche photodiode pixels of a sub-region, the selection circuit comprising an output node connected at least to the transistor of the avalanche photodiode pixel.

[0023] According to one embodiment, the output node of the selection circuit is also connected to the second input node of the output AND gate.

[0024] According to one embodiment, the output node of the selection circuit is also connected or linked to a node for applying a power supply to the inverter.

[0025] According to one embodiment, the buffer is included in the selection circuit. Brief description of the drawings

[0026] These and other features and advantages will be set forth in detail in the following description of particular embodiments made without limitation in relation to the attached figures among which:

[0027] [Fig.l] represents an example of a part of a SPAD matrix;

[0028] [Fig.2] represents a part of a SPAD matrix comprising a SPAD pixel according to one embodiment; and

[0029] [Fig.3] represents a part of a SPAD matrix comprising a SPAD pixel according to another embodiment. Description of the embodiments

[0030] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0031] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the implementation of an image sensor comprising a light source and a plurality of pixels, each having an avalanche photodiode, has not been described in detail, the described embodiments being compatible with conventional image sensors. More generally, the numerous applications in which one or more avalanche photodiodes are provided for detecting photons have not been described in detail, the described embodiments being compatible with conventional applications of these photodiodes.Furthermore, practical implementations of a photodiode suitable for use as an avalanche photodiode have not been described in detail, the described embodiments being compatible with conventional implementations of a photodiode suitable for use as an avalanche photodiode.

[0032] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0033] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0034] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0035] In the following description, a pixel, or an APD pixel, designates a pixel at avalanche photodiode, for example a SPAD pixel which can be referred to for short as a SPAD pixel. A SPAD array can be referred to as a SPAD matrix.

[0036] In the following description, a first state of the activation signal corresponds to a state, for example a high state, which is suitable for activating a pixel, while the second state of the activation signal corresponds to a state, for example a low state, which is suitable for deactivating the pixel. The first and second states correspond for example to different voltage levels, for example respectively a first voltage (high) and a second voltage (low), lower than the first voltage.

[0037] [Fig.l] shows an example of a part of a SPAD matrix 100. The SPAD matrix 100 has a plurality of different sub-regions of SPAD pixels, each sub-region being connected to a common counter 120, for example by means of an OR tree (not shown). The SPAD pixels of the sub-region can be activated one after the other to have only one active SPAD pixel at a time connected to the same counter, while the other SPAD pixels of the sub-region should preferably be deactivated. A single SPAD pixel of a sub-region is shown in [Fig.l].

[0038] More particularly, [Fig.l] shows an example of a SPAD circuit 102 and a detection circuit 103 in a SPAD pixel 101, and a selection circuit 104 configured to selectively activate a SPAD pixel, for example the SPAD pixel 101, in a sub-region of the SPAD matrix 100.

[0039] The SPAD circuit 102 comprises, in the example of [Fig.l], a protection diode 112 and a SPAD photodiode 114. The protection diode 112 is also called a "pull-up" diode, or a "clamp" diode. The protection diode 112 is connected, preferably connected, between a node for applying a pull-up voltage (VPULLUP) and a first node 113. The anode of the diode 112 is connected, preferably connected, to the first node 113 and the cathode of the diode 112 is connected, preferably connected, to the VpULLUP node.

[0040] The protection diode 112 is a deactivation diode, making it possible to maintain the anode node of the SPAD photodiode 114 at an intermediate voltage value between a high voltage (VHv) and a low voltage (VSub), for example equal to approximately 7 V or 8 V, when the SPAD photodiode 114 is blocked. For example, the high leveling voltage VpULLUP has a value at least 2 V higher than the excess bias applied to the SPAD beyond the breakdown voltage.

[0041] The SPAD photodiode 114 is connected, preferably connected, between the first node 113 and a second node 115. The cathode of the SPAD photodiode 114 is connected, preferably connected, to the second node 115 and the anode of the SPAD photodiode 114 is connected, preferably connected, to the first node 113.

[0042] The SPAD circuit 102 further comprises an extinguishing resistor 116 (Rq), in English "quench resistor", connected, preferably connected, between the second node 115 and a node for applying a voltage (VHv), for example a high voltage, for example a voltage greater than or equal to the breakdown voltage of the diode, which is typically between 10 V and 40 V.

[0043] The SPAD circuit 102 further comprises an activation transistor 118 and a cascode-mounted transistor 117, the transistors 117, 118 being connected, preferably connected, in series between a node for applying a low voltage (VSub), for example ground, and the first node 113. More particularly, the cascode-mounted transistor 117 is connected, preferably connected, by its conduction terminals, for example its drain and source, between the first node 113 and a third node 119. The activation transistor 118 is connected, preferably connected, by its conduction terminals, for example its drain and source, between the third node 119 and the VSub-

[0044] The low voltage VSub preferably corresponds to the voltage of the substrate on and in which the photodiode, and associated circuits, are formed, and may be referred to as the "substrate voltage". The substrate may be connected to ground, and the low voltage may be substantially equal to 0 V.

[0045] Transistors 117 and 118 are preferably N-type MOS field effect transistors.

[0046] The cascode-mounted transistor 117 is biased by a voltage Vcasn, which is a determined voltage and, preferably, has an intermediate value between the high voltage Vhv and the low voltage VSub, while the activation transistor 118 is biased by an activation signal EN, for example an activation voltage. The voltage VCasn is for example between 1 V and 2.5 V.

[0047] When the activation signal EN is in the first state, for example at a high voltage of about 1.1 V, the activation transistor 118 turns on, connecting the anode of the SPAD 114 to the low voltage VSub, for example ground, placing the reverse bias voltage of the SPAD 114 above the breakdown voltage, while the protection diode 112 disconnects the anode of the SPAD 114 from the high leveling voltage VPULLUP. When an incoming photon strikes the SPAD 114, its cathode voltage decreases between the high voltage VHv and a lower voltage, creating a current pulse that is collected by the detection circuit 103. The avalanche can be quenched by the quenching resistor 116, resetting the SPAD 114 for further detection.When the enable / disable function is operating correctly, and the enable signal EN is in the second state, for example has a low voltage of about 0 V, the enable transistor 118 is adapted to disconnect the anode of the SPAD 114 from the low voltage VSub, the anode of the SPAD 114 then being connected to the high leveling voltage VPUllup and the SPAD 114 is disabled.

[0048] The activation transistor 118 may form an activation / deactivation circuit, for example in combination with the cascode-connected transistor 117.

[0049] The purpose of having a determined voltage VCasn is to bias the cascode-mounted transistor 117 so that it limits the current flow into the activation transistor 118 during the avalanche, protecting the transistor 118 from damage.

[0050] The interest of having an intermediate high leveling voltage VPULLUP can also be to protect the activation transistor 118 when the activation signal EN is in the second state, because then the first node 113 is a floating node, that is to say not connected to the low voltage VSub-

[0051] The detection circuit 103 comprises a high-pass filter transistor 122 connected, preferably connected, by its conduction terminals, for example its drain and source, between a node for applying a supply voltage (VDDiVi) and the second node 115, for example by means of a fourth node 125 between the high-pass filter transistor 122 and the second node 115. A bias voltage node (VHPP) is connected, preferably connected, to the gate of the transistor 122. The transistor 122 is preferably a P-type MOS field-effect transistor. The voltage Vddivi ​​is for example between 0.9 V and 1.3 V. The voltage VHPP is for example between 0 V and V DD1V1*

[0052] The detection circuit 103 may further comprise capacitive elements, for example first and second capacitors 123, 124. The first capacitor 123 may be connected, preferably connected, between the second node 115 and the fourth node 125, which may be called a "mobile node". The second capacitor 124 may be connected, preferably connected, between the fourth node 125 and a node for applying the low voltage VSub-

[0053] The detection circuit 103 also comprises an inverter 130 connected, preferably connected, between the fourth node 125 and an output node 136 (output node of the inverter). The inverter 130 typically comprises a P-type MOS field effect transistor 132 in series with an N-type MOS field effect transistor 134. The P-type transistor 132 is connected, preferably connected, by its conduction terminals, for example its drain and source, between a node for applying a supply voltage VDD and the output node 136. The N-type transistor 134 is connected, preferably connected, by its conduction terminals, for example its drain and source, between the output node 136 and a node for applying a low voltage, for example the ground GND. The gates of transistors 132, 134 are connected, preferably connected, to the fourth node 125.

[0054] When an avalanche occurs in the SPAD photodiode 114, the voltage at the fourth node 125 decreases, and the high-pass filter transistor 122 increases the voltage at the node 125 after the avalanche, leading to a voltage signal in V-shaped 151 (analog signal), as shown at the fourth node 125 in [Fig.l]. The inverter 130 then converts the V-shaped voltage signal 151 into a pulse signal 152 (digital signal), as shown at the output node 136 in [Fig.l]. The pulse signal can then be applied to a counter 120 (COUNTER), preferably a digital counter, which is connected to the output node 136 of the inverter. In [Fig.l], the output node 136 corresponds to an output node of the SPAD pixel 101 (pixel output node), and the pulse signal 152 constitutes a digital output signal of the pixel which can then be integrated by the counter 120.

[0055] Therefore, the SPAD pixel 101 feeds a counter 120.

[0056] The selection circuit 104 of the SPAD pixel 101 of the SPAD matrix 100 comprises a register, or memory, 142 (SRAM) storing a binary value, or data D, associated with the SPAD pixel.

[0057] Register 142 receives a column select signal COL_SEL from a column select circuit SPAD (not shown in [Fig.l]) and a row select signal ROW_SEL from a row select circuit SPAD (also not shown in [Fig.l]). For example, register 142 is configured to program value D with the value of column select signal COL_SEL when row select signal ROW_SEL is asserted. According to the example of [Fig.l], register 142 includes a word line input WL receiving row select signal ROW_SEL, a positive bit line input BL receiving column select signal COL_SEL, and a negative bit line input BL_N receiving the inverse of column select signal COL_SEL, generated by another inverter 143.

[0058] The selection circuit 104 comprises, for example, an AND gate 144 (AND) dedicated to the SPAD pixel 101 of the matrix. The AND gate 144 provides an activation signal EN to the gate of the activation transistor 118. In certain embodiments, the activation signal EN is amplified by a buffer 145 (BUFFER), for example a buffer amplifier, connected between the output of the AND gate 144 and the gate of the activation transistor 118. Thus, the activation signal EN may correspond to an output signal of the AND gate 144 or of the buffer 145. The AND gate 144 has one of its input nodes connected to a corresponding output of the register 142 on which the data D is present, and the other of its input nodes connected to an input line which receives a common activation signal EN_SPAD for a sub-region of the SPAD matrix 100.

[0059] The counter 120 may be sequentially coupled with other SPAD pixels of the same sub-region (not shown). When a SPAD pixel of a sub-region is activated (ON), the other SPAD pixels of the same sub-region are preferably deactivated (OFF). For example, a SPAD pixel is activated when the activation signal EN applied to its enable transistor is in the first state, e.g., at about 1.1 V, and is turned off when the enable signal EN applied to its enable transistor is in the second state, e.g., at about 0 V. If other SPAD pixels in the same sub-region are not turned off, this may compromise counting in the sub-region of the matrix that has pixels connected to the same counter.

[0060] Unfortunately, the turn-on / turn-off function of a SPAD pixel may not work properly. For example, due to manufacturing defects, a Deep Trench Isolation (DTI) that is dedicated to isolating a photodiode from other circuits such as an on / off circuit, could fail to reach the back surface of the substrate, forming a resistive path. The on / off circuit, for example, the enable transistor 118, could be shorted and the anode of the photodiode permanently grounded, i.e., the photodiode always on. In other words, such a manufacturing defect could compromise the ability to turn off the SPAD pixel. In this case, the affected SPAD pixel is permanently connected to the common counter, impacting an entire subregion of pixels.

[0061] According to a standard procedure, a damaged pixel can be identified initially, for example using an internal verification circuit, and should be deactivated, for example to avoid disturbing other pixels connected to the same counter. This standard procedure does not work, however, for a pixel whose activation / deactivation function is damaged.

[0062] The inventors propose an avalanche photodiode pixel that can meet the improvement needs described above, and overcome all or part of the disadvantages of the SPAD pixels described above. In particular, the inventors propose a solution for making avalanche photodiode pixels more robust against manufacturing defects, preferably without adding a complex circuit or device.

[0063] Embodiments of SPAD pixels will be described hereinafter. The embodiments described are non-limiting and many variations thereof will be apparent to those skilled in the art based on the guidance in this disclosure. SPAD pixels are described, but the embodiments also apply to other avalanche photodiode pixels.

[0064] [Fig. 2] shows a portion of a SPAD matrix 200 comprising a SPAD pixel 201 according to one embodiment. Similar to the SPAD matrix 100 of [Fig. 1], the SPAD matrix 200 comprises a plurality of different sub-regions of SPAD pixels, each sub-region being connected to a common counter 120, for example by means of an OR tree (not shown).

[0065] [Fig.2] shows a SPAD pixel 201 comprising a similar SPAD circuit 102 to that of [Fig.l], and a detection circuit 203. [Fig.2] also represents a selection circuit 104 of the SPAD matrix 200 similar to the selection circuit of [Fig.l].

[0066] The detection circuit 203 of [Fig. 2] differs from that of [Fig. 1] essentially in that it comprises an output AND gate 210 (AND OUT). The output AND gate 210 comprises a first input node connected, preferably connected, to the output node 136 of the inverter 130, and a second input node connected, preferably connected, to an output of the buffer 145, or of the AND gate 144, in order to receive the activation signal EN. In other words, the activation signal EN is applied to the activation transistor 118 and to the output AND gate 210. The output AND gate 210 has its output node connected, preferably connected, to the counter 120.

[0067] Therefore, even if the activation / deactivation function is damaged, for example if the activation transistor 118 is short-circuited, and the anode of the SPAD photodiode 114 is permanently grounded, i.e. the photodiode is always activated, the activation signal EN is still sent to the output AND gate 210. The AND function applied by the output AND gate 210 between the pulse signal 152 generated by the inverter 130 and the activation signal EN generates, at an output node of the pixel 212, a digital output signal of the pixel which is applied to the counter 120. The output AND gate 210 is configured to block, or cancel, the pulse signal 152 when the activation signal EN is in the second state. In other words, when the enable signal EN is in the second state, the output AND gate 210 blocks any signal that would otherwise have been integrated by the counter 120.The output AND gate 210 is configured to pass the pulse signal 152 when the enable signal EN is in the first state. When the enable signal EN is in the first state, then the pulse signal 152 generated by the inverter 130 can be integrated by the counter 120.

[0068] This first solution is effective for deactivating a SPAD pixel even when the activation / deactivation function of this SPAD pixel is damaged. In addition, the first solution allows rapid extinction, or deactivation, of the SPAD pixel since the extinction is directly carried out at the output node of the pixel 212.

[0069] The first solution requires adding a component (another AND gate) that can consume area.

[0070] [Fig. 3] shows a portion of a SPAD array 300 comprising a SPAD pixel 301 according to another embodiment. Similar to the SPAD array 100 of [Fig. 1], the SPAD array 300 comprises a plurality of different sub-regions of SPAD pixels, each sub-region being connected to a common counter 120, for example by means of an OR tree (not shown).

[0071] [Fig. 3] represents a SPAD pixel 301 comprising a SPAD circuit 102 similar to that of [Fig. 1], and a detection circuit 303. [Fig. 3] also represents a selection circuit 104 of the SPAD matrix 300 similar to the selection circuit of [Fig. 1].

[0072] The detection circuit 303 of [Fig. 3] differs from that of [Fig. 1] essentially in that the inverter 130 is no longer powered by the supply voltage VDD, but is powered (controlled) by the activation signal EN. In the example shown, the node for applying a supply voltage to the P-type transistor 132 is connected, preferably connected, to an output of the buffer 145, or of the AND gate 144 directly, in order to receive the activation signal EN. Similar to [Fig. 1], in the embodiment of [Fig. 3], the output node of the pixel corresponds to the output node 136 of the inverter 130.

[0073] Therefore, even if the activation / deactivation function is damaged, for example if the activation transistor 118 is short-circuited, and the anode of the photodiode is permanently grounded, i.e. the photodiode is always activated, the activation signal EN is still sent to the inverter 130. When the activation signal EN is in the second state, then the inverter 130 does not generate a pulse signal at the output node 136 of the inverter, i.e. no digital output signal of the pixel at the output node of the pixel, which would otherwise have been integrated by the counter 120. In other words, the activation signal EN can avoid generating a pulse signal and having it integrated by the counter 120. When the activation signal EN is in the first state, then the inverter 130 is powered and can therefore generate a signal pulse 152 at the output node of pixel 136 which can be integrated by counter 120.

[0074] This second solution is effective for deactivating a pixel even when the activation / deactivation function of this pixel is damaged, and, moreover, it does not necessarily require the use of another component. Thus, the second solution is more optimal in terms of surface area used. Furthermore, the second solution can reduce power consumption, because the pixel inverter can be activated only, or essentially, when the pixel is activated, that is to say only, or essentially, during the integration time of the pixel.

[0075] The inventors have demonstrated, using simulations, that even in worst cases, using the output signal EN of buffer 145 or AND gate 144 as a power supply for inverter 130 does not significantly affect the states of the buffer or the AND gate. Using a simulation, the inventors found only 152 mV drop on the output signal of the buffer or the AND gate, which does not change the state of any logic circuit connected to the output of the buffer or the AND gate. Moreover, the inventors have demonstrated that the switching speed of the inverter 130 is practically unaffected during use of the activation signal EN.

[0076] The buffer 145 may be provided to increase the power of the activation signal EN, particularly when the pixel is activated. For example, the buffer comprises two inverters in series with each other, the inverters having, for example, larger transistors than those of the AND gate 144.

[0077] According to a variant, which can be applied to the first or to the second solution, the SPAD pixel detection circuit can comprise a second inverter (not shown) between the inverter 130 and the counter 120, for example between the inverter 130 and the output AND gate 210. The second inverter can be designed to be larger and / or more resistant, as a buffer stage more capable of quickly driving long lines or buses connecting the counter.

[0078] The inventors have shown that neither the first nor the second solution impacts the rise time of the digital output signal of the pixel.

[0079] Thus, the first or second solution makes it possible to have SPAD pixels that are more robust with respect to manufacturing defects, without degrading other characteristics of these SPAD pixels.

[0080] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0081] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. An avalanche photodiode pixel (201; 301) comprising: - a transistor (118) adapted to be controlled by an activation signal (EN) having a first state for controlling the activation of the pixel and a second state for controlling the deactivation of the pixel, the transistor being configured to connect an avalanche photodiode (114) of the pixel to a node for applying a substrate voltage (VSub) when the activation signal is in the first state; and - an output circuit (210, 130) adapted to be controlled by the activation signal and configured to provide an output signal of the pixel (152) when the activation signal is in the first state and to block the output signal of the pixel when the activation signal is in the second state; and - a detection circuit (203; 303) connected to the avalanche photodiode (114) and configured to generate the output signal of the pixel (152), the detection circuit (203; 303) comprising an inverter (130);the output circuit comprising the inverter, the inverter being adapted to be controlled by the activation signal (EN).;

2. An avalanche photodiode pixel (201; 301) according to claim 1, wherein the activation signal (EN) is an activation voltage.

3. The avalanche photodiode pixel (201; 301) of claim 1 or 2, wherein the inverter (130) is configured to convert an analog signal (151) generated by the avalanche photodiode (114) into a digital signal to generate the output signal of the pixel (152).

4. An avalanche photodiode pixel (201) according to any one of claims 1 to 3, wherein the output circuit comprises an output AND gate (210) comprising a first input node to which the output signal of the pixel (152) is adapted to be applied, a second input node to which the activation signal (EN) is adapted to be applied, the output node of the output AND gate being connected to, or corresponding to, an output node (212) of the pixel.

5. The avalanche photodiode pixel (201) of claim 4, wherein the first input node of the output AND gate (210) is coupled, e.g., connected, to an output node (136) of the inverter (130).

6. An avalanche photodiode pixel (201) according to claim 5, wherein the inverter (130) is adapted to be powered by a dedicated supply voltage (VDD).

7. An avalanche photodiode pixel (301) according to claim 1, wherein the activation signal is applied to a node for applying a supply voltage of the inverter.

8. The avalanche photodiode pixel (301) of claim 7, wherein an output node (136) of the inverter is connected to, or corresponds to, an output node of the pixel.

9. An avalanche photodiode pixel (201; 301) according to any one of claims 1 to 8, wherein the output circuit (210, 130) is connected, for example, to a counter (120), for example the counter being configured to integrate the output signal of the pixel (152) when the activation signal (EN) is in the first state.

10. An avalanche photodiode pixel according to any one of claims 1 to 9, further comprising a further inverter between the inverter (130) and the output node of the detection circuit.

11. An avalanche photodiode pixel (201; 301) according to any one of claims 1 to 10, further comprising a buffer (145) adapted to increase the power of the activation signal (EN).

12. A pixel array (200; 300) comprising a plurality of avalanche photodiode pixels (201; 301) according to any one of claims 1 to 11, wherein the avalanche photodiode pixels are organized into different avalanche photodiode pixel sub-regions, the avalanche photodiode pixels of the same sub-region being connected to a common counter (120).

13. Pixel array (200; 300) according to claim 12, further comprising a selection circuit (104) configured to selectively address the activation signal (EN) to an avalanche photodiode pixel (201; 301) among the avalanche photodiode pixels of a sub-region, the selection circuit comprising an output node connected at least to the transistor (118) of the avalanche photodiode pixel.

14. A pixel array (200) according to claim 13 in combination with any one of claims 4 to 6, wherein the output node of the selection circuit (104) is also coupled or connected to the second input node of the output AND gate (210).

15. Pixel matrix (300) according to claim 13, wherein the output node of the selection circuit (104) is also connected or coupled to a node for applying a power supply of the inverter (130).

16. A pixel array (200; 300) according to any one of claims 13 to 15 in combination with claim 11, wherein the buffer (145) is included in the selection circuit (104).

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