Semiconductor logic circuit and semiconductor integrated circuit

Abstract

To suppress a current flowing in an output end of a logic circuit and improve extremely low voltage operation performance by applying the same circuit as the logic circuit as a stack structure.SOLUTION: A Multi-Stacked NAND gate (MS-NAND) comprises a Main-NAND 10 and a first-stage NAND11,12 having a stack structure. The Main-NAND 10 comprises two pieces of input A and B and one output Y by connecting MOS transistors 1-4 and comprises a power supply end 101 for connecting a power source and a ground end 102 at both sides. The NAND 11, 12 has the same configuration as the Main-NAND 10 and controls a (inflow / outflow) current flowing in the one output Y of the Main-NAND 10 via a connection end 111, 121 corresponding to the output U, and the connection end 111, 121 is connected to each of the power supply end 101 and the ground end 102 of the Main-NAND.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a semiconductor logic circuit having an extremely low voltage operation capability and an integrated circuit thereof. [Background technology]

[0002] In recent years, wearable devices equipped with sensors that measure pulse, electrocardiogram, blood oxygen saturation, etc., have been developed in the medical field. Energy harvesting has been attracting attention as a power source for such devices. In energy harvesting, the use of physical energy such as heat, light, and electromagnetic waves that do not require charging or replacement is considered as a candidate, while thermoelectric conversion elements that generate electricity by utilizing the temperature difference between the human body and the atmosphere are particularly seen as a promising environmental power source for wearable devices. However, since the voltage that a thermoelectric conversion element can output from the temperature difference between the human body and the outside air is an extremely low voltage of less than 100 mV, when a MOS transistor circuit is operated using the output voltage of the thermoelectric conversion element as a power source, the MOS transistor circuit must be operated in the weak inversion region, that is, with a subthreshold current of the nanoampere order. Thus, when the current flowing through the MOS transistor is small, there is a risk that the output of a normal MOS transistor will not be stable and will not operate normally. For this reason, today, development of an architecture that enables stable operation of MOS transistors at extremely low voltages is underway.

[0003] Up to now, technologies for operating inverters using MOS transistors at extremely low voltages have been proposed. Non-Patent Documents 1 to 3 describe the results of improving an inverter (INV) to enable operation at a voltage of 35 to 50 mV and applying it to a ring oscillator circuit.

[0004] Non-Patent Document 1 relates to a stacked inverter (SI) that reduces the leakage current of a MOS transistor, which is a cause of deterioration of the output voltage of an INV. FIG. 18 is a diagram for explaining an SI, where (A) shows a circuit diagram of an INV, (B) shows a circuit diagram of an SI, and (C) is a symbolic representation of (B). An INV is a known circuit that inverts an input X to obtain an output Y, and has a structure in which a power supply Vdd and a ground Vss are connected to the source S of a PMOS transistor and an NMOS transistor whose gate G and drain D are connected to each other. As shown in FIG. 18(B), an SI has a configuration in which the output end of an INV having the same configuration as the main INV is connected to the source S of each of the PMOS and NMOS transistors of the main INV, and the drain-source voltage of the transistor on the side that is turned off of the main INV is lowered in accordance with the output Y, thereby reducing the leakage current and suppressing deterioration of the output voltage.

[0005] Non-Patent Document 2 uses the substrate bias effect to reduce the threshold voltage V THN ,V THP This paper relates to a Body-bias Inverter (BBI) that controls the output of the NMOS transistor and improves the output. FIG. 19 is a diagram for explaining the BBI, where (A) shows a circuit diagram of the inverter INV, (B) shows a circuit diagram of the BBI, and (C) shows a symbolic representation of (B). As shown in FIG. 19(B), the BBI is composed of two inverters, a feed-forward inverter (FF-INV) and a feedback inverter (FB-INV) in the subsequent stage, and adopts a configuration in which the output of the FF-INV is inverted by the FB-INV and fed back to the substrate potential of the FF-INV via the line Lfb. The BBI utilizes the substrate bias effect to improve the threshold voltage V THN ,V THP By controlling the on-state current, the on-state current is increased and voltage degradation is suppressed.

[0006] Non-Patent Document 3 relates to a stacked body-bias inverter (SBBI) that combines a stacked inverter (SI) and a body-bias inverter (BBI). FIG. 20 is a diagram for explaining the SBBI, where (A) shows a circuit diagram of an inverter INV, (B) shows a circuit diagram of the SBBI, and (C) shows a symbolic representation of (B). The output degradation suppression techniques used for the BBI and SI are not competitive, so they can be simultaneously applied to the INV. As shown in FIG. 20(B), the SBBI is composed of two inverters, the SI and the subsequent FB-INV. As with the BBI, the SBBI adopts a configuration in which the output of the SI is inverted by the FB-INV and fed back to the substrate potential of the SI. This configuration controls the threshold voltage and further improves the output of the SI. Furthermore, by applying the SI to the FB-INV as well, the feedback signal is also improved, resulting in further improvement of the output. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Bose and ML Johnston, “A Stacked-Inverter Ring Oscillator for 50 mV Fully-Integrated Cold-Start of Energy Harvesters,” IEEE ISCAS, 2018, pp. 1-5. [Non-Patent Document 2] R. Matsuzuka et al., “A 42-mV startup ring oscillator using gain-enhanced self-bias inverters for extremely low voltage energy harvesting,” Jpn. J. Appl. Phys. 59, SGGL01, 2020. [Non-Patent Document 3] M. Nishi et al., “A 35-mV supply ring oscillator consisting of stacked body bias Inverters for extremely low-voltage LSIs,” IEICE Electron. Express, vol. 18, issue 6, 20210065, 2021. Summary of the Invention [Problem to be solved by the invention]

[0008] Incidentally, in addition to the inverter described above, NAND (negative logical product) and NOR (negative logical sum) logic circuits are known as circuits composed of MOS transistors. Any logic given by a product-sum system can be realized by only NAND or NOR, so there is an even higher demand for stable operation of such logic circuits using an extremely low output voltage from a thermoelectric conversion element or the like as a power source. However, at present, it is difficult to say that extremely low voltage operation technology for logic circuits has been fully considered. A method has been proposed in which inverters are stacked on top of inverters to improve the extremely low voltage operation performance. In the case of an inverter, since it is a NOT gate with one input and one output, it is easy to divert the NOT gate to a control circuit, while it is possible to improve the extremely low voltage operation performance by stacking it in other logic circuits as well, but it is not necessarily easy to determine what kind of power supply circuit to apply.

[0009] The present invention has been made in view of the above, and has an object to provide a semiconductor logic circuit and an integrated circuit thereof that improves ultra-low voltage operation performance by stacking identical circuits in a logic circuit. [Means for solving the problem]

[0010] The semiconductor logic circuit of the present invention comprises a logic circuit having a plurality of MOS transistors connected to form a circuit with a plurality of inputs and one output terminal, the logic circuit having a power supply terminal and a ground terminal for supplying power to the circuit, and first and second control circuits of a first stage having the same configuration as the logic circuit and controlling the current flowing through the one output terminal of the logic circuit, wherein the first control circuit of the first stage has a connection terminal corresponding to the one output terminal connected to the power supply terminal of the logic circuit, and the second control circuit of the first stage has a connection terminal corresponding to the one output terminal connected to the ground terminal of the logic circuit.

[0011] According to the present invention, the environmental power supply is not directly connected as the power supply of the logic circuit (main logic circuit in the embodiment), but is turned on through a control circuit having at least one stage of stack structure. The same configuration as the logic circuit can be adopted as the control circuit. Also, by respectively interposing the first and second control circuits, the voltage difference between the one output terminal of the logic circuit and the power supply terminal and the ground terminal can be matched to the output voltage of the one output terminal as much as possible, and when the MOS transistor constituting the logic circuit is off, the drain-source voltage is lowered. This makes it possible to suppress the leakage current flowing through the MOS transistor in the weak inversion region, suppress the deterioration of the output voltage of the one output terminal, and realize stable operation of the MOS transistor in an extremely low voltage environment. The recursive stack structure from the second stage onwards is configured based on the control circuit of the first stage.

[0012] The present invention also includes a second-stage first and second control circuits having the same configuration as the logic circuit, which control the current flowing through the connection terminal of the first control circuit of the first stage, and a second-stage third and fourth control circuits which control the current flowing through the connection terminal of the second control circuit of the first stage, and the first control circuit of the second stage has a connection terminal connected to the power supply terminal of the first control circuit, the second control circuit of the second stage has a connection terminal connected to the ground terminal of the first control circuit of the first stage, the third control circuit of the second stage has a connection terminal connected to the power supply terminal of the second control circuit of the first stage, and the fourth control circuit of the second stage has a connection terminal connected to the ground terminal of the second control circuit of the first stage. According to this configuration, by recursively stacking each control circuit of the second stage with each control circuit of the first stage, the effect of suppressing the leakage current of the control circuits of each stage is expected to be cumulative. Note that the stack structure of the control circuits may be three or more stages as long as one and two stages are adopted. In addition, the recursive stack structure from the third stage onwards is constructed based on the control circuit in the second stage.

[0013] The circuit also includes a first circuit having a plurality of MOS transistors on the power supply terminal side and a second circuit having a plurality of MOS transistors on the ground terminal side, the plurality of MOS transistors of the first control circuit of the first stage corresponding to the first circuit have source-drain channel widths that are more than one time the source-drain channel widths of the plurality of MOS transistors of the first circuit of the logic circuit, and the plurality of MOS transistors of the second control circuit of the first stage corresponding to the second circuit have source-drain channel widths that are more than one time the source-drain channel widths of the plurality of MOS transistors of the second circuit of the logic circuit. With this configuration, by making the channel width W of each MOS transistor of the first stage control circuit more than one time the channel width of the MOS transistor of the logic circuit immediately below, it becomes possible to pass a larger current through the channel.

[0014] The circuit also includes a first circuit having a plurality of MOS transistors on the power supply terminal side, and a second circuit having a plurality of MOS transistors on the ground terminal side, the plurality of MOS transistors of a circuit corresponding to the first circuit among the first stage first control circuits have source-drain channel widths that are more than one time larger than the source-drain channel widths of the plurality of MOS transistors of the first circuit of the logic circuit, the plurality of MOS transistors of a circuit corresponding to the second circuit among the second stage second control circuits have source-drain channel widths that are more than one time larger than the source-drain channel widths of the plurality of MOS transistors of the second circuit of the logic circuit, and further, the plurality of MOS transistors of a circuit corresponding to the first circuit among the first stage first control circuits have source-drain channel widths that are more than one time larger than the source-drain channel widths of the plurality of MOS transistors of the circuit corresponding to the first circuit of the first stage first control circuit. a plurality of MOS transistors in a circuit corresponding to the second circuit of the second stage second control circuit have a source-drain channel width that is more than one time larger than the source-drain channel width of a plurality of MOS transistors in a circuit corresponding to the second circuit of the first stage second control circuit, a plurality of MOS transistors in a circuit corresponding to the first circuit of the third control circuit of the second stage have a source-drain channel width that is more than one time larger than the source-drain channel width of a plurality of MOS transistors in a circuit corresponding to the first circuit of the second control circuit of the first stage, and a plurality of MOS transistors in a circuit corresponding to the second circuit of the fourth control circuit of the second stage have a source-drain channel width that is more than one time larger than the source-drain channel width of a plurality of MOS transistors in a circuit corresponding to the second circuit of the second control circuit of the first stage. According to this configuration, by making the channel width W of each MOS transistor constituting the first and second circuits of each control circuit in the second stage more than one time the channel width of the MOS transistor constituting the corresponding circuit in the first and second circuits of the first stage control circuit, it is possible to pass a current that increases in accordance with the magnification through the channel.

[0015] The logic circuit of the present invention is a NAND circuit or a NOR circuit. With this configuration, NAND and NOR have completeness, that is, any combination logic can be configured only with NAND or only with NOR, so that it is possible to improve the extremely low voltage operation performance of any logic circuit.

[0016] The present invention also provides an inverter having an input terminal connected to the one output terminal of the logic circuit, the inverter having an output terminal for feeding back an output to a substrate potential of each MOS transistor constituting the logic circuit and the first-stage control circuit. With this configuration, the threshold voltage of the MOS transistor is controlled by a feedback voltage, and the threshold voltage of the MOS transistor is adjusted up or down, thereby enabling operation at an extremely low voltage.

[0017] The present invention also includes an inverter having an input terminal connected to the one output terminal of the logic circuit, the inverter having an output terminal for feeding back an output to a substrate potential of each MOS transistor constituting the logic circuit, the first-stage control circuit and the second-stage control circuit. With this configuration, the threshold voltages of the MOS transistors in all stages of the circuits are controlled by a feedback voltage, and the threshold voltages of the MOS transistors are adjusted up or down, making it possible to operate at an extremely low voltage.

[0018] Furthermore, according to the present invention, it is possible to realize a semiconductor integrated circuit having extremely low voltage operation performance. Effect of the Invention

[0019] According to the present invention, by applying the same circuit as the logic circuit as a stack structure, the current flowing through the output terminal of the logic circuit is suppressed, thereby improving the extremely low voltage operation performance. [Brief description of the drawings]

[0020] [Figure 1]FIG. 1 illustrates a NAND gate. (A) is a circuit diagram of a NAND gate with two inputs and one output, and (B) is its truth table. [Diagram 2] (A) is a diagram explaining the input / output logic, and (B) is a state diagram explaining the voltage of the source terminal determined by the output logic. [Diagram 3] FIG. 1A is a diagram for explaining a preferred voltage for the source terminal to suppress a leakage path that degrades the output logic, and FIG. 1B is a diagram for explaining a preferred voltage for the source terminal of a MOS transistor in an off state to suppress a leakage path on the parallel circuit side when the output Y is “1.” [Figure 4] FIG. 1 shows the voltages of all source terminals for the state of two inputs. [Diagram 5] This shows a circuit diagram of a single-stage MS-NAND (i.e., S-NAND) among Multi-Stacked NAND gates (MS-NAND). [Figure 6] These are symbolic diagrams of MS-NAND. (A) is a symbolic diagram of a 1S-NAND gate with one stage of NAND shown in FIG. 5. (B) is a symbolic diagram of a 2S-NAND gate with a second stage of NAND recursively stacked on the first stage of NAND in (A). (C) is a symbolic diagram of a 3S-NAND gate with a third stage of NAND recursively stacked on the second stage of NAND in (B). [Figure 7] FIG. 2 is a schematic vertical sectional perspective view for explaining a structure of a portion of an NMOS transistor. [Figure 8] 1A is a circuit diagram of a 1S-NAND and FIG. 1B is a circuit diagram of a 2S-NAND in an MS-NAND of an embodiment in which the dimension of the channel width W is adjusted. [Figure 9] (A) shows a circuit diagram of a Multi-stacked Body-bias NAND (MSBB-NAND), (B) shows a symbolic representation of a 1SBB-NAND, and (C) shows the 1SBB-NAND in (A) with FB-INV clearly indicated. [Figure 10]1 is a longitudinal sectional view of a semiconductor chip on which a MOS transistor circuit having an example of a structure for controlling a substrate potential (body voltage) is manufactured. [Figure 11] These are symbolic representations of MSBB-NAND. (A) is a symbolic representation of a 1SBB-NAND gate with one stage of stacked NAND as shown in FIG. 9. (B) is a symbolic representation of a 2SBB-NAND gate with a second stage of NAND recursively stacked with respect to the first stage of NAND in (A). (C) is a symbolic representation of a 3SBB-NAND gate with a third stage of NAND recursively stacked with respect to the second stage of NAND in (B). [Figure 12] This is a circuit diagram of a single-stage MS-NOR (i.e., 1S-NOR) among multi-stacked NOR gates (MS-NOR). [Figure 13] 6, which shows MS-NOR in symbolic notation; (A) is a symbolic notation of a 1S-NOR gate with one stage of stacked NOR; (B) is a symbolic notation of a 2S-NOR gate with a second stage of NOR recursively stacked with the first stage of NOR in (A); and (C) is a symbolic notation of a 3S-NOR gate with a third stage of NOR recursively stacked with the second stage of NOR in (B). [Figure 14] These are circuit diagrams of MSBB-NOR corresponding to Figure 11 showing MSBB-NAND. (A) is a circuit diagram of a 1SBB-NOR gate stacked by one stage, (B) is a symbolic representation of (A), (C) is a symbolic representation of 2SBB-NOR, and (D) is a symbolic representation of 3SBB-NOR. [Figure 15] FIG. 1 illustrates the simulation conditions, where (A) is a truth table and (B) is a diagram showing the relationship between input B and output Y. [Figure 16]This is a characteristic diagram of output Y, which is part of the test results for MS-NAND. (A) shows a comparative example, (B) shows the voltage change of each output Y for the NAND of the comparative example and the MS-NAND of the embodiment, and (C) shows the voltage change of each output Y for the NAND, BB-NAND of the comparative example and the MSBB-NAND of the embodiment. [Figure 17] This is a table summarizing all the test result data for NAND and NOR. [Figure 18] FIG. 1 is a diagram for explaining a conventional stacked inverter (SI), where (A) shows a circuit diagram of an inverter INV, (B) shows a circuit diagram of an SI, and (C) is a symbolic representation of (B). [Figure 19] FIG. 1 is a diagram for explaining a conventional BBI; (A) shows a circuit diagram of an inverter INV, (B) shows a circuit diagram of a BBI, and (C) is a symbolic representation of (B). [Figure 20] FIG. 1 is a diagram for explaining a conventional SBBI; (A) shows a circuit diagram of an inverter INV, (B) shows a circuit diagram of an SBBI, and (C) is a symbolic representation of (B). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The present invention relates to a logic circuit technology that enables logic circuits that realize, for example, NAND and NOR to operate with an extremely low voltage power supply, and mainly applies stack (S) technology and body bias (BB) technology to logic circuits such as NAND and NOR. First, a NAND gate will be described, and then a NOR gate will be described. Figures 1 to 11 are directed to a NAND gate, and Figures 12 to 14 are directed to a NOR gate. Figures 15 to 17 show test data by simulation to confirm low-voltage operating performance.

[0022] FIG. 1 is a diagram explaining a NAND gate; (A) is a circuit diagram of a NAND gate with two inputs and one output, and (B) is its truth table. A NAND gate is a parallel circuit made up of two PMOS transistors and a series circuit made up of two NMOS transistors connected in series with their sources S positioned on the outside, with a power supply terminal Vdd provided on the parallel circuit side at both ends of the outside, and a ground terminal Vss provided on the series circuit side. The two input terminals A and B are connected to the gates G of one of the PMOS transistors and one of the NMOS transistors, and the gates G of the other PMOS transistor and the other NMOS transistor. The output terminal Y is the connection point between the parallel circuit and the series circuit.

[0023] Next, the relationship between the output Y of the NAND gate and the levels "0" and "1" of the power supply terminal and ground terminal taking into account the leakage current of the MOS transistor will be analyzed using Figures 2 to 4. Note that when simply referring to a MOS transistor, this does not mean to distinguish between N-type and P-type.

[0024] Fig. 2(A) is a diagram explaining the input / output logic, and Fig. 2(B) is a state diagram explaining the voltage of the source terminal determined by the output logic. Fig. 3(A) is a diagram explaining the preferable voltage of the source terminal to suppress the leak path that deteriorates the output logic, and Fig. 3(B) is a diagram explaining the preferable voltage of the source terminal of the MOS transistor in the off state to suppress the leak path on the parallel circuit side when the output Y is "1". Fig. 4 is a diagram showing the relationship between the output Y and the levels of all the source terminals for each state of the two inputs A and B.

[0025] Figure 2(A) shows the input / output logic for two inputs, and as shown in the truth table, it is (A,B,Y)=(0,0,1),(0,1,1),(1,0,1),(1,1,0). The voltages of the source terminals of the PMOS transistors (1) and (2) at the power supply end and the source terminal of the NMOS transistor (4) at the ground end, which are determined by the input / output logic at this time, are as shown in Figure 2(B), when the output Y is "1", at least one of the source terminals on the parallel circuit side is "1", and conversely, when the output Y is "0", the two NMOS transistors (3) and (4) on the series circuit side are on, i.e., the source terminals on the ground end are "0".

[0026] In FIG. 2B, when the output Y is "1", at least one of the NMOS transistors (3) and (4) on the series circuit side is turned off, and when the output Y is "0", both the PMOS transistors (1) and (2) on the parallel circuit side are turned off. When the MOS transistor operates in the subthreshold region, the voltage at the output terminal Y is determined by the balance between the inflow and outflow currents of the drain current of the MOS transistor in the on state and the leakage current of the MOS transistor in the off state. Therefore, if the leakage current is large, the output voltage will deteriorate. Meanwhile, the drain current decreases when the drain-source voltage is decreased. In other words, when the output Y is "1", if the drain-source voltage of the NMOS transistor is decreased, the leakage current will be reduced and the output Y can be maintained at "1". Also, when the output Y is "0", if the drain-source voltage of the PMOS transistor is decreased, the leakage current will be reduced and the output can be maintained at "0".

[0027] Therefore, referring to Figure 3(A), we will consider the preferred voltage of the source terminal to suppress the leak path that degrades the output logic. When the output Y is "1", it is clear that in order to suppress the leak path on the series circuit side, it is sufficient to set "1" at the ground terminal and lower the potential between the output terminal Y. Similarly, when the output Y is "0", it is clear that in order to suppress the leak path on the parallel circuit side, it is sufficient to set "0" at the power terminal and lower the potential between the output terminal Y.

[0028] Furthermore, as shown in FIG. 3(B), when the output Y is “1”, the source terminal of the PMOS transistor in the parallel circuit that is in the off state, i.e., the power supply terminal, is set to “1” to minimize the leakage current flowing between the output Y.

[0029] According to the above, the voltages of all source terminals for suppressing leakage paths corresponding to the state of the two inputs are (output Y: power terminal, ground terminal) = (1:1,1), (1:1,1), (1:1,1), (0:0,0) when shown as the output Y, the power terminal to which the source terminals of the two PMOS transistors (1) and (2) are connected, and the ground terminal which is the source terminal of the NMOS transistor (4) as shown in FIG. 4. In other words, it was analyzed that the levels of the power terminal and the ground terminal can be treated as the same level as the level of the output Y in all states of the inputs A and B. This means that a circuit identical to a NAND gate, which is a logic circuit (that is, which has a different dimension of the channel width W as described later), can be stacked at the power terminal and ground terminal as a circuit (control circuit) that controls the power supply, and it was further found that the logic circuit and the power supply control circuit can be designed in the same configuration as a semiconductor circuit or as an integrated element thereof.

[0030] FIG. 5 shows a circuit diagram of a single-stage MS-NAND (i.e., 1S-NAND) among the Multi-Stacked NAND gates (MS-NAND). The 1S-NAND includes a main NAND (Main-NAND) 10, a power supply side NAND (High-Side NAND) 11, and a ground side NAND (Low-Side NAND) 12. The power supply side NAND 11 and the ground side NAND 12 have the same configuration as the main NAND 10, and function as a control circuit for the first stage power supply. The power supply side NAND 11 has a connection terminal 111 corresponding to the output terminal Y connected to the power supply terminal 101 of the main NAND 10, and the ground side NAND 12 has a connection terminal 121 corresponding to the output terminal Y connected to the ground terminal 102 of the main NAND 10. The 1S-NAND is configured such that the output voltage of a thermoelectric conversion element (not shown) is smoothed and input to the power supply terminal Vdd of the first stage power supply side NAND 11 and the ground side NAND 12.

[0031] Regarding the operation of the 1S-NAND, the drain current of the MOS transistor in the subthreshold region decreases when the drain-source voltage is decreased. More specifically, when the output Y is “1”, if “1” is set to the ground terminal 102, the voltage difference between the drain and source of the NMOS transistors 3 and 4 disappears, so that the leakage current becomes small and the output Y can be kept at “1”. Conversely, when the output Y is “0”, if “0” is set to the power terminal 101, the voltage difference between the drain and source of the PMOS transistors 1 and 2 disappears, so that the leakage current becomes small and the output can be kept at “0”. In this way, by setting the voltages of the connection terminals 111 and 121 of the power supply side NAND 11 and the ground side NAND 12 as shown in FIG. 4, the leakage current flowing through the output terminal Y is suppressed and the deterioration of the output voltage is improved.

[0032] Figure 6 is a symbolic representation of MS-NAND, where (A) is a symbolic representation of a 1S-NAND gate with one stage of NAND shown in Figure 5, (B) is a symbolic representation of a 2S-NAND gate with a second stage of NAND recursively stacked on the first stage of NAND in (A), and (C) is a symbolic representation of a 3S-NAND gate with a third stage of NAND recursively stacked on the second stage of NAND in (B). Note that some of the symbols have been omitted for ease of illustration.

[0033] 6B and 6C, a recursive stack structure is adopted for the previous stage NAND to connect the next stage NAND, and the output voltage from the thermoelectric conversion element is input to the power supply terminal Vdd of the last stage NANDs 31 and 32, so that the voltage degradation of the output (connection terminal) of successive NANDs from the last stage side is successively suppressed, and as a result, the main NAND 10 can efficiently prevent degradation of the output Y. Note that the number of stages is not limited to three stages, and may be four or more stages.

[0034] Here, the parameters of the MOS transistors constituting the NANDs 11 and 12 connected to the power supply terminal 101 and the ground terminal 102 of the main NAND 10 will be described with reference to FIG.

[0035] 7 is a schematic vertical sectional perspective view for explaining a partial structure of an NMOS transistor, for example. + Two diffusion layers 41, 42 made of a semiconductor material are formed at a predetermined distance apart. One of the diffusion layers 41, 42 is fabricated as a source and the other as a drain. The two diffusion layers 41, 42 have predetermined dimensions in the length direction, which is the left-right direction in the drawing, and in the depth direction, which is perpendicular to the length direction. On the upper surface of a P-type Si substrate 40, oxide films 43, 44 forming an insulating layer except for the diffusion layers 41, 42, and a central gate oxide film 45 are formed. A gate 46 made of a metal material is formed on the upper surface of the gate oxide film 45. The lengthwise separation dimension of the diffusion layers 41, 42 is called a channel length L, and the depthwise dimension is called a channel width W.

[0036] The drain current of a MOS transistor can be controlled by setting the channel length L and channel width W of the MOS transistor. The drain current I is expressed as follows: There is a relationship I∝W / L, and by adjusting the channel width W, it is possible to increase or decrease the drain current I.

[0037] In this embodiment, the power supply side NAND 11 connected to the power supply end 101 of the main NAND 10 needs to supply current flowing through the PMOS transistors 1 and 2 of the main NAND 10, so the channel width W of the PMOS transistor is designed to be wider than the channel width of the PMOS transistors 1 and 2 of the main NAND 10. Also, the ground side NAND 12 connected to the ground end of the main NAND 10 needs to pass the current flowing through the NMOS transistors 3 and 4 of the main NAND 10 to the ground end 102, so the channel width W of the NMOS transistor is designed to be wider than the channel width of the main NAND 10. Here, the channel widths W of the power supply side NAND 11 and the ground side NAND 12 are designed to be at least greater than the channel width of the main NAND 10, for example, twice as large. In this case, the number of parallel transistors is equivalently doubled. In addition, by applying a recursive stack structure to the power supply side NAND 11 and ground side NAND 12 stacked on the main NAND 10, as shown in Figure 8 (B) described below, it is possible to further reduce leakage current and improve low-voltage operating performance.

[0038] 8A and 8B are circuit diagrams of an MS-NNAND according to an embodiment in which the dimensions of the channel width W are adjusted, where (A) is a circuit diagram of a 1S-NAND and (B) is a circuit diagram of a 2S-NAND. The dimensions of the channel width W of the PMOS transistors of the parallel circuit 112 of the first stage power supply side NAND surrounded by a solid line frame in FIG. 8A and the parallel circuit 212 of the second stage power supply side NAND surrounded by a dashed line in FIG. 8B are set to be sequentially increased (e.g., 2 times, 4 times, 8 times, etc.) compared to the channel width W of the PMOS transistors of the parallel circuit of the power supply side NAND immediately preceding the stage. Also, as illustrated in FIGS. 8A and 8B, the dimensions of the channel width W of the NMOS transistors of the series circuit 122 of the first stage ground side NAND and the series circuit 222 of the second stage ground side NAND are set to be sequentially increased compared to the channel width W of the NMOS transistors of the series circuit of the ground side NAND immediately preceding the stage. By applying a recursive stack structure to the power supply side NAND 11 and ground side NAND 12 stacked on the main NAND 10, it is possible to further suppress leakage current and improve low voltage operation performance. Note that the increase ratio of the channel width W of the PMOS and NMOS transistors of the power supply side NAND and the ground side NAND may be the same or different.

[0039] In FIG. 9, (A) shows a circuit diagram of Multi-stacked Body-bias NAND (MSBB-NAND), (B) shows a symbolic representation of MSBB-NAND, and (C) shows a symbolic representation of (A). MSBB-NAND is a logic circuit that employs a stack structure and a body-bias (BB) structure in the NAND gate, and here it is applied to a circuit of a single-stage 1SBB-NAND out of the MSBB-NAND. The BB technology does not compete with the stack technology shown in FIG. 5 to FIG. 8, so both technologies can be used together. The BB technology and its operation are explained below.

[0040] 1SBB-NAND is equipped with a 1S-NAND in the front stage and a feedback inverter (FB-INV) in the rear stage, and the output Y of the 1S-NAND is inverted by the FB-INV and fed back to the substrate potential of each MOS transistor of the 1S-NAND. By feeding back the output of the FB-INV as the substrate potential of the 1S-NAND, the threshold voltage of the MOS transistor is controlled and degradation of the output voltage of the output Y is suppressed. In FIG. 9(A), for the sake of illustration, the MOS transistor in the upper right corner of the 1S-NAND is shown as a representative body bias structure.

[0041] Here, the relationship between the threshold voltage and the drain current of a MOS transistor in the subthreshold region will be explained based on Equation 1.

[0042]

number

[0043] In equation (1), I0 (=μC OX (W / L)(η-1)V T 2 ) is the prefactor of the subthreshold current, μ is the carrier mobility, and C OX (=ε OX / t OX ) is the gate oxide capacitance per unit area, ε OX is the dielectric constant of the oxide film, t OX is the oxide thickness, L is the channel length, W is the channel width, η is the subthreshold slope factor, V T (=k B T / q) is the thermal voltage, k B is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, V GS is the gate-source voltage, V DS is the drain-source voltage.

[0044] Equation (2) expresses the threshold voltage V TH In formula (2), V BS is the body-source voltage, V TH0 is V BS= 0V, Φ S is the surface state, and K1 and K2 are terms due to non-uniform doping in the vertical direction. From equation (2), the body bias voltage V BN Lowering the threshold voltage V THN rises, while V BN If you increase V THN Also, in pMOS transistors, the body bias voltage V BP If you increase V THP rises, while V BP Lowering V THP From equation (1), the threshold voltage V TH The lower the value, the easier it is for the drain current, i.e., the on-current, to flow.

[0045] Fig. 10 is a vertical cross-sectional view of a semiconductor chip on which a MOS transistor circuit having an example of a structure for controlling a substrate potential (body voltage) is manufactured. In Fig. 10, an NMOS transistor and a PMOS transistor are manufactured on the left and right sides of a P-type Si substrate 50. Usually, the source terminal and the body terminal of a MOS transistor are formed in common. On the other hand, in a MOS transistor for controlling a body bias, the body terminal and the source terminal made of a metal wiring 51 are separated by separation parts 52 and 53.

[0046] Furthermore, since a PMOS transistor is separated from the p-type silicon substrate by an n-well, separate voltages can be applied to the source terminal and the body terminal. On the other hand, in the case of an NMOS transistor, the p-type silicon substrate and the body terminal are common, so the voltage cannot be freely set in this state. Therefore, if you want to control the voltage of the body terminal of an NMOS transistor, you need to separate the p-type silicon substrate from the body terminal. The p-type silicon substrate and the body terminal are separated by n-wells 54 and 55 and deep-n-well 56. This structure makes it possible to input the FB-INV feedback voltage between the body terminal and the source terminal.

[0047] Returning to FIG. 9, the substrate potential control method is as follows: when the output Y is “1”, the feedback voltage is inverted and input, so that the threshold voltage of the PMOS transistor is lowered and the threshold voltage of the NMOS transistor is higher, and the PMOS transistor in the on-state is more likely to pass current. As a result, the on-current increases and the Y output can be kept at “1”. Conversely, when the output Y is “0”, the feedback voltage is inverted and input, so that the threshold voltage of the PMOS transistor is higher and the threshold voltage of the NMOS transistor is lowered, and the NMOS transistor in the on-state is more likely to pass current. As a result, the on-current increases and the Y output can be kept at “0”. In this way, by feeding back the inverted logic of the output Y between the source and body, the threshold voltage of the MOS transistor in the on-state is always controlled to be lowered, thereby increasing the on-current Ion of the MOS transistor, and reducing the ratio of the off-current Ioff to the on-current Ion, thereby preventing deterioration of the output voltage.

[0048] FIG. 11 is a symbolic representation of MSBB-NAND, where (A) is a symbolic representation of a 1SBB-NAND gate having one stage of stacked NAND as shown in FIG. 9, (B) is a symbolic representation of a 2SBB-NAND gate having a second stage of NAND recursively stacked with respect to the first stage of NAND in (A), and (C) is a symbolic representation of a 3SBB-NAND gate having a third stage of NAND recursively stacked with respect to the second stage of NAND in (B).

[0049] 12 to 14 show an embodiment in which a stack structure and body bias (BB) control are applied to a NOR gate. FIG. 12 shows a circuit diagram of a single-stage MS-NOR (i.e., 1S-NOR) among multi-stacked NOR gates (MS-NOR). The 1S-NOR includes a main-NOR 10a, a first-stage power supply side NOR 11a, and a ground side NOR 12a. The main NOR 10a includes a series circuit of two PMOS transistors and a parallel circuit of two NMOS transistors, and the series circuit and the parallel circuit are connected in series so that the sources are located at both ends. The power supply side NOR 11a and the ground side NOR 12a have the same configuration as the main NOR 10a, and function as a control circuit for the power supply of the first stage. The power supply side NOR 11a has a connection terminal corresponding to the output terminal Y connected to the power supply terminal of the main NOR 10a, and the ground side NOR 12a has a connection terminal corresponding to the output terminal Y connected to the ground terminal of the main NOR 10a. The 1S-NOR is configured such that the output voltage of a thermoelectric conversion element (not shown) is smoothed and input to each power supply terminal Vdd of the first-stage power supply side NOR 11a and ground side NOR 12a.

[0050] The 1S-NOR outputs "1" only when all inputs are "0", and outputs "0" when there is even one "1". For the MS-NOR, by stacking the power supply side NOR 11a and ground side NOR 12a, which have the same configuration as the main NOR 10a, at the power supply end and ground end, it is possible to suppress the leakage current flowing through the output end Y for the state of each of the inputs A and B, and improve degradation of the output voltage.

[0051] Fig. 13 is a diagram of MS-NOR in symbolic notation corresponding to Fig. 6 showing MS-NAND, where (A) is a diagram of a 1S-NOR gate with one-stage stacked NOR, (B) is a diagram of a 2S-NOR gate with a second-stage NOR recursively stacked with respect to the first-stage NOR in (A), and (C) is a diagram of a 3S-NOR gate with a third-stage NOR recursively stacked with respect to the second-stage NOR in (B). Fig. 14 is a circuit diagram of MSBB-NOR corresponding to Fig. 11 showing MSBB-NAND, where (A) is a circuit diagram of a one-stage stacked 1SBB-NOR gate, (B) is a diagram of (A) in symbolic notation, (C) is a diagram of a 2SBB-NOR, and (D) is a diagram of a 3SBB-NOR. The logic circuits of MS-NOR and MSBB-NOR in FIG. 13 and FIG. 14 can also improve the extremely low voltage operation performance, similar to the case of MS-NAND and MSBB-NAND.

[0052] 15 to 17 show the contents of the evaluation test by simulation performed on each embodiment of MS-NAND, MSBB-NAND, MS-NOR, and MSBB-NOR. The evaluation test was performed by simulation evaluation using deep n-well option with 0.18 μm standard CMOS technology for the logic circuit of each embodiment.

[0053] I. Simulation Conditions A test was conducted to evaluate the voltage change of the output Y when one of the inputs A and B was changed for the NAND gate shown in the truth table of FIG. 15(A) and the NOR gate not shown. In this test, the power supply voltage Vdd was set to 50 mV, and as shown in FIG. 15(B), the input A was fixed to 50 mV, while the input B was changed in the range of 0-50 mV, and the voltage characteristics and the amplitude of the output Y were examined. For the configuration using the stack structure, the channel width W was designed to be doubled in sequence for each stage. A test was also conducted in which the inputs A and B were swapped. In addition, normal NAND, NOR, BB-NAND, and BB-NOR were used as comparative examples. In addition, a low-voltage operating 1S-BB inverter was used for the FB-INV applied to the BB-NAND and MSBB-NAND.

[0054] II. Test Results Fig. 16 is a characteristic diagram of output Y, which is part of the test results for the MS-NAND gate, and shows the voltage of output Y on the vertical axis versus the voltage of input B on the horizontal axis. Fig. 16(A) is a comparative example, where waveform (1) shows the voltage change of output Y of NAND, and waveform (2) shows the voltage change of output Y of BB-NAND.

[0055] 16B shows the voltage change of each output Y of the NAND of the comparative example and the MS-NAND of the embodiment. Waveform (1) shows the voltage change of the output Y of the NAND of the comparative example, waveform (2) shows the voltage change of the output Y of the S-NAND with a single-stack structure, waveform (3) shows the voltage change of the output Y of the 2S-NAND with a two-stack structure, and waveform (4) shows the voltage change of the output Y of the 3S-NAND with a three-stack structure.

[0056] FIG. 16C shows the voltage change of each output Y of the NAND and BB-NAND of the comparative example and the MSBB-NAND of the embodiment.

[0057] Figure 17 is a table summarizing all the test result data for NAND and NOR. In Figure 17, each item indicates, starting from the Logic Gates at the top, the type of logic circuit, the specific logic circuit, the number of stack stages, the number of MOS transistors included in the logic circuit, the maximum voltage of the output Y of each NAND gate when the input A side is changed, the maximum voltage of the output Y of each NAND gate when the input B side is changed, the maximum voltage of the output Y of each NOR gate when the input A side is changed, and the maximum voltage of the output Y of each NOR gate when the input B side is changed.

[0058] III. Discussion It was found that the voltage amplitude under the input condition where the output Y becomes "1" is improved as the number of stack stages is increased in both the NAND side and the NOR side according to the embodiment, compared to normal NAND, NOR, and BB-NAND, BB-NOR. For example, in a simulation in which the amplitude of the input B on the NAND side was changed, the amplitude was 32.4 mV in normal NAND, and 38.2 mV in 1S-NAND, an improvement of 18%. In addition, since the amplitude of BB-NAND was 37.1 mV at this time, it was found that the 1S-NAND was further improved than the BB-NAND. Furthermore, in the MS-NAND, the amplitude of the output Y increased as the number of stack stages increased, and the maximum amplitude of 3S-NAND was 44.3 mV, an improvement of 37%. It was confirmed that such a tendency was also shown in the simulation in which the amplitude of the input A was changed.

[0059] In addition, in a simulation in which the amplitude of input B on the NOR side was changed, the output was 33.0 mV for a normal NOR, while the output was 38.6 mV for the 1S-NOR, a 17% improvement. At the same time, the output was 37.4 mV for the BB-NOR, so the 1S-NOR was found to have been an even greater improvement than the BB-NOR. Furthermore, in the MS-NOR, the amplitude of output Y increased as the number of stack stages increased, and the maximum output was 44.8 mV for the 3S-NOR, a 36% improvement. This tendency was also observed in a simulation in which the amplitude of input A was changed.

[0060] Next, in a simulation in which the amplitude of input B was changed for MSBB-NAND, the amplitude of output Y increased by 13% compared to 37.1mV for normal BB-NAND, which was 42.1mV for 1SBB-NAND. In addition, the amplitude of output Y increased with the number of stack stages for MSBB-NAND, reaching 47.0mV for the maximum 3SBB-NAND, which was 45% better than normal NAND and 27% better than normal BB-NAND. This tendency was also observed in a simulation in which the amplitude of input A was changed.

[0061] In addition, as can be seen from Figures 16(B) and (C), the voltage level when the output Y becomes "0" is lower in MS-NAND and MSBB-NAND than in normal NAND and BB-NAND, and becomes even lower as the number of stack stages increases, making the "0" output more stable.

[0062] Finally, for MSBB-NOR, in a simulation in which the amplitude of input B was changed, the amplitude of output Y increased by 13% compared to 37.4mV for normal BB-NOR, and 42.3mV for 1SBB-NAND. In addition, the amplitude of output Y increased with the number of stack stages in MSBB-NOR, reaching 47.2mV for the maximum 3SBB-NOR, a 43% improvement over normal NOR and a 26% improvement over normal BB-NAND. This tendency was also observed in a simulation in which the amplitude of input A was changed.

[0063] In this embodiment, the logic circuit applied to a wearable device has been described, but it can also be applied to semiconductor logic circuits incorporated in various industrial IoT devices. In addition, in this embodiment, the stack structure and body bias technology are applied to both the power supply side and the ground side, but it may be applied to only one of the power supply sides. [Explanation of symbols]

[0064] 1,2 PMOS transistor 3,4 NMOS transistor 10 Main NAND 101 Power supply end 102 Ground end 11,12 1st row NAND 21,22 Second stage NAND 31,32 3rd row NAND 13 FB-INV W Channel width 52, 53 Separation part 10a Main NOR 11a,12a 1st stage NOR

Claims

1. a logic circuit including a plurality of MOS transistors connected together to form a circuit having a plurality of inputs and one output terminal, the logic circuit having a power supply terminal and a ground terminal for supplying power to the circuit; a first stage first and second control circuits having the same configuration as the logic circuit and controlling a current flowing through the one output terminal of the logic circuit; the first control circuit of the first stage has a connection terminal corresponding to the one output terminal connected to the power supply terminal of the logic circuit; The first stage second control circuit is a semiconductor logic circuit having a connection terminal corresponding to the one output terminal connected to the ground terminal of the logic circuit.

2. a first and second control circuit of a second stage having the same configuration as the logic circuit and controlling a current flowing through a connection terminal of the first control circuit of the first stage, and a third and fourth control circuit of the second stage controlling a current flowing through a connection terminal of the second control circuit of the first stage; a connection terminal of the second stage first control circuit is connected to a power supply terminal of the first stage first control circuit; a connection terminal of the second control circuit of the second stage is connected to a ground terminal of the first control circuit of the first stage; a connection terminal of the third control circuit of the second stage is connected to a power supply terminal of the second control circuit of the first stage; 2. The semiconductor logic circuit according to claim 1, wherein a connection terminal of the fourth control circuit of the second stage is connected to a ground terminal of the second control circuit of the first stage.

3. The circuit includes a first circuit having a plurality of MOS transistors on the power supply terminal side, and a second circuit having a plurality of MOS transistors on the ground terminal side, a plurality of MOS transistors in a circuit corresponding to the first circuit in the first stage first control circuit have a source-drain channel width that is more than one time a source-drain channel width of the plurality of MOS transistors in the first circuit of the logic circuit; 2. The semiconductor logic circuit according to claim 1, wherein a plurality of MOS transistors in a circuit corresponding to the second circuit in the first stage second control circuit have source-drain channel widths that are more than one time larger than source-drain channel widths of a plurality of MOS transistors in the second circuit of the logic circuit.

4. The circuit includes a first circuit having a plurality of MOS transistors on the power supply terminal side, and a second circuit having a plurality of MOS transistors on the ground terminal side, a plurality of MOS transistors in a circuit corresponding to the first circuit in the first stage first control circuit have a source-drain channel width that is more than one time a source-drain channel width of the plurality of MOS transistors in the first circuit of the logic circuit; a plurality of MOS transistors in a circuit corresponding to the second circuit in the first stage second control circuit have a source-drain channel width that is more than one time a source-drain channel width of a plurality of MOS transistors in the second circuit of the logic circuit; a plurality of MOS transistors in a circuit corresponding to the first circuit in the second stage first control circuit have a source-drain channel width that is more than one time a source-drain channel width of a plurality of MOS transistors in a circuit corresponding to the first circuit in the first stage first control circuit; a plurality of MOS transistors in a circuit corresponding to the second circuit in the second stage second control circuit have a source-drain channel width that is more than one time a source-drain channel width of a plurality of MOS transistors in a circuit corresponding to the second circuit in the first stage second control circuit; a plurality of MOS transistors in a circuit corresponding to the first circuit in the third control circuit in the second stage have a source-drain channel width that is more than one time a source-drain channel width of a plurality of MOS transistors in a circuit corresponding to the first circuit in the second control circuit in the first stage; 3. The semiconductor logic circuit according to claim 2, wherein a plurality of MOS transistors in a circuit corresponding to the second circuit in the fourth control circuit of the second stage have source-drain channel widths that are more than one time larger than source-drain channel widths of a plurality of MOS transistors in a circuit corresponding to the second circuit in the second control circuit of the first stage.

5. 2. The semiconductor logic circuit according to claim 1, wherein the logic circuit is a NAND circuit.

6. 2. The semiconductor logic circuit according to claim 1, wherein the logic circuit is a NOR circuit.

7. an inverter having an input terminal connected to the one output terminal of the logic circuit; 2. The semiconductor logic circuit according to claim 1, wherein the inverter has an output terminal for feeding back an output to a substrate potential of each MOS transistor constituting the logic circuit and the first stage control circuit.

8. an inverter having an input terminal connected to the one output terminal of the logic circuit; 3. The semiconductor logic circuit according to claim 2, wherein said inverter has an output terminal for feeding back an output to a substrate potential of each of MOS transistors constituting said logic circuit, said first stage control circuit and said second stage control circuit.

9. A semiconductor integrated circuit in which the semiconductor logic circuit according to any one of claims 1 to 8 is integrated.

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