Semiconductor element

Abstract

To provide a semiconductor element capable of preventing current leakage from below a source / drain, and a manufacturing method thereof.SOLUTION: A semiconductor device according to the present invention includes a lower pattern layer including a first semiconductor material, a first conductive type doped pattern layer disposed on the lower pattern layer and including a semiconductor material doped with a first conductive type impurity, a source / drain pattern disposed on the first conductive type doped pattern layer and including a semiconductor material doped with a second conductive type impurity different from the first conductive type impurity, a channel pattern connecting the source / drain patterns and stacked at a distance from each other, including a semiconductor pattern including a second semiconductor material different from the first semiconductor material, and a gate pattern disposed on the first conductive type doped pattern layer, crossing between the source / drain patterns, and surrounding the channel pattern.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device capable of preventing current leakage from below a source / drain and a method for manufacturing the same. [Background technology]

[0002] A semiconductor is a material that is intermediate between a conductor and a non-conductor, and is a material that conducts electricity under certain conditions. Such semiconductor materials can be used to manufacture various semiconductor devices, such as memory devices. Such semiconductor devices can be used in a variety of electronic devices.

[0003] 2. Description of the Related Art As the electronics industry develops to a high level, the requirements for the properties of semiconductor devices are becoming higher and higher. For example, there is an ever-increasing demand for semiconductor devices with higher reliability, higher speeds, and / or more functionality.

[0004] In order to satisfy such required characteristics, the structures within semiconductor elements are becoming increasingly complex and highly integrated. For example, there is a problem of source / drain unetching in devices with reduced dimensions. Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned problems in conventional semiconductor devices, and an object of the present invention is to provide a semiconductor device which can solve the problem of source / drain unetching, prevent current leakage from below the source / drain, and easily realize a structure in which the entire lower substrate is removed (BSPDN bulk-less) when a BSPDN (backside power distribution network) structure is applied through etching selectivity. [Means for solving the problem]

[0006] The present invention provides a semiconductor device having a first semiconductor material, comprising: a lower pattern layer including a first semiconductor material; a first conductive type doped pattern layer disposed on the lower pattern layer and including a semiconductor material doped with a first conductive type impurity; a source / drain pattern disposed on the first conductive type doped pattern layer and including a semiconductor material doped with a second conductive type impurity different from the first conductive type impurity; a channel pattern including a semiconductor pattern including a second semiconductor material different from the first semiconductor material, stacked apart from each other and connecting the source / drain patterns; and a gate pattern disposed on the first conductive type doped pattern layer, crossing between the source / drain patterns and surrounding the channel pattern.

[0007] In order to achieve the above object, a semiconductor device according to the present invention includes a lower pattern layer including a first semiconductor material, a first conductive type doped pattern layer disposed on the lower pattern layer and including a semiconductor material doped with a first conductive type impurity, a source / drain pattern disposed on the first conductive type doped pattern layer and including a semiconductor material doped with a second conductive type impurity different from the first conductive type impurity, a channel pattern connecting the source / drain patterns and stacked at a distance from each other, including a semiconductor pattern including a second semiconductor material different from the first semiconductor material, a gate pattern disposed on the first conductive type doped pattern layer, crossing between the source / drain patterns and surrounding the channel pattern, and a lower contact electrode disposed under the source / drain pattern, penetrating the lower pattern layer and the first conductive type doped pattern layer, and connected to the source / drain pattern.

[0008] In order to achieve the above object, a semiconductor device according to the present invention includes a first conductive type doped pattern layer including a semiconductor material doped with a first conductive type impurity, a source / drain pattern disposed on the first conductive type doped pattern layer and including a semiconductor material doped with a second conductive type impurity different from the first conductive type impurity, a channel pattern including semiconductor patterns stacked apart from each other and connecting the source / drain patterns, a gate pattern disposed on the first conductive type doped pattern layer, crossing between the source / drain patterns and surrounding the channel pattern, and a lower contact electrode disposed under the source / drain pattern, penetrating the first conductive type doped pattern layer, and connected to the source / drain pattern. Effect of the Invention

[0009] According to the semiconductor device of the present invention, since etching can be formed deeply even in a device having a reduced size, the problem of source / drain being unetched can be solved and current leakage from the lower part of the source / drain can be prevented. In addition, when a backside power distribution network (BSPDN) structure is applied, a structure in which the lower substrate is entirely removed (BSPDN bulk-less) can be easily realized through etching selectivity. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view showing a semiconductor device according to an embodiment of the present invention; [Figure 2A] 2 is a cross-sectional view taken along the line XX' in FIG. [Figure 2B] 2 is a cross-sectional view taken along line YY' in FIG. [Figure 2C] 2 is a cross-sectional view taken along line ZZ' in FIG. [Diagram 3]3 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention, corresponding to the cross-sectional view taken along line XX' in FIG. 2. [Figure 4A] 2B is a cross-sectional view corresponding to FIG. 2A, illustrating a semiconductor device according to another embodiment of the present invention. [Figure 4B] 2B is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention; FIG. [Figure 5A] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5B] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6A] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6B] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7A] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7B] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8A] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8B] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9A] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9B] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10A] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10B]1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11A] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11B] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12A] 4A to 4C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 12B] 4A to 4C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 13A] 4A to 4C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 13B] 4A to 4C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 14A] 4A to 4C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 14B] 4A to 4C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 15] 4A to 4C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 16] 4A to 4C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 17] 4A to 4C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 18] 4A to 4C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 19] 4A to 4C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 20A]1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 20B] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 21] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 23A] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 23B] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 24A] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 24B] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 25A] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 25B] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 26A] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 26B] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 27A] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 27B] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 28A]1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 28B] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 29A] 4A to 4C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 29B] 4A to 4C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Next, specific examples of embodiments for carrying out a semiconductor device according to the present invention will be described with reference to the drawings. As those skilled in the art will realize, the described embodiments may be implemented in various different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly explain the present invention, parts not necessary for the explanation will be omitted, and the same reference numerals will be used throughout the specification to refer to the same or similar components. Furthermore, the size and thickness of each component shown in the drawings are shown arbitrarily for convenience of explanation, and the present invention is not limited to the drawings. For convenience of explanation and / or ease of illustration, the thicknesses of some layers and regions have been enlarged or exaggerated.

[0012] In addition, when a part such as a layer, film, region, or plate is said to be "on" or "above" another part, this includes not only the case where it is "directly on" the other part, but also the case where there is another part in between. Conversely, when one part is said to be "directly above" another, it means that there is no other part in between. In addition, being "above" or "on" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" or "on" the direction opposite to gravity. In addition, throughout the specification, when a part "comprises" other elements, this means that the part may further include the other elements, not excluding the other elements, unless otherwise specified. Also, throughout the specification, "on a plane" or "when viewed from a plane" means when the subject part is viewed from above, and "on a cross section" or "when viewed from a cross section" means when the subject part is viewed from the side through a vertical cross section.

[0013] In the drawings relating to a semiconductor device according to an embodiment of the present invention, a transistor including a nanowire or nanosheet, a Multi-Bridge Channel Field Effect Transistor (MBCFET), and a FinFET including a channel region having a fin-shaped pattern are shown as examples, but are not limited thereto. Of course, the semiconductor device according to some embodiments may include a tunneling transistor (tunneling FET), a 3D stack field effect transistor (3DSFET), a complementary field effect transistor (CFET), or the like.

[0014] A semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG. FIG. 1 is a plan view showing a semiconductor device according to one embodiment of the present invention, FIG. 2A is a cross-sectional view taken along line X-X' in FIG. 1, FIG. 2B is a cross-sectional view taken along line Y-Y' in FIG. 1, FIG. 2C is a cross-sectional view taken along line Z-Z' in FIG. 1, and FIG. 3 is a cross-sectional view corresponding to the cross-sectional view taken along line X-X' in FIG. 2 showing a semiconductor device according to another embodiment of the present invention.

[0015] 1, 2A, 2B, and 2C, a semiconductor device 10 according to an embodiment of the present invention includes a lower insulating layer 330, a lower pattern layer 110 disposed on the lower insulating layer 330, a first conductive type doped pattern layer 115 disposed on the lower pattern layer 110, a source / drain pattern 150 disposed on the first conductive type doped pattern layer 115, a channel pattern (CP) disposed between the source / drain patterns 150, and a gate pattern (GS) crossing between the source / drain patterns 150 and surrounding the channel pattern (CP). Optionally, the semiconductor device 10 may further include a first spacer 130 and a second spacer 141 . Optionally, the semiconductor device 10 may further include a gate spacer 140 , a capping layer 145 , an etch stop layer 185 , and an interlayer insulating layer 190 . Optionally, the semiconductor device 10 may further include a lower contact electrode (CT1) and a lower wiring structure (ML1). Optionally, the semiconductor device 10 may further include a first upper contact electrode (UCT1), a second upper contact electrode (UCT2), and an upper wiring structure (ML2).

[0016] The lower insulating layer 330 has an upper surface and a lower surface. The upper and lower surfaces of the lower insulating layer 330 are formed on planes parallel to a first direction (D1) and a second direction (D2) intersecting the first direction (D1). An upper surface of the lower insulating layer 330 faces opposite a lower surface of the lower insulating layer 330 in the third direction D3. Here, the third direction (D3) is a direction intersecting the first direction (D1) and the second direction (D2). For example, the third direction (D3) is the thickness direction of the substrate 100. The lower surface of the lower insulating layer 330 is referred to as the backside of the lower insulating layer 330 . In some embodiments, the logic circuitry of the cell area is implemented on the top surface of the lower insulating layer 330 . Although the lower insulating layer 330 is shown as being a single film, this is for convenience of explanation and is not intended to be limiting.

[0017] As shown in Figures 26A to 27B described below, a semiconductor device 10 according to one embodiment of the present invention is manufactured by removing the substrate 100 using the lower pattern layer 110 as an etch stop layer, and then forming a lower insulating layer 330 on the sheet where the substrate 100 was previously located. Thus, the lower insulating layer 330 may have a shape similar to that of the substrate 100 but may be made of a different material than the substrate 100 . By way of example, the substrate 100 may include, for example, bulk silicon, silicon on insulator (SOI), silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The lower insulating layer 330 may include, for example, an oxide, a nitrate, an oxynitride, or a combination thereof.

[0018] As shown in FIGS. 6A and 6B, the substrate 100 has trenches that define a sacrificial active pattern (AP_P), and a field insulating film 105 is disposed within the trenches. In the process of removing the substrate 100, the field insulating film 105 is also removed. In this case, the lower insulating layer 330 does not include the field insulating film 105 . However, if the field insulating film 105 is not removed together with the substrate 100 during the process of removing the substrate 100 , the lower insulating layer 330 includes the field insulating film 105 . During the process of removing the substrate 100, the sacrificial active pattern AP_P of the substrate 100 is also removed. The lower insulating layer 330 formed in the region where the substrate 100 is located includes some sacrificial active patterns (AP_P), for example, active patterns (AP) having a shape corresponding to the sacrificial active patterns (AP_P) protruding above the field insulating layer 105 .

[0019] The active pattern (AP) has a sheet or fin shape. The active patterns (AP) extend along a first direction (D1) and are spaced apart from each other along a second direction (D2). As an example, the active pattern (AP) is placed in a region where an NMOS is to be formed. As another example, the active pattern (AP) is disposed in the area where the PMOS is to be formed. The active pattern (AP), such as the lower insulating layer 330, may include, for example, oxides, nitrates, oxynitrides, or combinations thereof. The lower pattern layer 110 is disposed on top of the lower insulating layer 330 . The lower pattern layer 110 extends in a first direction D1 like the active patterns AP of the lower insulating layer 330 and is spaced apart from one another in a second direction D2. First spacers 130 are disposed on both sides of the lower pattern layer 110 and the active pattern AP in the second direction D2.

[0020] The lower pattern layer 110 overlaps with a source / drain pattern 150, which will be described later, in a third direction (D3). The lower pattern layer 110 extends in a first direction D1 across a gate pattern GS, which will be described later. The lower pattern layer 110 includes a first semiconductor material having an etching selectivity with respect to the substrate 100 or semiconductor patterns (SP1, SP2, SP3, SP4) described below. As an example, the first semiconductor material may include silicon (Si), germanium (Ge), or a combination thereof, and carbon (C). For example, the first semiconductor material may include germanium (Ge) in a range of 0 at% to 31.5 at%, carbon (C) in a range of more than 0 at% to 2 at% or less, and silicon (Si) in the remaining content.

[0021] As shown in Figures 7A to 11B described below, when forming source / drain recesses (150R) and selectively removing the sacrificial lower pattern (UBP) below the source / drain recesses (150R), the lower pattern layer 110 includes a first semiconductor material having an etching selectivity with the substrate 100 or the semiconductor patterns (SP1, SP2, SP3, SP4), and therefore the lower pattern layer 110 can act as an etch stopper to prevent the substrate 100 or the semiconductor patterns (SP1, SP2, SP3, SP4) from being etched. The first conductive type doped pattern layer 115 is disposed on an upper surface of the lower pattern layer 110 . The first conductive type doped pattern layers 115 extend in a first direction (D1) like the lower pattern layers 110, and are spaced apart from each other in a second direction (D2). The first conductive type doped pattern layer 115 overlaps with a source / drain pattern 150 (to be described later) in a third direction D3.

[0022] The first conductive type doped pattern layer 115 extends in a first direction D1 across a gate pattern GS, which will be described later. The first conductive type doped pattern layer 115 includes a semiconductor material doped with first conductive type impurities. Meanwhile, the source / drain patterns 150, which will be described later, include a semiconductor material doped with a second conductive type impurity different from the first conductive type impurity. That is, the first conductive type doped pattern layer 115 includes an anti-doped semiconductor material opposite to that of the source / drain patterns 150 . The first conductive type doped pattern layer 115 can prevent current from leaking under the source / drain pattern 150, which eliminates the need to reserve space to prevent leakage, thereby allowing the size of the semiconductor device 10 to be further reduced.

[0023] In addition, as shown in Figures 7A to 11B described later, a source / drain recess (150R) may be formed, and the sacrificial lower pattern (UBP) under the source / drain recess (150R) may be selectively removed, and then the first conductive type doped pattern layer 115 and the source / drain pattern 150 may be formed together, or as shown in Figures 12A to 14B described later, the first conductive type doped pattern layer 115 may be formed and then the source / drain pattern 150 may be formed. The first conductive type doped pattern layer 115 can prevent current from leaking under the source / drain pattern 150 . In addition, since the first conductive type doped pattern layer 115 is formed together with the source / drain pattern 150 , the first conductive type doped pattern layer 115 does not hinder the growth of the source / drain pattern 150 . Therefore, it is possible to prevent a decrease in productivity due to the first conductive type doped pattern layer 115 inhibiting the growth of the source / drain pattern 150, a reduction in the stress effect due to the occurrence of defects in the source / drain pattern 150, a reduction in “dopant activation”, and performance degradation due to increased diffusion due to crystal defects.

[0024] The first conductive type doped pattern layer 115 may include, for example, a semiconductor material, such as at least one of silicon (Si) and silicon germanium (SiGe), doped with first conductive type impurities. As an example, when the semiconductor material doped with the second conductive type impurities included in the source / drain pattern 150 includes a semiconductor material doped with n-type impurities, i.e., when the source / drain pattern 150 is located in an NMOS region, the semiconductor material doped with the first conductive type impurities included in the first conductive type doped pattern layer 115 includes a semiconductor material doped with p-type impurities. In addition, when the semiconductor material doped with the second conductive type impurities included in the source / drain pattern 150 includes a semiconductor material doped with p-type impurities, i.e., when the source / drain pattern 150 is located in a PMOS region, the semiconductor material doped with the first conductive type impurities included in the first conductive type doped pattern layer 115 includes a semiconductor material doped with n-type impurities.

[0025] By way of example, the n-type impurities may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. For example, when phosphorus (P) is used as an n-type impurity, phosphorus (P) or phosphine (PH3) is used as an impurity gas, and phosphorus (P) is doped into the semiconductor material through low energy ion implantation, plasma ion implantation, pulsed laser ablation deposition, or the like. The p-type impurities may include boron (B), aluminum (Al), gallium (Ga), indium (In), or combinations thereof. For example, when boron (B) is used as a p-type impurity, boron (B), boron difluoride (BF2), boron trifluoride (BF3), or the like is used as an impurity gas, and boron (B) is doped into the semiconductor material through low-energy ion implantation, plasma ion implantation, pulsed laser ablation deposition, or the like.

[0026] Since the first conductive type doped pattern layer 115 is formed together with the source / drain pattern 150, the first conductive type doped pattern layer 115 is an epilayer formed by a selective epitaxial growth process using the lower pattern layer 110 as a seed. Second spacers 141 are disposed on both sides of the first spacer 130, the first conductive type doped pattern layer 115, and the source / drain patterns 150 in the second direction (D2). At this time, the second spacers 141 cover the entire side of the source / drain patterns 150, but are not limited thereto. The second spacers 141 may cover only a portion of the side of the source / drain patterns 150. That is, the height of the upper end of the second spacer 141 in the third direction (D3) may be the same as the height of the upper end of the source / drain pattern 150 in the third direction (D3), or may be lower than the height of the upper end of the source / drain pattern 150 in the third direction (D3).

[0027] Meanwhile, there may be cases where the second spacers 141 cannot be disposed on both sides of the source / drain patterns 150 in the second direction (D2). In this case, the source / drain pattern 150 has a diamond shape with convex left and right sides because lateral growth in the second direction D2 also occurs during epitaxial growth. The channel pattern (CP) is disposed on top of the active pattern (AP). The channel pattern (CP) is spaced apart from the active pattern (AP) in a third direction (D3). A lower pattern layer 110 and a first conductive type doped pattern layer 115 are disposed between the channel pattern (CP) and the active pattern (AP). The channel pattern CP is also spaced apart from the first conductive type doped pattern layer 115 in the third direction D3.

[0028] The channel pattern (CP) may include semiconductor patterns (SP1, SP2, SP3, SP4). As an example, the channel pattern (CP) includes a first semiconductor pattern (SP1), a second semiconductor pattern (SP2), a third semiconductor pattern (SP3), and a fourth semiconductor pattern (SP4). The first semiconductor pattern (SP1), the second semiconductor pattern (SP2), the third semiconductor pattern (SP3), and the fourth semiconductor pattern (SP4) are disposed higher than an upper surface of the first conductive type doped pattern layer 115.

[0029] A second semiconductor pattern (SP2) is disposed on the first semiconductor pattern (SP1), a third semiconductor pattern (SP3) is disposed on the second semiconductor pattern (SP2), and a fourth semiconductor pattern (SP4) is disposed on the third semiconductor pattern (SP3). The second semiconductor pattern (SP2) is spaced apart from the first semiconductor pattern (SP1) and the third semiconductor pattern (SP3) in the third direction (D3), and the third semiconductor pattern (SP3) is spaced apart from the second semiconductor pattern (SP2) and the fourth semiconductor pattern (SP4) in the third direction (D3). The separation distances between the semiconductor patterns (SP1, SP2, SP3, SP4) are substantially the same. However, the present invention is not limited to this, and the distance between the semiconductor patterns (SP1, SP2, SP3, SP4) may be different.

[0030] The thicknesses of the semiconductor patterns (SP1, SP2, SP3, SP4) are substantially the same, but are not limited to this, and the thickness of at least one of the semiconductor patterns (SP1, SP2, SP3, SP4) may be different. Although Figures 2A, 2B, and 2C show four semiconductor patterns (SP1, SP2, SP3, SP4) stacked at a distance along the third direction (D3), this is for convenience of explanation and is not limited to this. For example, three or five or more semiconductor patterns may be stacked at intervals along the third direction (D3). The semiconductor patterns (SP1, SP2, SP3, SP4) may include a second semiconductor material that is different from the first semiconductor material that the lower pattern layer 110 includes. In addition, each of the semiconductor patterns (SP1, SP2, SP3, SP4) may include the same semiconductor material as the sacrificial active pattern (AP_P) of the substrate 100, or may include a different semiconductor material than the sacrificial active pattern (AP_P).

[0031] Since the semiconductor patterns (SP1, SP2, SP3, SP4) contain a second semiconductor material different from the first semiconductor material contained in the lower pattern layer 110, an upper pattern (U_AP) for forming the semiconductor patterns (SP1, SP2, SP3, SP4) can be easily formed, as shown in Figures 5A and 5B described below. In addition, as shown in Figures 9A and 9B described below, when removing the sacrificial lower pattern (UBP), the lower pattern layer 110 acts as an etch stopper (wet stopper) to prevent the substrate 100 or the semiconductor patterns (SP1, SP2, SP3, SP4) from being etched. In addition, as shown in Figures 26A and 26B described below, in the manufacturing method of a semiconductor device 10 according to an embodiment of the present invention, even in the process of completely removing the substrate 100 when applying a BSPDN (backside power distribution network) structure, a "BSPDN bulk-less" structure (a structure in which the entire silicon substrate is removed) can be easily realized through etching selectivity by using the lower pattern layer 110 as an etching stopper (wet stopper).

[0032] As an example, the second semiconductor material included in the semiconductor patterns (SP1, SP2, SP3, SP4) may include the elemental semiconductor material silicon (Si) or germanium (Ge). The second semiconductor material may also include a compound semiconductor, such as a Group IV-IV compound semiconductor or a Group III-V compound semiconductor. The IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn). A III-V compound semiconductor is, for example, any of a binary compound, a ternary compound, and a quaternary compound formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with one of the group V elements phosphorus (P), arsenic (As), and antimony (Sb).

[0033] The gate pattern (GS) is disposed on the lower insulating layer 330 . Between the gate pattern (GS) and the lower insulating layer 330, the lower pattern layer 110 and the first conductive type doped pattern layer 115 are disposed. The gate pattern (GS) extends in a second direction (D2). The gate patterns (GS) are disposed to be spaced apart from each other in a first direction (D1). As an example, the gate pattern (GS) is disposed on the first conductive type doped pattern layer 115 and crosses the first conductive type doped pattern layer 115 . The bottom of the gate pattern (GS) intersects with the top of the first conductive type doped pattern layer 115 .

[0034] The gate pattern (GS) has a sub-gate portion (S_GS) and a main gate portion (M_GS). The sub-gate portions (S_GS) are disposed between the semiconductor patterns (SP1, SP2, SP3, SP4) adjacent to each other in the third direction (D3) and between the first conductive type doped pattern layer 115 and the semiconductor patterns (SP1, SP2, SP3, SP4). The main gate portion (M_GS) is disposed on the uppermost semiconductor pattern (SP1, SP2, SP3, SP4) in the third direction (D3) and between the semiconductor patterns (SP1, SP2, SP3, SP4) spaced apart from each other in the second direction (D2). Since the channel pattern (CP) includes a plurality of semiconductor patterns (SP1, SP2, SP3, SP4), the gate pattern (GS) includes a plurality of sub-gate portions (S_GS). The number of sub-gate portions (S_GS) is proportional to the number of semiconductor patterns (SP1, SP2, SP3, SP4) included in the channel pattern (CP). For example, the number of sub-gate portions (S_GS) is the same as the number of semiconductor patterns (SP1, SP2, SP3, SP4).

[0035] The sub-gate portion (S_GS) includes a first sub-gate portion, a second sub-gate portion, a third sub-gate portion, and a fourth sub-gate portion. The first sub-gate portion, the second sub-gate portion, the third sub-gate portion, and the fourth sub-gate portion are sequentially stacked on the lower insulating layer 330 in a third direction (D3) to be spaced apart from each other. The following description will be given for the case where the number of sub-gate portions (S_GS) is four. However, the present invention is not limited to this and may include three or more sub-gate portions. As an example, the first sub-gate portion is disposed between an upper surface of the first conductive type doped pattern layer 115 and a lower surface of the first semiconductor pattern (SP1), the second sub-gate portion is disposed between an upper surface of the first semiconductor pattern (SP1) and a lower surface of the second semiconductor pattern (SP2), the third sub-gate portion is disposed between an upper surface of the second semiconductor pattern (SP2) and a lower surface of the third semiconductor pattern (SP3), and the fourth sub-gate portion is disposed between an upper surface of the third semiconductor pattern (SP3) and a lower surface of the fourth semiconductor pattern (SP4).

[0036] The sub-gate portions S_GS are disposed between source / drain patterns 150 (to be described later) and spaced apart in the first direction D1. Each of the sub-gate portions (S_GS) includes a sub-gate electrode 120s, a sub-interface insulating film 131S, and a sub-gate insulating film 132S. The sub-gate electrode 120s is disposed on the first conductive type doped pattern layer 115. The sub-gate electrodes 120s intersect with the active pattern (AP). At least a portion of the sub-gate electrode 120s is disposed on a stacked structure of the sub-gate electrode 120s and the channel pattern (CP). At this time, parts of the main gate electrode 120M are disposed so as to cover both side surfaces of the laminated structure of the sub-gate electrode 120s and the channel pattern (CP). As a result, the four sides of the channel pattern (CP) are surrounded by the sub-gate electrodes 120s and the main gate electrode 120M.

[0037] The sub-gate electrode 120 may comprise a metal, a metal alloy, a conductive metal nitrate, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride. The sub-gate electrode 120 may be formed of, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitrate (TaN), titanium silicon nitrate (TiSiN), tantalum silicon nitrate (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitrate (TiAlN), tantalum aluminum nitrate (TaAlN), tungsten nitrate (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride nitrate (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride nitrate (TaCN), tungsten The metals may include, but are not limited to, copper (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitrate (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitrate (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof. The conductive metal oxides and conductive metal oxynitrides may include, but are not limited to, oxidized forms of the above-mentioned materials.

[0038] The sub-interface insulating film 131S is disposed on an upper surface of the first conductive type doped pattern layer 115. The sub-interface insulating film 131S is disposed along the periphery of the channel pattern (CP). The sub-interface insulating film 131S directly contacts the first conductive type doped pattern layer 115, the source / drain pattern 150, and the channel pattern (CP). The sub-interface insulating film 131S is interposed between the channel pattern (CP) and the sub-gate insulating film 132S. The sub-gate insulating film 132S is disposed on an upper surface of the sub-interface insulating film 131S. The sub-gate insulating film 132S surrounds the channel pattern (CP). The sub-gate insulating film 132S is disposed along the periphery of the channel pattern (CP). The sub-gate insulating film 132S is interposed between the sub-gate electrode 120s and the sub-interface insulating film 131S.

[0039] As shown in FIG. 3, which will be described later, the sub-gate insulating film 132S is interposed between the sub-gate electrode 120s and the internal gate spacer 133. The sub-interface insulating film 131S is made of, for example, silicon oxide (SiO 2 ). The sub-gate insulating film 132S includes, for example, a high dielectric constant material. High-k materials include silicon oxides (SiO ), such as hafnium oxide (HfO ), aluminum oxide (AlO ), or tantalum oxide (TaO ). 2 ) includes materials with a dielectric constant greater than 0.01.

[0040] The main gate portion (M_GS) is disposed on the uppermost fourth semiconductor pattern (SP4) in a region where it intersects with the active pattern (AP), and is disposed on the lower insulating layer 330 in a region where it does not intersect with the active pattern (AP). As a result, the gate pattern (GS) surrounds the channel pattern (CP). As an example, in the semiconductor patterns (SP1, SP2, SP3, SP4), surfaces not connected to the source / drain pattern 150, for example, four surfaces, are surrounded by a gate pattern (GS). That is, the sub-gate portion (S_GS) surrounds the upper and lower portions of the semiconductor patterns (SP1, SP2, SP3, SP4), and the main gate portion (M_GS) encompasses the sides of the semiconductor patterns (SP1, SP2, SP3, SP4) and the upper portion of the top semiconductor pattern (SP4). The main gate portion (M_GS) includes a main gate electrode 120M, an interface insulating film 131M, and a gate insulating film 132M. The main gate electrode 120M may include a metal, a metal alloy, a conductive metal nitrate, a metal suicide, a doped semiconductor material, a conductive metal oxide, a conductive metal oxynitride, or a combination thereof.

[0041] The interface insulating film 131M extends along the top surfaces of the semiconductor patterns SP1, SP2, SP3, and SP4 and the top surface of the active pattern AP. The interface insulating film 131M may not extend along the side surface of the gate spacer 140, which will be described later. However, the present invention is not limited thereto, and the interface insulating film 131M may extend along the side surface of the gate spacer 140. The interface insulating film 131M is, for example, a silicon oxide (SiO 2 ).

[0042] The gate insulating film 132M includes, for example, a high dielectric constant material. High-k materials include silicon oxides (SiO ), such as hafnium oxide (HfO ), aluminum oxide (AlO ), or tantalum oxide (TaO ). 2 ) includes materials with a dielectric constant greater than 0.01. The gate insulating film 132M extends along the side and bottom surfaces of the main gate electrode 120M. The gate insulating film 132M extends along the side surface of the gate spacer 140. The gate insulating film 132M includes, for example, a high dielectric constant material. High-k materials include silicon oxides (SiO ), such as hafnium oxide (HfO ), aluminum oxide (AlO ), or tantalum oxide (TaO ). 2 ) includes materials with a dielectric constant greater than 0.01.

[0043] The gate spacers 140 are disposed on the sides of the main gate electrode 120M. The gate spacers 140 are not disposed between the active patterns (AP) and the semiconductor patterns (SP1, SP2, SP3, SP4). The gate spacers 140 are not disposed between the semiconductor patterns (SP1, SP2, SP3, SP4) adjacent to each other in the third direction (D3). The gate spacer 140 may be made of, for example, silicon nitrate (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon carbonate nitrate (SiOCN), silicon boron nitrate (SiBN), silicon oxynitride (SiOBN), silicon carbide (SiOC), or combinations thereof. Although the gate spacer 140 is shown as being a single layer, this is for convenience of explanation and is not intended to be limiting.

[0044] Meanwhile, as shown in FIG. 3, an inner gate spacer 133 is disposed between the sub-gate portion (S_GS) and the source / drain pattern 150 . The inner gate spacers 133 contact the sub-gate structures (S_GS) and the source / drain patterns 150, respectively. The inner gate spacers 133 are disposed between the first conductive type doped pattern layer 115 and the channel patterns (CP) and between adjacent channel patterns (CP) in the third direction (D3). The inner gate spacer 133 comprises a low dielectric constant material. Low dielectric constant materials include silicon oxide or materials with a dielectric constant lower than silicon oxide. For example, the low dielectric constant material may include silicon oxide, fluorine or carbon doped silicon oxide, porous silicon oxide, or an organic polymeric dielectric. As other examples, the inner gate spacer 133 may include silicon nitrate (SiN), silicon oxynitride (SiON), silicon (Si) carbonitride (SiCN), or silicon carbonitride (SiOCN).

[0045] Referring again to FIGS. 1, 2A, 2B, and 2C, a capping layer 145 is disposed over the main gate portion (M_GS) and the gate spacer 140. The top surface of the capping layer 145 is disposed flush with the top surface of the interlayer insulating film 190 . Alternatively, the capping layer 145 may be disposed between the gate spacers 140 as shown. The capping layer 145 may include, for example, silicon nitrate (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonate nitrate (SiOCN), or combinations thereof. The capping layer 145 includes a material that has an etch selectivity with respect to the interlayer insulating film 190 .

[0046] The source / drain pattern 150 is disposed on the active pattern (AP). The source / drain patterns 150 are disposed within source / drain recesses 150R extending in a third direction D3. The source / drain recesses (150R) are formed as shown in FIGS. 7A to 11B, which will be described later. The source / drain pattern 150 fills the source / drain recesses (150R). The bottom of the source / drain recess (150R) is defined by the first conductivity type doped pattern layer 115. The sides of the source / drain recess (150R) are defined by the semiconductor patterns (SP1, SP2, SP3, SP4) and the sub-gate portion (S_GS).

[0047] The source / drain pattern 150 is disposed on the side of the sub-gate portion (S_GS). For example, the source / drain pattern 150 contacts the sub-interface insulating film 131S of the sub-gate portion (S_GS) or the side of the inner gate spacer 133. The source / drain pattern 150 is disposed between the sub-gate portions (S_GS) adjacent to each other in the first direction (D1). For example, the source / drain patterns 150 are disposed on both sides of the sub-gate portion (S_GS). The source / drain patterns 150 are disposed on the sides of the semiconductor patterns (SP1, SP2, SP3, SP4) of the channel pattern (CP). For example, the source / drain patterns 150 contact the sides of the semiconductor patterns (SP1, SP2, SP3, SP4). The source / drain patterns 150 are disposed between the semiconductor patterns (SP1, SP2, SP3, SP4) adjacent to each other in the first direction (D1).

[0048] The side surface of the source / drain pattern 150 has an uneven wavy shape. For example, the side of the source / drain pattern 150 adjacent to the sub-gate portion (S_GS) has a concave shape toward the sub-gate portion (S_GS), and the side of the source / drain pattern 150 adjacent to the semiconductor patterns (SP1, SP2, SP3, SP4) has a convex shape toward the semiconductor patterns (SP1, SP2, SP3, SP4). The source / drain pattern 150 is an epitaxial pattern formed by a selective epitaxial growth process. The source / drain pattern 150 includes, for example, at least one of silicon (Si) and silicon germanium (SiGe). The source / drain patterns 150 act as the source / drain of a transistor that uses the semiconductor patterns SP1, SP2, SP3, and SP4 as a channel region.

[0049] As described above, the source / drain patterns 150 include a semiconductor material doped with second conductive impurities that is different from the semiconductor material doped with first conductive impurities included in the first conductive doped pattern layer 115 . The source / drain patterns 150 may include, for example, a semiconductor material, such as at least one of silicon (Si) and silicon germanium (SiGe), doped with second conductive type impurities. As an example, when the semiconductor material doped with the second conductive type impurities included in the source / drain pattern 150 includes a semiconductor material doped with n-type impurities, i.e., when the source / drain pattern 150 is located in an NMOS region, the semiconductor material doped with the first conductive type impurities included in the first conductive type doped pattern layer 115 includes a semiconductor material doped with p-type impurities. In addition, when the semiconductor material doped with the second conductive type impurities included in the source / drain pattern 150 includes a semiconductor material doped with p-type impurities, i.e., when the source / drain pattern 150 is located in a PMOS region, the semiconductor material doped with the first conductive type impurities included in the first conductive type doped pattern layer 115 includes a semiconductor material doped with n-type impurities.

[0050] By way of example, the n-type impurities may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. For example, when phosphorus (P) is used as the n-type impurity, phosphorus (P) or phosphine (PH 3 ) or the like, and then phosphorus (P) is doped into the semiconductor material through low energy ion implantation, plasma ion implantation, or pulsed laser ablation deposition. The p-type impurities may include boron (B), aluminum (Al), gallium (Ga), indium (In), or combinations thereof. For example, when using boron (B) as a p-type impurity, boron (B) and boron difluoride (BF) are used as impurity gases. 2 ), or boron trifluoride (BF 3 ) or the like, and then doping the semiconductor material with boron (B) through low energy ion implantation, plasma ion implantation, or pulsed laser ablation deposition.

[0051] The source / drain pattern 150 includes a first source / drain structure 151 and a second source / drain structure 152 . The first source / drain structure 151 and the second source / drain structure 152 are respectively connected to a first upper contact electrode (UCT1) or a lower contact electrode (CT1) described below. For example, the first source / drain structure 151 is connected to the first upper contact electrode (UCT1), and the second source / drain structure 152 is connected to the lower contact electrode (CT1). Hereinafter, the source / drain pattern 150 connected to the first upper contact electrode (UCT1) will be referred to as a first source / drain structure 151, and the source / drain pattern 150 connected to the lower contact electrode (CT1) will be referred to as a second source / drain structure 152.

[0052] The first source / drain structure 151 and the second source / drain structure 152 are spaced apart from each other in a second direction D2 along the extension direction of the gate pattern GS. An interlayer insulating film 190, which will be described later, is disposed between the first source / drain structure 151 and the second source / drain structure 152. The etch stop layer 185 is disposed on the side surfaces of the gate spacer 140 and on the top surfaces of the source / drain patterns 150 . The etch stop layer 185 includes a material having an etch selectivity with respect to an interlayer insulating film 190, which will be described later. The etch stop film 185 may include, for example, silicon nitrate (SiN), silicon oxynitride (SiON), silicon carbonate nitrate (SiOCN), silicon boron nitrate (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), or combinations thereof. An interlayer dielectric 190 is disposed over the etch stop layer 185 . An interlayer insulating film 190 is disposed on the source / drain pattern 150 . The interlayer insulating film 190 does not cover the top surface of the capping layer 145 .

[0053] The interlayer insulating film 190 is, for example, a silicon oxide (SiO 2 ), silicon nitrate (SiN), silicon oxynitride (SiON), or a low dielectric constant material. Low dielectric constant materials include, for example, Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane(HSQ), Bis-benzoCycloButene(BCB), TetraMethylOrthoSilicate(TMOS), OctaMethyleyCloTetraSiloxane(OMCTS), HexaMethylDiSiloxane(HMDS), TriMethylSilyl Borate(TMSB), DiAcetoxyDitertiaryButoSiloxane(DADBS), TriMethylSilil Phosphate(TMSP), PolyTetraFluoroEthylene(PTFE), TOSZ(Tonen SilaZen), FSG(Fluoride Silicate Glass), polyimide nanofoams like polypropylene oxide, CDO(Carbon Dopedsilicon Oxide), OSG(Organo Silicate Glass), SiLK, Amorphous These may include, but are not limited to, fluorinated carbon, silica aerogels, silica xerogels, mesoporous silica, or combinations thereof.

[0054] A lower wiring structure ML1 is disposed below the lower surface of the lower insulating layer 330. The lower wiring structure (ML1) is, for example, a power delivery network that provides a voltage (eg, a power supply voltage) to the source / drain patterns 150. The lower wiring structure (ML1) includes a lower wiring 340 and a lower wiring insulating layer 350. The lower wiring 340 is disposed on the lower surface of the lower insulating layer 330 . The lower wiring 340 includes a metal (for example, copper). The lower wiring 340 is electrically connected to the lower contact electrode (CT1). This will be explained later. Also, in Figures 1, 2A, 2B, and 2C, the lower wiring 340 is extended in the second direction (D2) parallel to the direction in which the gate pattern (GS) extends, but this is not limited to this. For example, the lower wiring 340 may extend in a first direction D1 that crosses the direction in which the gate pattern GS extends.

[0055] The lower wiring insulating layer 350 is disposed below the lower surface of the lower insulating layer 330 . The lower wiring insulating layer 350 covers the lower wiring 340 , and the lower wiring 340 is disposed within the lower wiring insulating layer 350 . The lower wiring insulating layer 350 is made of, for example, silicon oxide (SiO 2 ), silicon nitrate (SiN), silicon oxynitride (SiON), or a low dielectric film. The bottom contact electrode (CT1) is disposed between the source / drain pattern 150 and the lower wiring structure (ML1). The lower contact electrode (CT1) is connected to at least one source / drain pattern 150. For example, the bottom contact electrode (CT1) is connected to the second source / drain structure 152. The bottom contact electrode (CT1) may not be connected to the first source / drain structure 151.

[0056] In the following description, a case in which the lower contact electrode (CT1) is connected to the second source / drain structure 152 and not connected to the first source / drain structure 151 will be described. However, the present invention is not limited thereto, and the lower contact electrode CT1 may be connected to the first source / drain structure 151. The bottom contact electrode (CT1) may not be connected to the second source / drain structure 152. At this time, the second source / drain structure 152 may be connected to the first upper contact electrode (UCT1), and the first source / drain structure 151 may not be connected to the first upper contact electrode (UCT1).

[0057] The bottom contact electrode (CT1) is disposed between the second source / drain structure 152 and the lower wiring structure (ML1). The lower contact electrode CT1 extends in a third direction D3 from the second source / drain structure 152 to the lower wiring structure ML1. The lower surface of the lower contact electrode (CT1) is connected to the lower wiring structure (ML1). The top surface of the bottom contact electrode (CT1) is connected to the second source / drain structure 152. The lower contact electrode (CT1) penetrates the lower pattern layer 110 and the first conductive type doped pattern layer 115. In addition, the lower contact electrode (CT1) is disposed in the lower insulating layer 330, the lower contact electrode (CT1) penetrates the lower insulating layer 330, the upper surface of the lower contact electrode (CT1) is connected to the second source / drain structure 152, and the lower surface of the lower contact electrode (CT1) is connected to the lower wiring structure (ML1).

[0058] The second source / drain structure 152 and the lower wiring structure (ML1) are electrically connected to each other via the lower contact electrode (CT1). That is, a voltage (eg, a power supply voltage) is applied from the lower wiring structure (ML1) to the second source / drain structure 152 via the lower contact electrode (CT1). The lower contact electrode (CT1) includes a conductive pattern 230 and a barrier pattern 240 surrounding the conductive pattern 230. The conductive pattern 230 may include, for example, at least one of a metal, a metal alloy, a conductive metal nitrate, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonaceous material, and a two-dimensional (2D) material.

[0059] The barrier pattern 240 covers the sidewalls and bottom surface of the conductive pattern 230 . The barrier pattern 240 may include a metal, a metal alloy, or a conductive metal nitrate. The metal may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitrate may include at least one of titanium nitride (TiN), tantalum nitrate (TaN), tungsten nitrate (WN), nickel nitrate (NiN), cobalt nitrate (CoN), and platinum nitrate (PtN). Although the lower contact electrode CT1 is illustrated as being a double film including the conductive pattern 230 and the barrier pattern 240, this is for convenience of explanation and is not limited thereto.

[0060] Although not shown, a metal silicide film may be further disposed between the second source / drain structure 152 and the lower contact electrode (CT1) of the semiconductor device 10 according to some embodiments. For example, the metal silicide film is disposed along the interface of the bottom contact electrode (CT1) that contacts the second source / drain structure 152. The metal silicide film includes a metal silicide. On the upper surface of the interlayer insulating layer 190, an upper wiring structure (ML2) is disposed. The upper wiring structure (ML2) may be, for example, a power delivery network that supplies a voltage (eg, a power supply voltage) to the gate pattern (GS) or the source / drain pattern 150. The upper wiring structure (ML2) includes an upper wiring 320 and an upper wiring insulating layer 310.

[0061] The upper wiring 320 is disposed on the upper surface of the interlayer insulating layer 190 . The upper wiring 320 includes a metal (for example, copper). The upper wiring 320 is electrically connected to a first or second upper contact electrode (UCT1, UCT2) described later. In Figures 1, 2A, 2B, and 2C, the upper wiring 320 is shown as being connected to a first upper contact electrode (UCT1) described later, and not connected to a second upper contact electrode (UCT2) described later, but this is not limited to this. For example, there is a case where the upper wiring 320 is connected to the second upper contact electrode (UCT2) and is not connected to the first upper contact electrode (UCT1). Alternatively, the upper wiring 320 may be connected to the first upper contact electrode (UCT1) and the second upper contact electrode (UCT2), respectively. Also, in Figures 1, 2A, 2B, and 2C, the upper wiring 320 is extended in the second direction (D2) parallel to the direction in which the gate pattern (GS) extends, but this is not limited to this. For example, the upper wiring 320 may extend in a first direction D1 that crosses the direction in which the gate pattern GS extends.

[0062] The upper wiring insulating layer 310 is disposed on the upper surface of the interlayer insulating layer 190 . The upper wiring insulating layer 310 covers the upper wiring structure (ML2). That is, the upper wiring insulating layer 310 covers the upper wiring 320 , and the upper wiring 320 is disposed within the upper wiring insulating layer 310 . The upper wiring insulating layer 310 is made of, for example, silicon oxide (SiO 2 ), silicon nitrate (SiN), silicon oxynitride (SiON), or a low dielectric film.

[0063] The first upper contact electrode (UCT1) is disposed between the source / drain pattern 150 and the upper wiring structure (ML2). The first upper contact electrode (UCT1) is connected to at least one source / drain pattern 150. For example, the first upper contact electrode (UCT1) is connected to the first source / drain pattern 151. The first upper contact electrode (UCT1) may not be connected to the second source / drain structure 152. In the following description, a case in which the first upper contact electrode (UCT1) is connected to the first source / drain structure 151 and is not connected to the second source / drain structure 152 will be described.

[0064] The first upper contact electrode (UCT1) is disposed on one side of the main gate structure (M_GS). The first upper contact electrode (UCT1) is disposed on the source / drain pattern 150. For example, a first upper contact electrode (UCT1) is disposed on the first source / drain structure 151. The first upper contact electrode (UCT1) may not be disposed on the second source / drain structure 152. The first upper contact electrode (UCT1) penetrates at least one interlayer insulating layer 190. For example, the first upper contact electrode (UCT1) penetrates the interlayer insulating layer 190 on the first source / drain structure 151 and is connected to the first source / drain structure 151. The first upper contact electrode (UCT1) does not penetrate the interlayer insulating layer 190 on the second source / drain structure 152. That is, the first upper contact electrode (UCT1) may not be connected to the second source / drain structure 152.

[0065] A bottom surface of the first upper contact electrode UCT1 is disposed at a level similar to that of an upper surface of the fourth semiconductor pattern SP4 located at the top of the channel pattern CP. However, the present invention is not limited thereto, and the bottom surface of the first upper contact electrode UCT1 may be higher or lower than the bottom surface of the fourth semiconductor pattern SP4 located at the top of the channel pattern CP. Alternatively, the bottom surface of the first upper contact electrode (UCT1) may be disposed between the bottom surface of the first semiconductor pattern (SP1) located at the bottom of the channel pattern (CP) and the bottom surface of the fourth semiconductor pattern (SP4) located at the top.

[0066] The first upper contact electrode (UCT1) includes a conductive pattern 210 and a barrier pattern 220 surrounding the conductive pattern 210. The conductive pattern 210 may include, for example, at least one of a metal, a metal alloy, a conductive metal nitrate, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonaceous material, and a two-dimensional (2D) material. The barrier pattern 220 covers the sidewalls and bottom surface of the conductive pattern 210 . The barrier pattern 220 may include a metal, a metal alloy, or a conductive metal nitrate. The metal may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitrate may include at least one of titanium nitride (TiN), tantalum nitrate (TaN), tungsten nitrate (WN), nickel nitrate (NiN), cobalt nitrate (CoN), and platinum nitrate (PtN). Although the first upper contact electrode (UCT1) is illustrated as being a double layer including the conductive pattern 210 and the barrier pattern 220, this is for convenience of explanation and is not intended to be limiting.

[0067] A metal silicide film (not shown) is further disposed between the source / drain pattern 150 and the first upper contact electrode (UCT1). The metal silicide film includes a metal silicide. In Figures 1, 2A, 2B, and 2C, the first upper contact electrode (UCT1) is shown to be disposed on the first source / drain structure 151 and not on the second source / drain structure 152, but is not limited to this. For example, a first upper contact electrode (UCT1) may be disposed on the first source / drain structure 151 and the second source / drain structure 152, respectively. The first upper contact electrode (UCT1) is connected to the first source / drain structure 151 and the second source / drain structure 152, respectively. In this case, the first upper contact electrode UCT1 connected to the second source / drain structure 152 may be a dummy contact electrode to which no electrical signal is applied.

[0068] The second upper contact electrode (UCT2) is disposed between the gate pattern (GS) and the upper wiring structure (ML2). The second upper contact electrode (UCT2) is connected to at least one gate pattern (GS). The second upper contact electrode (UCT2) is disposed on one side of the first upper contact electrode (UCT1). A second top contact electrode (UCT2) is disposed on the main gate structure (M_GS). The second upper contact electrode (UCT2) penetrates at least one capping layer 145. For example, the second upper contact electrode (UCT2) is The gate electrode 144 penetrates the capping layer 145 on the top of the body (M_GS) and connects to the main gate structure (M_GS).

[0069] The second upper contact electrode (UCT2) does not penetrate the interlayer insulating layer 190 on the source / drain pattern 150. That is, the second upper contact electrode (UCT2) is not connected to the source / drain pattern 150. A lower surface of the second upper contact electrode (UCT2) is, for example, disposed at a level similar to an upper surface of the main gate structure (M_GS). However, the present invention is not limited thereto, and the lower surface of the second upper contact electrode (UCT2) may be disposed between the lower surface and the upper surface of the main gate structure (M_GS). The second upper contact electrode (UCT2) includes a conductive pattern 250 and a barrier pattern 260 surrounding the conductive pattern 250.

[0070] The conductive pattern 250 may include, for example, at least one of a metal, a metal alloy, a conductive metal nitrate, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonaceous material, and a two-dimensional (2D) material. The barrier pattern 260 covers the sidewalls and bottom surface of the conductive pattern 250 . The barrier pattern 260 may include a metal, a metal alloy, or a conductive metal nitrate. The metal may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitrate may include at least one of titanium nitride (TiN), tantalum nitrate (TaN), tungsten nitrate (WN), nickel nitrate (NiN), cobalt nitrate (CoN), and platinum nitrate (PtN).

[0071] Although the second upper contact electrode (UCT2) is illustrated as being a double layer including the conductive pattern 250 and the barrier pattern 260, this is for convenience of explanation and is not intended to be limiting. A metal silicide film (not shown) may be further disposed between the main gate structure (M_GS) and the second upper contact electrode (UCT2). The metal silicide film includes a metal silicide.

[0072] Hereinafter, a semiconductor device 10 according to another embodiment of the present invention will be described with reference to FIGS. 4A and 4B. 4A and 4B are cross-sectional views corresponding to FIGS. 2A and 2B, illustrating a semiconductor device 10 according to another embodiment of the present invention. The embodiment shown in FIGS. 4A and 4B has the same parts as the embodiment shown in FIGS. 2A and 2B, so a description thereof will be omitted and differences will be mainly described.

[0073] 2A and 2B, the lower pattern layer 110 is shown disposed on the lower insulating layer 330, and the first conductive type doped pattern layer 115 is shown disposed on the lower pattern layer 110. As shown in FIG. 4A and 4B, the first conductive type doped pattern layer 115 is shown disposed on the lower insulating layer 330, and the lower pattern layer 110 is not shown. As shown in Figures 26A and 26B described below, in a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention, when a BSPDN (backside power distribution network) structure is applied, the lower pattern layer 110 is used as an etching stopper (wet stopper) to remove the entire substrate 100, and then the lower pattern layer 110 is selectively removed. As a result, the manufactured semiconductor device 10 does not include the lower pattern layer 110 between the lower insulating layer 330 and the first conductive type doped pattern layer 115 . At this time, the lower contact electrode CT1 penetrates the first conductive type doped pattern layer 115 and is connected to the second source / drain structure 152.

[0074] Hereinafter, a method for manufacturing a semiconductor device 10 according to an embodiment of the present invention will be described with reference to FIGS. 5A to 29B. Figures 12A to 14B are cross-sectional views showing intermediate stages for illustrating a method for manufacturing a semiconductor element 10 according to another embodiment of the present invention, Figures 15 to 19 are cross-sectional views showing intermediate stages for illustrating a method for manufacturing a semiconductor element according to another embodiment of the present invention, and Figures 29A and 29B are cross-sectional views showing intermediate stages for illustrating a method for manufacturing a semiconductor element according to another embodiment of the present invention.

[0075] As shown in FIGS. 5A and 5B, a preliminary lower pattern layer 110P is formed on a substrate 100. As shown in FIG. The substrate 100 comprises bulk silicon or silicon on insulator (SOI). Alternatively, the substrate 100 may include a silicon substrate or may include other materials, such as silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The preliminary lower pattern layer 110P includes a first semiconductor material having an etch selectivity with respect to the substrate 100. As an example, the first semiconductor material includes silicon (Si), germanium (Ge), or a combination thereof, and carbon (C), for example, the first semiconductor material includes 0 at% to 31.5 at% germanium (Ge), more than 0 at% but not more than 2 at% carbon (C), and the remaining content is silicon (Si). Or, carbon (C) is contained in an amount of 0.1 at % to 1 at %.

[0076] Subsequently, a preliminary sacrificial lower pattern (UBP_P) and an upper pattern (U_AP) are formed on the preliminary lower pattern layer 110P. A preliminary sacrificial lower pattern (UBP_P) is disposed on the preliminary lower pattern layer 110P, and an upper pattern (U_AP) is disposed on the preliminary sacrificial lower pattern (UBP_P). The upper pattern (U_AP) includes sacrificial layers (SC_L) and semiconductor layers (ACT_L) alternately stacked on the substrate 100 . For example, the preliminary sacrificial lower pattern (UBP_P) includes silicon (Si), the sacrificial layer (SC_L) includes silicon germanium (SiGe), and the semiconductor layer (ACT_L) includes silicon (Si).

[0077] As shown in FIGS. 6A and 6B, a sacrificial active pattern (AP_P) is formed on a substrate 100. The substrate 100 has trenches defining a sacrificial active pattern (AP_P) and a field dielectric 105 disposed within the trenches. The sacrificial active pattern (AP_P) has a sheet or fin shape. The sacrificial active patterns AP_P extend along a first direction D1 and are spaced apart from each other along a second direction D2. The sacrificial active pattern (AP_P) may be formed by etching a part of the substrate 100, or may be formed by etching an epitaxial layer grown on the substrate 100.

[0078] A field insulating film 105 is disposed on the substrate 100 . The field insulating film 105 is disposed so as to fill the trench. As an example, the field insulating film 105 is disposed on the sidewalls of the sacrificial active pattern (AP_P). The field insulating film 105 is not disposed on the top surface of the sacrificial active pattern (AP_P). The field insulating film 105 entirely covers the side surfaces of the sacrificial active pattern AP_P. Alternatively, the field insulating film 105 may cover a portion of the sidewall of the sacrificial active pattern (AP_P). In this case, a portion of the sacrificial active pattern AP_P protrudes from the top surface of the field insulating film 105 in the third direction D3. The field dielectric 105 includes an insulating material and may include, for example, an oxide, a nitrate, an oxynitride, or a combination thereof. Although the field insulating film 105 is illustrated as being a single film, this is for convenience of explanation and is not intended to be limiting. Along with the formation of the sacrificial active pattern (AP_P), the lower pattern layer 110 and the sacrificial lower pattern (UBP) are formed from the preliminary lower pattern layer 110P and the preliminary sacrificial lower pattern (UBP_P).

[0079] Subsequently, a preliminary gate insulating film 130P, a preliminary main gate electrode 120MP, and a preliminary capping layer 120_HM are formed on the upper pattern U_AP. The preliminary gate insulating film 130P is also disposed on both side surfaces in the second direction D2 of the sacrificial active pattern AP_P and the upper pattern U_AP. The preliminary gate insulating film 130P may include, but is not limited to, silicon oxide, for example. The preliminary main gate electrode 120MP may include, for example, polysilicon, but is not limited to this. The pre-capping layer (120_HM) may include, for example, but is not limited to, silicon nitrate.

[0080] Preliminary gate spacers 140p are formed on both side surfaces of the preliminary main gate electrode 120MP. The preliminary gate spacers 140p are also disposed on both side surfaces in the second direction D2 of the sacrificial active pattern AP_P and the upper pattern U_AP. In addition, when the preliminary gate insulating film 130P is also disposed on both side surfaces in the second direction (D2) of the sacrificial active pattern (AP_P) and the upper pattern (U_AP), the preliminary gate spacers 140p are disposed on the surface of the preliminary gate insulating film 130P. The preliminary gate spacers 140p located on both sides of the sacrificial active pattern AP_P and the upper pattern U_AP in the second direction D2 become second spacers 141.

[0081] As shown in FIGS. 7A and 7B, using the preliminary capping layer (120_HM) and the preliminary gate spacer 140P as a mask, at least a portion of the upper pattern (U_AP) is etched to form source / drain recesses (150R). A portion of the source / drain recess (150R) is formed in the sacrificial active pattern (AP_P). By forming the source / drain recesses (150R), the semiconductor layer (ACT_L) is separated and semiconductor patterns (SP1, SP2, SP3, SP4) are formed, and the semiconductor patterns (SP1, SP2, SP3, SP4) are arranged between the source / drain recesses (150R). The semiconductor patterns (SP1, SP2, SP3, SP4) and the sacrificial layers (SC_L) are alternately stacked in a third direction (D3).

[0082] In addition, when the source / drain recesses (150R) are formed, the preliminary gate insulating film 130P located on the side of the source / drain recesses (150R) is also removed, and the preliminary gate insulating film 130P remaining on the side of the sacrificial active pattern (AP_P) becomes the first spacer 130. Furthermore, when the source / drain recesses (150R) are formed, a part of the second spacers 141 is also etched. Thus, the second spacer 141 covers the entire side surface of the source / drain pattern 150, but is not limited thereto. The second spacer 141 may cover only a portion of the side surface of the source / drain pattern 150. That is, the height of the upper end of the second spacer 141 in the third direction (D3) may be the same as the height of the upper end of the source / drain pattern 150 in the third direction (D3), or may be lower than the height of the upper end of the source / drain pattern 150 in the third direction (D3).

[0083] As shown in FIGS. 8A and 8B, third spacers 142 are formed on the side surfaces of the semiconductor patterns (SP1, SP2, SP3, and SP4), the sacrificial layer (SC_L), and the preliminary gate spacer 140P. First, a preliminary third spacer is formed on the preliminary capping layer (120_HM), the semiconductor patterns (SP1, SP2, SP3, SP4), the sacrificial layer (SC_L), the preliminary gate spacer 140P, the field insulating film 105, and the sacrificial lower pattern (UBP), and the upper surface of the preliminary third spacer is removed through an etching process to form a third spacer 142. The third spacer 142 covers the side surfaces of the semiconductor patterns (SP1, SP2, SP3, SP4) and the sacrificial layer (SC_L) in the source / drain recesses (150R) but does not cover the top surface of the sacrificial lower pattern (UBP). The third spacer 142 covers the side surfaces of the preliminary gate spacer 140P and does not cover the top surface of the preliminary capping layer (120_HM). The third spacer 142 includes silicon nitrate. However, the material of the third spacer 142 is not limited thereto, and may be changed in various ways. For example, the third spacer 142 may be made of SiOCN or the like.

[0084] As shown in FIGS. 9A and 9B, the sacrificial lower pattern (UBP) located under the source / drain recesses (150R) and under the semiconductor patterns (SP1, SP2, SP3, SP4) is selectively removed. At this time, the semiconductor patterns SP1, SP2, SP3, and SP4, the sacrificial layer SC_L, and the preliminary gate spacer 140P are not removed by the third spacer 142, but the sacrificial lower pattern UBP is selectively removed. In addition, when the sacrificial lower pattern (UBP) is removed, since the lower pattern layer 110 includes a first semiconductor material having an etching selectivity with the sacrificial lower pattern (UBP) and the substrate 100, the lower pattern layer 110 acts as an etch stopper to prevent the substrate 100 from being etched. As an example, the sacrificial bottom pattern (UBP) is removed using a wet etching process. At this time, an etchant is selected and used so that the first semiconductor material included in the lower pattern layer 110 is not removed, and the second semiconductor material included in the sacrificial lower pattern (UBP) is selectively removed.

[0085] That is, the etchant used to remove the lower pattern layer 110 has a relatively higher etch rate with respect to the second semiconductor material of the sacrificial lower pattern (UBP) than with respect to the first semiconductor material of the lower pattern layer 110 . For example, the first semiconductor material of the lower pattern layer 110 may include silicon (Si), germanium (Ge), and carbon (C) (SiGe:C), and the second semiconductor material of the sacrificial lower pattern (UBP) may include silicon (Si). At this time, the sacrificial lower pattern (UBP) is selectively etched by performing an etching process using an etchant having a higher etching rate for Si than for SiGe:C. Thus, the lower pattern layer 110 and the underlying substrate 100 are not removed, and the sacrificial lower pattern (UBP) can be selectively removed. A blank space (SS) is formed in the area where the sacrificial bottom pattern (UBP) is located. Meanwhile, in the process of selectively removing the sacrificial lower pattern (UBP), the preliminary gate insulating film 130P is partially or completely removed. In this case, a dent is formed in the portion where the preliminary gate insulating film 130P is removed, and at least a portion of the dent is filled with the source / drain pattern 150, and the source / drain pattern 150 is also disposed on both sides of the lower pattern layer 110 in the second direction (D2).

[0086] As shown in FIGS. 10A and 10B, the third spacers 142 are removed using an etching process. By removing the third spacers 142, the side surfaces of the semiconductor patterns (SP1, SP2, SP3, SP4) and the sacrificial layer (SC_L) are exposed within the source / drain recesses (150R). Furthermore, the third spacer 142 covering the side surface of the preliminary gate spacer 140P is also removed.

[0087] As shown in FIGS. 11A and 11B, a first conductive type doped pattern layer 115 and a source / drain pattern 150 are sequentially formed in one process. The first conductive type doped pattern layer 115 and the source / drain patterns 150 are formed using an epitaxial growth method. The upper surface of the lower pattern layer 110 and the inner wall of the source / drain recess 150R are used as a seed. The inner walls of the source / drain recesses (150R) are formed by the semiconductor patterns (SP1, SP2, SP3, SP4), the side surfaces of the sacrificial layer (SC_L), and the upper surface of the lower pattern layer 110. A first conductive type doped pattern layer 115 is formed in the blank space (SS) formed in the region where the sacrificial bottom pattern (UBP) is located, and a source / drain pattern 150 is formed in the source / drain recess (150R). At this time, the growth rate in the surface direction of the wafer is adjusted so that the first conductive type doped pattern layer 115 is formed first, and then the source / drain patterns 150 are formed.

[0088] For example, when the growth rate of the 100-plane of the wafer is higher than that of the 110-plane, the epitaxial layer grows in a third direction (D3), resulting in the growth of a first conductive type doped pattern layer 115 in the blank space (SS) formed in the area where the sacrificial bottom pattern (UBP) is located, and when the growth rate of the 110-plane of the wafer is higher than that of the 100-plane, the epitaxial layer grows in a first direction (D1), resulting in the growth of a source / drain pattern 150 in the source / drain recess (150R). As described above, the first conductive type doped pattern layer 115 includes a semiconductor material doped with a first conductive type impurity, and the source / drain pattern 150 includes a semiconductor material doped with a second conductive type impurity different from the first conductive type impurity. For example, when the source / drain patterns 150 include a semiconductor material doped with n-type impurities, the first conductive type doped pattern layer 115 includes a semiconductor material doped with p-type impurities.

[0089] Also, when the source / drain patterns 150 include a semiconductor material doped with p-type impurities, the first conductive type doped pattern layer 115 includes a semiconductor material doped with n-type impurities. Taking as an example a case where the source / drain pattern 150 includes a semiconductor material doped with n-type impurities and the first conductive type doped pattern layer 115 includes a semiconductor material doped with p-type impurities, boron (B) is used as the impurity gas under conditions where the growth rate of the 100 plane is dominant in the early stage of epitaxial growth, and phosphorus (P) is used as the impurity gas under conditions where the growth rate of the 110 plane is dominant after the epitaxial growth. Meanwhile, instead of sequentially forming the first conductive type doped pattern layer 115 and the source / drain pattern 150 in one process, as shown in Figures 12A to 14B, the first conductive type doped pattern layer 115 is formed and then the source / drain pattern 150 is formed in the next process.

[0090] In this case, the third spacers 142 are not removed, and the first conductive type doped pattern layer 115 is formed in the state in which the third spacers 142 are present. As an example, assuming that the source / drain pattern 150 includes a semiconductor material doped with n-type impurities and the first conductive type doped pattern layer 115 includes a semiconductor material doped with p-type impurities, the first conductive type doped pattern layer 115 can be formed by epitaxial growth using boron (B) as an impurity gas under conditions where the growth rate of the 100 plane is dominant.

[0091] Subsequently, as shown in FIGS. 14A and 14B, the third spacers 142 are removed using an etching process to form source / drain patterns 150 in the source / drain recesses 150R. At this time, the bottom surface of the source / drain recess (150R) is the top surface of the first conductive type doped pattern layer 115. As an example, assuming that the source / drain pattern 150 includes a semiconductor material doped with n-type impurities and the first conductive type doped pattern layer 115 includes a semiconductor material doped with p-type impurities, the source / drain pattern 150 is formed by epitaxial growth using phosphorus (P) as an impurity gas under conditions where the growth rate of the 110 plane is dominant.

[0092] Meanwhile, as shown in FIG. 15, after the source / drain recesses (150R) are formed, an indentation process for the sacrificial layer (SC_L) is carried out. In the indent process, the sacrificial layer (SC_L) is etched using a wet etching or dry etching method to further shorten the length of the sacrificial layer (SC_L) in the first direction (D1) to form an indent 155. As a result, the surface of the sacrificial layer (SC_L) in contact with the source / drain recess (150R) has a concave shape facing the source / drain recess (150R). For example, when a wet etching method is used, an etchant such as aqueous ammonia is used.

[0093] Next, as shown in Figures 16 to 19, a third spacer 142 is formed on the sides of the semiconductor patterns (SP1, SP2, SP3, SP4), the sacrificial layer (SC_L), and the preliminary gate spacer 140P, and the sacrificial lower pattern (UBP) under the source / drain recess (150R) is selectively removed, and then the third spacer 142 is removed using an etching process. However, even if the third spacer 142 is removed, the third spacer 142 inside the indent 155 remains, and the inner gate spacer 133 is formed. Subsequently, when the first conductive type doped pattern layer 115 and the source / drain pattern 150 are formed, the inner gate spacer 133 is disposed between the sacrificial layer (SC_L) and the source / drain pattern 150, as shown in FIG.

[0094] Furthermore, as shown in Figures 21 and 22 described below, when the sacrificial layer (SC_L) is removed and a sub-gate structure (S_GS) is formed in the area where the sacrificial layer (SC_L) was located, the inner gate spacer 133 is located between the sub-gate structures (S_GS) and the source / drain pattern 150. The inner gate spacer 133 comprises a low dielectric constant material. Low dielectric constant materials include silicon oxide or materials with a dielectric constant lower than silicon oxide. For example, the low dielectric constant material may include silicon oxide, fluorine or carbon doped silicon oxide, porous silicon oxide, or an organic polymeric dielectric. As another example, the inner gate spacer 133 may include at least one of silicon nitrate, silicon carbonate, silicon carbonate nitrate, and silicon acid nitrate.

[0095] 20A and 20B, an etch stop layer 185 and an interlayer insulating layer 190 are sequentially formed on the source / drain pattern 150. As shown in FIG. Then, a portion of the interlayer insulating film 190, a portion of the etch stop film 185, and the preliminary capping layer 120_HM are removed to expose the upper surface of the preliminary main gate electrode 120MP. A gate spacer 140 is formed while the top surface of the preliminary main gate electrode 120MP is exposed.

[0096] As shown in FIG. 21, the preliminary gate insulating film 130P and the preliminary main gate electrode 120MP located on the upper pattern structure (U_AP) are removed to expose the upper pattern structure (U_AP) between the gate spacers 140. Next, gate trenches 120t are formed between the semiconductor patterns (SP1, SP2, SP3, SP4) and under the first semiconductor pattern (SP1).

[0097] As shown in FIG. 22, a sub-interface insulating film 131S, a sub-gate insulating film 132S, and a sub-gate electrode 120s are formed in this order in the gate trench 120t. Further, an interface insulating film 131M, a main gate insulating film 132M, a main gate electrode 120M, and a capping layer 145 are sequentially formed.

[0098] As shown in FIGS. 23A and 23B, a first upper contact electrode (UCT1) is formed in the interlayer insulating layer 190. First, contact holes are formed through the interlayer insulating layer 190 to expose the source / drain patterns 150 . For example, contact holes are formed through the interlayer insulating layer 190 to expose the first source / drain structures 151 . A contact hole exposing the second source / drain structure 152 is not formed, but the present invention is not limited thereto. Next, a first upper contact electrode (UCT1) that fills the contact hole and electrically connects to the first source / drain structure 151 is formed. For example, a barrier pattern 220 and a conductive pattern 210 are sequentially formed in the contact hole. As a result, the first upper contact electrode (UCT1) penetrates the interlayer insulating layer 191 and is electrically connected to the first source / drain structure 151.

[0099] In addition, a second upper contact electrode (UCT2) is formed in the capping layer 145. First, a contact hole is formed through the capping layer 145 to expose the main gate structure (M_GS). For example, a contact hole is formed through the capping layer 145 to expose the main gate structure (M_GS). Subsequently, a second upper contact electrode (UCT2) is formed to fill the contact hole and to be electrically connected to the main gate structure (M_GS). For example, a barrier pattern 250 and a conductive pattern 260 are sequentially formed in the contact hole. Thereby, the second upper contact electrode (UCT2) penetrates the capping layer 145 and is electrically connected to the main gate structure (M_GS).

[0100] As shown in FIGS. 24A and 24B, an upper wiring structure ML2 is formed on an upper surface of the interlayer insulating layer 190 and the capping layer 145 to be electrically connected to the first upper contact electrode UCT1. However, the present invention is not limited to this, and the upper wiring structure (ML2) can also be electrically connected to the second upper contact electrode (UCT1). The upper wiring structure (ML2) may include a first upper wiring 320 and an upper wiring insulating layer 310 covering the first upper wiring 320.

[0101] As shown in FIGS. 25A and 25B, the semiconductor device 10 according to one embodiment of the present invention is rotated. As an example, the rotated semiconductor device 10 is disposed on a carrier substrate (not shown). At this time, the upper surface of the semiconductor element 10 is disposed so as to face the carrier substrate, and then attached to the carrier substrate. That is, the upper wiring structure ML2 located on the upper surface of the semiconductor device 10 is attached onto the carrier substrate. An adhesive member (not shown) is disposed between the upper wiring structure ML2 and the carrier substrate.

[0102] The carrier substrate can have substantially the same area as the semiconductor device 10, or it can have a larger area. The carrier substrate may be, for example, a semiconductor wafer, a ceramic substrate, or a glass substrate. The adhesive member may be in the form of a film. The adhesive member includes a base film and adhesive layers attached to both sides of the base film. The base film can be, for example, a polyethylene-based film or a polyolefin-based film, such as polyethylene terephthalate (PET) or polyethylene-2,6-naphthalenedicarboxylate (PEN). The base film is formed by coating a polyethylene film or a polyolefin film with silicone or Teflon. The adhesive layer may be made of, for example, an acrylic polymer resin, an epoxy resin, or a mixture thereof.

[0103] As shown in FIGS. 26A and 26B, an etching process is performed to remove the substrate 100. The etching process may be performed by, but is not limited to, a wet etching method. At this time, since the lower pattern layer 110 includes a first semiconductor material having an etching selectivity with respect to the substrate 100, the lower pattern layer 110 serves as an etch stop layer. That is, when the lower pattern layer 110 is exposed during the etching of the substrate 100, the etching process is stopped.

[0104] In this manner, in the manufacturing method of the semiconductor device 10 according to an embodiment of the present invention, even in the process of completely removing the substrate 100 when applying a BSPDN (backside power distribution network) structure, the lower pattern layer 110 can be used as an etching stopper, and a “BSPDN bulk-less” structure (a structure in which the entire silicon substrate is removed) can be easily realized through etching selectivity. The process of etching the substrate 100 is carried out using an etchant having a relatively high etching rate for the substrate 100 . For example, if the substrate 100 includes Si and the lower pattern layer 110 includes SiGe:C, the etching process is performed using an etchant having a relatively high etching rate for Si. The substrate 100 is removed to expose the underlying pattern layer 110 .

[0105] As shown in FIGS. 27A and 27B, a lower insulating layer 330 is formed to cover the lower pattern layer 110. As shown in FIG. This causes the lower insulating layer 330 to contact the lower pattern layer 110 . The lower insulating layer 330 is formed by forming a preliminary lower insulating layer to cover the lower pattern layer 110 and then performing a chemical mechanical polishing (CMP) process to planarize the upper surface of the lower insulating layer 330, but is not limited to this. In Figures 26A to 27B, an etching process is performed to remove substrate 100, and a lower insulating layer 330 is formed in the area from which substrate 100 has been removed, but this is not limited to this, and the processes of Figures 26A to 27B may be omitted. For example, the substrate 100 is not removed by etching the entire surface, but a portion of the substrate 100 is selectively removed. At this time, the substrate 100 is patterned using a photo and etching process so that the lower pattern layer 110 is exposed. Alternatively, the substrate 100 may not be completely removed through the etching process, but only a portion of the substrate 100 may be removed so that the lower pattern layer 110 is exposed.

[0106] Then, a photolithography and etching process is performed to remove a portion of the lower insulating layer 330 to form a contact hole through which the second source / drain structure 152 is exposed. At this time, the contact holes penetrate the lower pattern layer 110 and the first conductive type doped pattern layer 115 . The side surface of the contact hole is surrounded by, for example, the lower insulating layer 330 . Subsequently, a lower contact electrode (CT1) that fills the contact hole and electrically connects to the second source / drain structure 152 is formed. For example, a barrier pattern 240 and a conductive pattern 230 are sequentially formed in the contact hole. Thus, the lower contact electrode (CT1) penetrates the lower pattern layer 110 and the first conductive type doped pattern layer 115 and is electrically connected to the second source / drain structure 152.

[0107] As shown in FIGS. 28A and 28B, a lower wiring structure (ML1) is formed on the lower surface of the lower insulating layer 330 to be electrically connected to the lower contact electrode (CT1). The lower wiring structure (ML1) includes a lower wiring 340 and a lower wiring insulating layer 350 covering the lower wiring 340. The carrier substrate and adhesive member are then removed, and the semiconductor device 10 is then spun to form the semiconductor device 10 of Figures 1, 2A, 2B, and 2C. Meanwhile, after removing the substrate 100 as shown in FIGS. 26A and 26B, the lower pattern layer 110 can also be selectively removed as shown in FIGS. 29A and 29B.

[0108] That is, in the method for manufacturing a semiconductor device 10 according to one embodiment of the present invention, when a BSPDN (backside power distribution network) structure is applied, the lower pattern layer 110 is used as an etch stopper (wet stopper) to remove the entire substrate 100, and then the lower pattern layer 110 is selectively removed. The lower pattern layer 110 is removed using an etching process. The etching process may be performed by, but is not limited to, a wet etching method. The process of etching the lower pattern layer 110 is performed using an etchant having a relatively high etching rate for the lower pattern layer 110 . For example, if the lower pattern layer 110 includes SiGe:C, the etching process is performed using an etchant having a relatively high etching rate for SiGe:C.

[0109] Next, a lower insulating layer 330 is formed to cover the first conductive type doped pattern layer 115 exposed by removing the lower pattern layer 110, a lower contact electrode (CT1) electrically connected to the second source / drain structure 152 is formed, and a lower wiring structure (ML1) electrically connected to the lower contact electrode (CT1) is formed on the lower surface of the lower insulating layer 330. Then, the semiconductor device 10 is rotated to form the semiconductor device 10 of Figures 4A and 4B.

[0110] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0111] 10 Semiconductor elements 100 Substrates 105 Field Insulation Film 110 Lower Pattern Layer 110P spare lower pattern layer 115 First conductive type doping pattern layer 120_HM Pre-capping layer 120M Main gate electrode 120MP spare main gate electrode 120s Subgate electrode 130 First spacer 130P spare gate insulating film 131M Interface insulating film 132M Main gate insulating film 131S Sub-interface insulating film 132S Sub-gate insulating film 133 Inner Gate Spacer 140 Gate Spacer 140P Spare Gate Spacer 141 Second Spacer 142 3rd Spacer 145 Capping Layer 150 Source / Drain Pattern 150R Source / Drain Recess 151 First source / drain structure 152 Second source / drain structure 155 indent 185 Etching stop film 190 Interlayer insulating film 210, 230, 250 Conductive pattern 220, 240, 260 Barrier Pattern 310 Upper wiring insulation layer 320 Upper Wiring 330 Lower insulation layer 340 Lower Wiring 350 Lower wiring insulation layer ACT_L Semiconductor layer AP Activity Pattern AP_P Sacrificial Active Pattern CP Channel Pattern GS Gate Pattern ML1 Lower Wiring Structure ML2 upper wiring structure M_GS Main gate part SC_L Sacrificial layer S_GS Subgate part SP1, SP2, SP3, SP4 Semiconductor patterns UBP Sacrificial Lower Pattern UBP_P Reserve Sacrificial Lower Pattern U_AP Upper pattern CT1 Lower contact electrode UCT1 First upper contact electrode UCT2 Second upper contact electrode

Claims

1. a lower pattern layer comprising a first semiconductor material; a first conductive type doped pattern layer disposed on the lower pattern layer and including a semiconductor material doped with a first conductive type impurity; a source / drain pattern disposed on the first conductive type doped pattern layer and including a semiconductor material doped with a second conductive type impurity different from the first conductive type impurity; a channel pattern including a semiconductor pattern that is stacked apart from the source / drain patterns and includes a second semiconductor material different from the first semiconductor material, the channel pattern connecting the source / drain patterns and being spaced apart from each other; a gate pattern disposed on the first conductive type doped pattern layer, crossing between the source / drain patterns and surrounding the channel pattern.

2. 2. The semiconductor device of claim 1, wherein the first semiconductor material comprises germanium (Ge) in a range of 0 at % to 31.5 at %, carbon (C) in a range of more than 0 at % to 2 at %, and the remaining content being silicon (Si).

3. The semiconductor device of claim 1 , wherein the second semiconductor material comprises silicon (Si), germanium (Ge), or a combination thereof.

4. 2. The semiconductor device according to claim 1, wherein the first conductive type impurity is an n-type impurity, and the second conductive type impurity is a p-type impurity.

5. the n-type impurity comprises phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof; 5. The semiconductor device of claim 4, wherein the p-type impurity comprises boron (B), aluminum (Al), gallium (Ga), indium (In), or a combination thereof.

6. A semiconductor device, a lower pattern layer comprising a first semiconductor material; a first conductive type doped pattern layer disposed on the lower pattern layer and including a semiconductor material doped with a first conductive type impurity; a source / drain pattern disposed on the first conductive type doped pattern layer and including a semiconductor material doped with a second conductive type impurity different from the first conductive type impurity; a channel pattern including a semiconductor pattern that is stacked apart from the source / drain patterns and includes a second semiconductor material different from the first semiconductor material, the channel pattern connecting the source / drain patterns and being spaced apart from each other; a gate pattern disposed on the first conductive type doped pattern layer, crossing between the source / drain patterns and surrounding the channel pattern; a lower contact electrode disposed under the source / drain pattern, penetrating the lower pattern layer and the first conductive type doped pattern layer, and connected to the source / drain pattern.

7. The source / drain pattern includes a first source / drain structure and a second source / drain structure spaced apart from each other, 7. The semiconductor device of claim 6, further comprising a first upper contact electrode disposed on and connected to the first source / drain structure.

8. The semiconductor device of claim 7 , wherein the lower contact electrode is disposed under the second source / drain structure and connected to the second source / drain structure.

9. 8. The semiconductor device of claim 7, further comprising a second upper contact electrode disposed on and connected to the gate pattern.

10. a first conductive type doped pattern layer including a semiconductor material doped with a first conductive type impurity; a source / drain pattern disposed on the first conductive type doped pattern layer and including a semiconductor material doped with a second conductive type impurity different from the first conductive type impurity; a channel pattern including semiconductor patterns spaced apart from each other and connecting the source / drain patterns; a gate pattern disposed on the first conductive type doped pattern layer, crossing between the source / drain patterns and surrounding the channel pattern; a lower contact electrode disposed under the source / drain pattern, penetrating the first conductive type doped pattern layer, and connected to the source / drain pattern.

Images