Electro-optic device and electronic apparatus

Abstract

To provide an electro-optic device including a Peltier element having high cooling performance or cooling efficiency.SOLUTION: The electro-optic device is a liquid crystal device 300 including a Peltier element 20 outside a display area A1. The Peltier element 20 comprises: a p-type semiconductor member 21 as first conductivity type first member; a p-type semiconductor member 21; an n-type semiconductor member 22 as second conductivity type second member, provided adjacent to a Y1-direction as direction along the display area A1; an electrode 23a as first electrode, in contact with a portion 21a of the p-type semiconductor member 21 closer to the display area A1; an electrode 23b as second electrode, provided adjacent to the electrode 23a in the Y1-direction and in contact with a portion 22a of the n-type semiconductor member 22 closer to the display area A1; and an electrode 24 as third electrode, in contact with a portion 21b of the p-type semiconductor member 21 opposite the display area A1 and a portion 22b of the n-type semiconductor member 22 opposite the display area A1.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an electro-optical device and an electronic device equipped with the electro-optical device. [Background technology]

[0002] 2. Description of the Related Art An electro-optical device having a Peltier element for heat dissipation is known, for example, as described in Patent Document 1. Patent document 1 describes a liquid crystal device that includes a light-shielding film arranged in a matrix in the display area of ​​a liquid crystal panel, a pair of semiconductor elements of different conductivity types connected to both ends of the light-shielding film, heat-dissipating electrodes connected to each of the pair of semiconductor elements, and a power supply means that supplies voltage between the heat-dissipating electrodes to utilize the light-shielding film as a heat sink for the Peltier element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2002-303880 A Summary of the Invention [Problem to be solved by the invention]

[0004] In order to realize a bright projector, efforts are being made to increase the luminous flux of the light source. However, increasing the luminous flux of the light source causes the temperature of the liquid crystal panel to rise, and the rise in temperature of the liquid crystal panel affects the light resistance life and the operation of the liquid crystal. Therefore, there is a demand for further improvements in technology to suppress temperature increases in liquid crystal panels. [Means for solving the problem]

[0005] An electro-optical device according to one embodiment of the present application is an electro-optical device including Peltier elements outside a display area, each of the Peltier elements including a first member of a first conductivity type, a second member of a second conductivity type arranged adjacent to the first member in a direction along the display area, a first electrode in contact with the display area side of the first member, a second electrode arranged adjacent to the first electrode in the direction and in contact with the display area side of the second member, and a third electrode in contact with the side of the first member and the second member opposite the display area side.

[0006] An electro-optical device according to one embodiment of the present application is an electro-optical device including a Peltier element made of a semiconductor material outside a display area, the Peltier elements each including, in the semiconductor material, a first region of a first conductivity type, a second region of a second conductivity type adjacent to the first region in a direction along the display area, a third region of the second conductivity type adjacent to the first region in the opposite direction, a first junction region where the display area side of the first region and the display area side of the third region meet, and a second junction region where the opposite side of the display area of ​​the first region and the opposite side of the display area of ​​the second region meet.

[0007] An electronic device according to an aspect of the present application includes the electro-optical device described above. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of an electro-optical device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of the electro-optical device taken along line AA in FIG. [Diagram 3] FIG. 2 is an equivalent circuit diagram showing an electrical configuration of an element substrate. [Figure 4] FIG. 2 is an explanatory diagram showing the planar structure of a Peltier element. [Diagram 5] 5 is an explanatory diagram showing a cross-sectional structure of the Peltier element taken along line BB in FIG. 4. [Figure 6A] FIG. 4 is an explanatory diagram showing a cross-sectional structure of a Peltier element according to a first modified example. [Figure 6B] FIG. 11 is an explanatory diagram showing a cross-sectional structure of a Peltier element according to Modification 2. [Figure 6C] FIG. 11 is an explanatory diagram showing a cross-sectional structure of a Peltier element according to Modification 3. [Figure 6D] FIG. 13 is an explanatory diagram showing a cross-sectional structure of a Peltier element according to Modification 4. [Figure 6E] FIG. 13 is an explanatory diagram showing a cross-sectional structure of a Peltier element according to Modification 5. [Figure 6F] FIG. 13 is an explanatory diagram showing a cross-sectional structure of a Peltier element according to Modification 6. [Figure 7] FIG. 11 is an explanatory diagram showing the planar structure of a Peltier element according to a second embodiment. [Figure 8] 4 is a flowchart showing a method for manufacturing a Peltier element. [Figure 9] FIG. 4 is a plan view showing one process of manufacturing the Peltier element. [Figure 10] FIG. 4 is a plan view showing one process of manufacturing the Peltier element. [Figure 11] FIG. 4 is a plan view showing one process of manufacturing the Peltier element. [Figure 12] FIG. 4 is a plan view showing one process of manufacturing the Peltier element. [Figure 13] FIG. 11 is a schematic diagram showing an example of an electronic device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the dimensions of the components may be shown on different scales in order to make the components easier to see. For ease of explanation, the following description will be made using the mutually orthogonal X-axis, Y-axis, and Z-axis as appropriate. A direction along the X-axis will be referred to as the X1 direction, and a direction opposite to the X1 direction will be referred to as the X2 direction. Similarly, a direction along the Y-axis will be referred to as the Y1 direction, and a direction opposite to the Y1 direction will be referred to as the Y2 direction. A direction along the Z-axis will be referred to as the Z1 direction, and a direction opposite to the Z1 direction will be referred to as the Z2 direction. In the following description, a view in the Z1 or Z2 direction will be referred to as a "planar view," and a view from a direction perpendicular to a cross section including the Z-axis will be referred to as a "cross-sectional view."

[0010] Furthermore, in the following description, for example, the term "on a base" with respect to a substrate means that it is disposed on the base, that it is disposed on the base via another structure, or that it is disposed partly on the base and partly via another structure. The term "upper surface of the base" refers to the surface of the substrate on the Z1 direction side, and the term "lower surface of the substrate" refers to the surface of the substrate on the Z2 direction side.

[0011] 1. Embodiment 1 In this embodiment, a liquid crystal device will be described as an example of the electro-optical device. The liquid crystal device is an active-drive transmissive liquid crystal device having a TFT (Thin Film Transistor) as a switching element for each pixel. This liquid crystal device is used as a light modulation device in a projection display device, which will be described later. In this embodiment, the projection display device is an example of an electronic device.

[0012] 1.1. Overview of the structure of liquid crystal devices The structure of a liquid crystal device 300 according to this embodiment will be described with reference to Figures 1 and 2. Figure 1 is a plan view of the liquid crystal device 300. Figure 2 is a cross-sectional view of the liquid crystal device 300 taken along line AA in Figure 1.

[0013] 1 and 2, the liquid crystal device 300 has an element substrate 100, a counter substrate 200, a seal member 8, a liquid crystal layer Lc, and a plurality of Peltier elements 20. The liquid crystal device 300 also has a display region A1 and a peripheral region A2. In this embodiment, the element substrate 100 is an example of a first substrate, and the counter substrate 200 is an example of a second substrate.

[0014] The element substrate 100 and the counter substrate 200 each have light-transmitting properties. Note that the term "light-transmitting properties" refers to transparency to visible light, and preferably refers to a visible light transmittance of 50% or more.

[0015] The seal member 8 is disposed in the peripheral region A2 so as to surround the display region A1. The seal member 8 is disposed between the element substrate 100 and the counter substrate 200, and bonds the element substrate 100 and the counter substrate 200. As a material for the seal member 8, for example, an adhesive containing various curable resins such as epoxy resin can be used.

[0016] The liquid crystal layer Lc is provided in an area surrounded by the element substrate 100, the counter substrate 200, and the seal member 8. The liquid crystal layer Lc contains liquid crystal molecules having positive or negative dielectric anisotropy. The liquid crystal layer Lc is an electro-optical layer in which the orientation of the liquid crystal molecules changes in response to an electric field generated by the pixel electrodes 10 and the common electrode 250, thereby changing the optical characteristics.

[0017] In this embodiment, the counter substrate 200 is disposed on the light incident side of the liquid crystal layer Lc, and the element substrate 100 is disposed on the light exit side of the liquid crystal layer Lc. Incident light IL incident on the counter substrate 200 is modulated by the liquid crystal layer Lc and is emitted from the element substrate 100 as modulated light ML.

[0018] The display area A1 has a plurality of pixels P arranged in a matrix, and an image is displayed by the plurality of pixels P. The peripheral area A2 is an area outside the display area A1. A plurality of Peltier elements 20 are provided outside the display area A1. Here, the four peripheral sides of the element substrate 100 or the counter substrate 200 are sides f1, f2, f3, and f4, respectively, and in the peripheral area A2, the area between the side f1 and the display area A1 is e1, the area between the side f2 and the display area A1 is e2, the area between the side f3 and the display area A1 is e3, and the area between the side f4 and the display area A1 is e4. In this embodiment, the plurality of Peltier elements 20 are provided in the areas e1, e2, and e3. The Peltier elements 20 may be provided in all areas including the area e4, or may be provided along only one or two areas among the areas e1, e2, e3, and e4.

[0019] The Peltier element 20 has a P-type semiconductor member 21, an N-type semiconductor member 22, an electrode 23, and an electrode . The P-type semiconductor members 21 and the N-type semiconductor members 22 are alternately arranged along the display area A1. Furthermore, the P-type semiconductor members 21 and the N-type semiconductor members 22 are provided at positions overlapping the seal member 8 in plan view.

[0020] The electrode 23 is disposed between the sealing member 8 and the display region A1 in a plan view in the peripheral region A2. The electrode 23 includes an electrode 23a and an electrode 23b provided adjacent to each other in a direction along the display region A1. The electrode 23 electrically connects the display region A1 side of the P-type semiconductor member 21 and the display region A1 side of the N-type semiconductor member 22. In this embodiment, the electrode 23 functions as a heat absorbing member for the Peltier element 20.

[0021] The electrodes 24 are disposed in the peripheral region A2 between the sealing member 8 and the outer edge of the element substrate 100 in a plan view. The electrodes 24 are provided adjacent to each other in a direction along the display region A1. The electrodes 24 electrically connect the P-type semiconductor member 21 on the opposite side to the display region A1 and the N-type semiconductor member 22 on the opposite side to the display region A1. In this embodiment, the electrodes 24 function as a member for dissipating heat from the Peltier element 20.

[0022] The Peltier element 20 is connected to a DC power supply 150 via an external terminal 9. An electrode 23a of the Peltier element 20 is connected to the positive side of the DC power supply 150, and an electrode 23b of the Peltier element 20 is connected to the negative side of the DC power supply 150. A DC current I is supplied from the DC power supply 150 in the direction of the arrow.

[0023] In this embodiment, the P-type semiconductor member 21 is an example of a first member, and the N-type semiconductor member 22 is an example of a second member. The electrode 23a is an example of a first electrode, the electrode 23b is an example of a second electrode, and the electrode 24 is an example of a third electrode. The direction along the display region A1 is the Y1 direction in region e1, the X1 direction in region e2, and the Y2 direction in region e3.

[0024] A scanning line driving circuit (not shown) is provided outside the area e1 and area e3 of the peripheral area A2. An inspection circuit (not shown) is provided outside the area e4. A plurality of external terminals 9 and a data line driving circuit (not shown) are provided outside the area e4. The shape of the display area A1 is a rectangle, but may be another shape, for example, a circle.

[0025] The element substrate 100 includes a base 90 , a relay wiring layer 50 including a conductive layer and an insulating layer, pixel electrodes 10 , and an alignment film 12 .

[0026] The substrate 90 is a flat plate having optical transparency and insulating properties, and is, for example, a quartz substrate or a glass substrate. The pixel electrode 10 is transparent. The pixel electrode 10 is made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or fluorine-doped tin oxide (FTO). The thickness direction of the pixel electrode 10 coincides with the Z1 direction or the Z2 direction. The alignment film 12 has light-transmitting and insulating properties. The alignment film 12 aligns the liquid crystal molecules of the liquid crystal layer Lc. Examples of materials for the alignment film 12 include silicon oxide (SiO2) and polyimide.

[0027] The counter substrate 200 includes a base 210 , an insulating layer 220 , a common electrode 250 , and an alignment film 260 . The substrate 210 is a flat plate having optical transparency and insulating properties, and is, for example, a quartz substrate or a glass substrate. The insulating layer 220 is transparent and insulating, and is made of an inorganic material such as silicon oxide.

[0028] The common electrode 250 is an electrode disposed opposite the multiple pixel electrodes 10, and may be referred to as a counter electrode. The common electrode 250 includes a transparent conductive material such as ITO, IZO, or FTO.

[0029] The external terminals 9 are mounting terminals on which external connection lines such as FPCs (Flexible Printed Circuits) (not shown) are mounted. A signal source that supplies various signals including an image signal, a synchronization signal, an inspection signal, and the like from the outside, and a power source that supplies voltage and current are connected to the external terminals 9 via the external connection lines.

[0030] 1.2.Electrical configuration of the element substrate FIG. 3 is an equivalent circuit diagram showing the electrical configuration of the element substrate 100. As shown in FIG. 3, a display area A1 of the element substrate 100 is provided with a plurality of transistors 1, n scanning lines 3, m data lines 4, and m capacitance lines 5. n and m are each an integer of 2 or more. The transistors 1 are disposed at intersections between the n scanning lines 3 and the m data lines 4.

[0031] Each of the n scanning lines 3 extends in the X1 direction, and the n scanning lines 3 are arranged at equal intervals in the Y1 direction. Each of the n scanning lines 3 is electrically connected to the gate electrode of the corresponding transistor 1. The n scanning lines 3 are electrically connected to a scanning line driving circuit, and scanning signals G1, G2, ..., and Gn are supplied from the scanning line driving circuit.

[0032] Each of the m data lines 4 extends in the Y1 direction, and the m data lines 4 are arranged at equal intervals in the X1 direction. Each of the m data lines 4 is electrically connected to the source regions of the corresponding transistors 1. The m data lines 4 are electrically connected to a data line driving circuit, and image signals E1, E2, ..., and Em are supplied from the data line driving circuit.

[0033] The n scanning lines 3 and the m data lines 4 are electrically insulated from each other and arranged in a lattice pattern in a plan view. An area surrounded by two adjacent scanning lines 3 and two adjacent data lines 4 corresponds to a pixel P. A pixel electrode 10 is provided for each pixel P. The pixel electrode 10 is electrically connected to the drain region of the transistor 1.

[0034] Each of the m capacitance lines 5 extends in the Y1 direction, and the m capacitance lines 5 are arranged at equal intervals in the X1 direction. The m capacitance lines 5 are electrically insulated from the m data lines 4 and the n scanning lines 3, and are arranged at intervals from these. A fixed potential such as a common potential or a ground potential is applied to each capacitance line 5 via an external terminal 9.

[0035] One electrode of the capacitance element 2 is electrically connected to the capacitance line 5. The other electrode of the capacitance element 2 is electrically connected to the pixel electrode 10 and holds the potential of the image signal supplied to the pixel electrode 10.

[0036] 1.3. Structure of Peltier element Fig. 4 is an explanatory diagram showing the planar structure of the Peltier element 20, and is a partially enlarged plan view of a portion near the region e1 in the peripheral region A2. Fig. 5 is a cross-sectional view taken along the line BB in Fig. 4, and is an explanatory diagram showing the cross-sectional structure of the Peltier element 20.

[0037] As shown in FIG. 4, the Peltier element 20 includes a P-type semiconductor member 21, an N-type semiconductor member 22, an electrode 23a, an electrode 23b, and an electrode .

[0038] In the peripheral area A2, a plurality of Peltier elements 20 are provided along the display area A1. The Peltier elements 20 are connected in series. In Fig. 4, the Peltier elements 20 are provided adjacent to each other in the Y1 and Y2 directions in an area e1 between the display area A1 and the side f1 of the element substrate 100.

[0039] A portion 21a of the P-type semiconductor member 21 on the display region A1 side is electrically connected to the electrode 23a via a contact hole 25. In addition, a portion 21b of the P-type semiconductor member 21 on the opposite side to the display region A1 is electrically connected to the electrode 24 via a contact hole 26.

[0040] The N-type semiconductor member 22 is provided adjacent to the P-type semiconductor member 21 in the Y1 direction. A portion 22b of the N-type semiconductor member 22 opposite the display region A1 is electrically connected to the electrode 24 via a contact hole 28. In addition, a portion 22a of the N-type semiconductor member 22 on the display region A1 side is electrically connected to the electrode 23b via a contact hole 27. The electrode 23b is electrically connected via a contact hole 29 to the display area A1 side of the P-type semiconductor member 21 of the Peltier element 20 provided adjacently in the Y1 direction.

[0041] The Peltier element 20 has the Peltier effect, which is a phenomenon in which, when different types of conductors or semiconductors are electrically connected in series and a direct current is passed through the PN junction, heat absorption occurs at the N→P junction and heat dissipation occurs at the P→N junction.

[0042] As shown in FIG. 1, by passing a direct current I from electrode 23a to electrode 23b of Peltier element 20, heat absorption occurs at electrode 23a and electrode 23b between N-type semiconductor member 22 and P-type semiconductor member 21, which form the N→P junction, and heat is generated at electrode 24 between the P-type semiconductor member 21 and N-type semiconductor member 22, which forms the N→P junction.

[0043] The heat absorbed by the electrodes 23a and 23b is released from the electrode 24 to the outside of the liquid crystal device 300. In this manner, in the liquid crystal device 300, the liquid crystal layer Lc can be cooled by the Peltier element 20.

[0044] The heat absorbing electrodes 23 are provided adjacent to each other in the direction along the display area A1. Therefore, the arrangement pitch of the electrodes 23 does not depend on the arrangement pitch of the pixel electrodes 10. Therefore, regardless of the arrangement pitch of the pixel electrodes 10, the electrodes 23 can be provided at a desired pitch. 4, the arrangement pitch of the electrodes 23 is larger than the arrangement pitch of the pixel electrodes 10, but this is not limiting and the arrangement pitch may be smaller than the arrangement pitch of the pixel electrodes 10. Furthermore, the arrangement pitch of the electrodes 23 may be changed depending on the location. For example, the arrangement pitch of the electrodes 23 may be changed near the center of the region e2 and near both sides.

[0045] In this way, the arrangement of the Peltier elements 20 can be optimized according to the required cooling capacity or to enhance the cooling efficiency, without depending on the arrangement pitch of the pixel electrodes 10. For example, they can be arranged at a pitch smaller than the pixel pitch. Also, if there is unevenness in temperature depending on the location, the arrangement pitch of the Peltier elements 20 can be changed depending on the location to reduce the temperature unevenness.

[0046] On the other hand, in the device described in Patent Document 1, a light-shielding film arranged in the display area to correspond to the scanning lines and data lines is used as a heat sink for the Peltier elements, so the arrangement pitch of the Peltier elements depends on the arrangement pitch of the scanning lines and data lines, in other words, the arrangement pitch of the pixel electrodes.

[0047] The heat absorbing electrodes 23 are provided adjacent to each other in a direction along the display area A1. In other words, the heat absorbing electrodes 23 are not provided in the display area A1. Therefore, the incident light IL that enters the display area A1 does not hit the electrodes 23. This makes it possible to prevent the electrodes 23 from becoming hot due to being illuminated by the incident light IL, which would increase the temperature of the liquid crystal layer Lc. On the other hand, in the device described in Patent Document 1, the light-shielding film used as a heat sink is placed in the display area, so that the light-shielding film is illuminated by incident light, causing it to become hot and reducing its cooling ability.

[0048] As shown in FIG. 5, the P-type semiconductor member 21 is provided on the TFT layer 40. The TFT layer 40 has an insulating layer 43 and a transistor 1 provided between the insulating layers 43. The transistor 1 is composed of a semiconductor layer 41 having an LDD (Lightly Doped Drain) structure and a gate electrode 42. Note that the layer on which the P-type semiconductor member 21 and the N-type semiconductor member 22 are provided is not limited to the TFT layer 40. Other examples of the layer on which the P-type semiconductor member 21 and the N-type semiconductor member 22 are provided will be described in the modified examples described later.

[0049] In this embodiment, the P-type semiconductor member 21 is formed in the same layer and made of the same material as the semiconductor layer 41. Although not shown, the N-type semiconductor member 22 is also formed in the same layer and made of the same material as the semiconductor layer 41. Specifically, the P-type semiconductor member 21 and the N-type semiconductor member 22 are made of polysilicon. The P-type semiconductor member 21 has a thickness of, for example, 1E+12 cm 3 ~1E+16cm 3 The N-type semiconductor member 22 contains a P-type impurity with a concentration of about 1E+12 cm 3 ~1E+16cm 3 It contains a concentration of N-type impurities of about

[0050] The P-type semiconductor member 21 and the N-type semiconductor member 22 may be a combination of thermoelectric materials such as Group 4 element (Si, Ge, Sn, Pb, etc.) based semiconductors, Group 3 element (B, Al, Ga, In, etc.) based semiconductors and Group 5 element (N, P, As, Sb, etc.) based semiconductors, or Group 2 element (Zn, Cd, Hg, etc.) based semiconductors and Group 6 element (S, Se, Te, Po, etc.) based semiconductors.

[0051] The electrodes 23 and 24 are provided on the relay wiring layer 50 . The relay wiring layer 50 includes an insulating layer 54 and conductive layers 51, 52, and 53 provided between the insulating layers 54.

[0052] The insulating layer 54 is transparent and insulating, and is made of an inorganic material such as silicon oxide. The conductive layers 51, 52, and 53 are formed of a conductive material having a light-shielding property. Examples of the conductive material having a light-shielding property include metals such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), and aluminum (AL), metal nitrides, and metal silicides. The term "light-shielding property" refers to a property of blocking visible light, and preferably refers to a visible light transmittance of less than 50%, and more preferably refers to a visible light transmittance of 10% or less.

[0053] The conductive layers 51, 52, and 53 form the scanning lines 3, the data lines 4, the capacitance lines 5, the electrodes of the capacitance elements 2, and other relay electrodes. The number of conductive layers may be two or less or four or more.

[0054] In this embodiment, the electrodes 23 and 24 are formed in the relay wiring layer 50 in the same layer and made of the same material as the conductive layer 51. The electrodes 23 and 24 may be formed in the same layer and made of the same material as the conductive layer 52 or the conductive layer 53. The electrodes 23 and 24 may be formed in the same layer as different conductive layers. The layer on which the electrodes 23 and 24 are provided is not limited to the relay wiring layer 50. Other examples of the layers on which the electrodes 23 and 24 are provided will be described in the modified examples described later.

[0055] The electrode 23 is electrically connected to the P-type semiconductor member 21 through a contact hole 25. The electrode 24 is electrically connected to the P-type semiconductor member 21 through a contact hole 26. The electrode 23 and the P-type semiconductor member 21 may be electrically connected to each other through a contact plug made of a conductive material provided in the contact hole 25. Similarly, the electrode 24 and the P-type semiconductor member 21 may be electrically connected to each other through a contact plug made of a conductive material provided in the contact hole 26. Although not shown, the contact holes 27 and 28 may also be configured to have contact plugs.

[0056] 1.4. Variations There may be various modifications to the embodiment of the cross-sectional structure of the Peltier element 20 described above. Specific modifications will be exemplified below.

[0057] 1.4.1. Variation 1 FIG. 6A is an explanatory diagram showing a cross-sectional structure of the Peltier element 20 according to the first modification, and is a cross-sectional view taken along the line BB in FIG. 4, similar to FIG. In the first modification, the layers on which the P-type semiconductor member 21 and the N-type semiconductor member 22 are provided are different from those in the example shown in FIG.

[0058] As shown in FIG. 6A, the P-type semiconductor member 21 is provided on the lower layer 30. The lower layer 30 is an insulating layer between the base 90 and the TFT layer 40, and is made of a light-transmitting inorganic material such as silicon oxide. The lower layer 30 may be provided with a light-shielding layer (not shown). Although not shown, the N-type semiconductor member 22 is provided in the same layer as the P-type semiconductor member 21 .

[0059] 1.4.2. Variation 2 FIG. 6B is an explanatory diagram showing the cross-sectional structure of the Peltier element 20 according to the second modification, and is a cross-sectional view taken along the line BB in FIG. 4, similar to FIG. In the second modification, the Peltier element 20 is provided on the relay wiring layer 50. As shown in FIG. 6B, the P-type semiconductor member 21, the electrode 23, and the electrode 24 are provided on the relay wiring layer 50. Although not shown, the N-type semiconductor member 22, the electrode 23, and the electrode 24 are also provided on the relay wiring layer 50 in the same manner.

[0060] Variation 3 FIG. 6C is an explanatory diagram showing a cross-sectional structure of the Peltier element 20 according to Modification 3, and is a cross-sectional view taken along the line BB in FIG. 4, similar to FIG. In the third modification, the P-type semiconductor member 21 is provided on the surface layer 60 . The surface layer 60 is a protective layer between the pixel electrodes 10 and the relay wiring layer 50, and is made of an inorganic material having translucency and moisture absorption properties, such as BSG (Borosilicate Glass). Although not shown, the N-type semiconductor member 22 is also provided on the surface layer 60, similar to the P-type semiconductor member 21.

[0061] The electrodes 23 and 24 are provided in the relay wiring layer 50. The electrodes 23 and 24 may be provided in the TFT layer 40 or the lower layer 30.

[0062] Variation 4 FIG. 6D is an explanatory diagram showing a cross-sectional structure of the Peltier element 20 according to Modification 4, and is a cross-sectional view taken along line BB of FIG. 4, similar to FIG. In the fourth modification, the Peltier element 20 is provided on the counter substrate 200.

[0063] As shown in FIG. 6D, the P-type semiconductor member 21 is provided on an insulating layer 220. The electrodes 23 and 24 are provided on the surface layer 240. The surface layer 240 is a protective layer between the common electrode 250 and the lens forming layer 230. The electrodes 23 and 24 may be provided on the insulating layer 220 or the lens forming layer 230. Although not shown, the N-type semiconductor member 22 is also provided on the insulating layer 220, similar to the P-type semiconductor member 21.

[0064] The electrode 23 is electrically connected to the P-type semiconductor member 21 via a contact plug provided in a contact hole 25. In addition, the electrode 24 is electrically connected to the P-type semiconductor member 21 via a contact plug provided in a contact hole 26.

[0065] Variation 5 FIG. 6E is an explanatory diagram showing a cross-sectional structure of the Peltier element 20 according to Modification 5, and is a cross-sectional view taken along the line BB in FIG. 4, similar to FIG.

[0066] In the fifth modification, the P-type semiconductor member 21 is provided on the lens formation layer 230. The lens forming layer 230 includes lenses 231 and a light-transmitting layer 232. The lenses 231 are formed of an inorganic material having a different refractive index from that of the light-transmitting layer 232. For example, the lenses 231 are formed of silicon oxynitride (SiON), and the light-transmitting layer 232 is formed of an inorganic material such as silicon oxide. Although not shown, the N-type semiconductor member 22 is also provided on the lens formation layer 230, similar to the P-type semiconductor member 21.

[0067] Variation 6 FIG. 6F is an explanatory diagram showing a cross-sectional structure of the Peltier element 20 according to Modification 6, and is a cross-sectional view taken along line BB of FIG. 4, similar to FIG.

[0068] In the sixth modification, the P-type semiconductor member 21 is provided on the surface layer 240. Although not shown, the N-type semiconductor member 22 is also provided on the surface layer 240, similar to the P-type semiconductor member 21. The electrodes 23 and 24 are provided on the lens formation layer 230. The electrodes 23 and 24 may be provided on the insulating layer 220 or the surface layer 240.

[0069] Variation 7 In the above-described example, the Peltier element 20 is provided on either the element substrate 100 or the counter substrate 200, but the Peltier element 20 may be provided on both the element substrate 100 or the counter substrate 200.

[0070] As described above, the liquid crystal device 300 serving as an electro-optical device according to this embodiment has the following advantages. The liquid crystal device 300 of this embodiment is a liquid crystal device 300 equipped with a Peltier element 20 outside the display region A1, and the Peltier element 20 has a P-type semiconductor member 21 as a first member of a first conductivity type, an N-type semiconductor member 22 as a second member of a second conductivity type arranged adjacent to the P-type semiconductor member 21 in the Y1 direction which is the direction along the display region A1, an electrode 23a as a first electrode in contact with a portion 21a of the P-type semiconductor member 21 on the display region A1 side, an electrode 23b as a second electrode arranged adjacent to the electrode 23a in the Y1 direction and in contact with a portion 22a of the N-type semiconductor member 22 on the display region A1 side, and an electrode 24 as a third electrode in contact with the portion 21b of the P-type semiconductor member 21 on the opposite side to the display region A1 side and the portion 22b of the N-type semiconductor member 22 on the opposite side to the display region A1 side.

[0071] In this manner, the P-type semiconductor member 21 and the N-type semiconductor member 22 are provided adjacent to each other outside the display region A1 in the Y1 direction which is the direction along the display region A1.

[0072] Therefore, the arrangement pitch of the Peltier elements 20 can be optimized regardless of the arrangement pitch of the pixel electrodes 10, so that the cooling capacity or cooling efficiency of the Peltier elements 20 can be maximized. Furthermore, since the Peltier element 20 is not disposed in the display area A1, the incident light IL entering the display area A1 does not strike the Peltier element 20. This makes it possible to prevent the incident light IL from increasing the temperature of the Peltier element 20 and thus the increase in the temperature of the liquid crystal layer Lc.

[0073] The liquid crystal device 300 of this embodiment further includes an element substrate 100 as a first substrate, a counter substrate 200 as a second substrate opposite the element substrate 100, a liquid crystal layer Lc as an electro-optical layer sandwiched between the element substrate 100 and the counter substrate 200, and a sealing member 8 arranged to surround the liquid crystal layer Lc, and the P-type semiconductor member 21 and the N-type semiconductor member 22 overlap with the sealing member 8 in a planar view.

[0074] In this way, the P-type semiconductor member 21 and the N-type semiconductor member 22 overlap with the sealing member 8 in a plan view. Therefore, the P-type semiconductor member 21 and the N-type semiconductor member 22 can be efficiently arranged outside the display region A1, and a configuration can be achieved that makes it easy to narrow the frame.

[0075] The liquid crystal device 300 of this embodiment further includes an element substrate 100 as a first substrate, a counter substrate 200 as a second substrate opposite the element substrate 100, a liquid crystal layer Lc as an electro-optical layer sandwiched between the element substrate 100 and the counter substrate 200, and a sealing member 8 arranged to surround the liquid crystal layer Lc, and the electrode 23a as the first electrode and the electrode 23b as the second electrode overlap between the sealing member 8 and the display area A1 in a planar view.

[0076] In this way, the electrodes 23a and 23b overlap the gap between the seal member 8 and the display region A1 outside the display region A1. In other words, the electrodes 23a and 23b overlap the liquid crystal layer Lc outside the display region A1. Therefore, the electrodes 23a and 23b, which are heat absorbing members of the Peltier element 20, can be provided at positions overlapping the liquid crystal layer Lc, thereby improving the cooling capacity or cooling efficiency of the Peltier element 20.

[0077] The liquid crystal device 300 of this embodiment further includes an element substrate 100 as a first substrate, and a counter substrate 200 as a second substrate opposed to the element substrate 100. The Peltier element 20 is provided on the element substrate 100 or the counter substrate 200.

[0078] In this manner, the Peltier elements 20 are provided on the element substrate 100 or the counter substrate 200. In other words, one pair of Peltier elements 20 may be provided on the element substrate 100, and another pair of Peltier elements 20 may be provided on the counter substrate 200. Therefore, the cooling capacity or cooling efficiency of the Peltier element 20 can be easily increased.

[0079] The liquid crystal device 300 of this embodiment further includes an element substrate 100 as a first substrate, and an opposing substrate 200 as a second substrate opposed to the element substrate 100. The element substrate 100 has a plurality of external terminals 9 as a plurality of terminals, a side f4 as a first side along the plurality of external terminals 9, a side f1 as a second side intersecting with side f4, and a side f3 as a third side, and a side f2 as a fourth side opposed to side f4 and intersecting with sides f1 and f3. The Peltier elements 20 are arranged in a region e1 between the display region A1 and the side f1 of the element substrate 100, a region e2 between the display region A1 and the side f2 of the element substrate 100, and a region e3 between the display region A1 and the side f3 of the element substrate 100, when viewed in a plane.

[0080] Thus, in a plan view, the Peltier elements 20 are arranged in an area e1 between the display area A1 and the side f1 of the element substrate 100, an area e2 between the display area A1 and the side f2 of the element substrate 100, and an area e3 between the display area A1 and the side f3 of the element substrate 100. Therefore, a Peltier element 20 with high cooling capacity or cooling efficiency can be realized.

[0081] 2. Embodiment 2 A liquid crystal device 300 as an electro-optical device according to a second embodiment will be described with reference to FIGS. Fig. 7 is an explanatory diagram showing the planar structure of the Peltier element 20 according to embodiment 2, and is a partially enlarged plan view of a portion near region e1 in the peripheral region A2, similar to Fig. 4. Fig. 8 is a flowchart showing a method for manufacturing the Peltier element 20 according to embodiment 2. Figs. 9 to 12 are plan views showing one step of the method for manufacturing the Peltier element 20. The same components as those in the first embodiment are denoted by the same reference numerals and the description thereof will be omitted.

[0082] 2.1. Structure of Peltier element As shown in FIG. 7, in a liquid crystal device 300 of the second embodiment, the Peltier element 20 has a P-type semiconductor region 71, an N-type semiconductor region 72, a junction region 73, and another junction region 74.

[0083] An N-type semiconductor region 72a is provided in the Y1 direction of the P-type semiconductor region 71 with a junction region 74 interposed therebetween, and an N-type semiconductor region 72b is provided in the Y2 direction of the P-type semiconductor region 71 with a junction region 73 interposed therebetween. The P-type semiconductor region 71 is a region in the semiconductor member 70 that contains P-type impurities, and the N-type semiconductor regions 72a and 72b are regions in the semiconductor member 70 that contain N-type impurities.

[0084] The junction region 73 is the portion where a portion 71a of the P-type semiconductor region 71 on the display region A1 side and a portion 72ba of the N-type semiconductor region 72b on the display region A1 side are in contact, and the junction region 74 is the portion where a portion 71b of the P-type semiconductor region 71 on the opposite side of the display region A1 and a portion 72ab of the N-type semiconductor region 72a on the opposite side of the display region A1 are in contact.

[0085] In the second embodiment, the P-type semiconductor region 71 is an example of a first region, the N-type semiconductor region 72a is an example of a second region, and the N-type semiconductor region 72b is an example of a third region. The junction region 73 is an example of a first junction region, and the junction region 74 is an example of a second junction region.

[0086] In the second embodiment, a DC power source is connected so that bonding region 73 becomes the anode side, and a DC current is passed from bonding region 73 to bonding region 74, whereby heat is absorbed in bonding region 73 and heat is generated in bonding region 74.

[0087] The heat absorbed in the bonding region 73 is released from the bonding region 74 to the outside of the liquid crystal device 300. In this manner, in the liquid crystal device 300, the liquid crystal layer Lc can be cooled by the Peltier element 20.

[0088] In this way, the Peltier element 20 of the second embodiment does not have the heat absorbing electrode 23 and the heat dissipating electrode 24. Therefore, the structure of the Peltier element 20 can be simplified, and the structure can be made suitable for narrowing the frame or making the device thinner.

[0089] 2.2. Manufacturing method of Peltier element Next, a method for manufacturing the Peltier element 20 of the second embodiment will be described with reference to the flow chart of FIG. In step S1, the semiconductor member 70 is formed. The semiconductor member 70, which serves as a base material, is formed on a desired layer on a substrate 90, and then patterned as shown in Fig. 9. The semiconductor member 70 is made of silicon.

[0090] In step S2, a mask 80 is formed to provide the P-type semiconductor region 71. As shown in Fig. 10, the mask 80 is formed by patterning a resist so as to cover the region of the semiconductor member 70 where the N-type semiconductor region 72 is to be provided.

[0091] In step S3, P-type impurities are implanted into the semiconductor member 70. Through this process, a P-type semiconductor region 71 is formed in the semiconductor member 70, as shown in FIG. In step S4, a mask 80 is formed in order to provide the N-type semiconductor region 72. The mask 80 is formed by patterning a resist so as to cover the P-type semiconductor region 71 in the semiconductor member 70.

[0092] In step S5, the semiconductor member 70 is implanted with an N-type impurity. Through this process, an N-type semiconductor region 72 is formed in the semiconductor member 70, as shown in Fig. 12. In addition, a junction region 73 is formed in the boundary between the P-type semiconductor region 71 and the N-type semiconductor region 72 on the display region A1 side, and a junction region 74 is formed in the boundary between the P-type semiconductor region 71 and the N-type semiconductor region 72 on the opposite side to the display region A1.

[0093] As described above, according to the liquid crystal device 300 serving as an electro-optical device of the second embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

[0094] The liquid crystal device 300 of embodiment 2 is an electro-optical device having a Peltier element 20 made of a semiconductor member 70 outside the display region A1, and the Peltier element 20 has, in the semiconductor member 70, a P-type semiconductor region 71 as a first region of a first conductivity type, an N-type semiconductor region 72a as a second region of a second conductivity type adjacent to the P-type semiconductor region 71 in the Y1 direction which is the direction along the display region A1, an N-type semiconductor region 72b as a third region of the second conductivity type adjacent to the P-type semiconductor region 71 in the Y2 direction which is the opposite direction to the Y1 direction, a junction region 73 as a first junction region where a portion 71a of the P-type semiconductor region 71 on the display region A1 side and a portion 72ba of the N-type semiconductor region 72b on the display region A1 side are in contact, and a junction region 74 as a second junction region where a portion 71b of the P-type semiconductor region 71 on the opposite side of the display region A1 and a portion 72ab of the N-type semiconductor region 72a on the opposite side of the display region A1 are in contact.

[0095] In this way, the P-type semiconductor region 71 and the N-type semiconductor region 72a are provided adjacent to each other in the Y1 direction outside the display area A1, and the P-type semiconductor region 71 and the N-type semiconductor region 72b are provided adjacent to each other in the Y2 direction outside the display area A1. In other words, the Peltier elements 20 are provided adjacent to each other in the Y1 direction outside the display area A1.

[0096] Therefore, the arrangement pitch of the Peltier elements 20 can be optimized regardless of the arrangement pitch of the pixel electrodes 10, so that the cooling capacity or cooling efficiency of the Peltier elements 20 can be maximized. Furthermore, since the Peltier element 20 is not disposed in the display area A1, the incident light IL entering the display area A1 does not strike the Peltier element 20. This makes it possible to prevent the incident light IL from increasing the temperature of the Peltier element 20 and thus the increase in the temperature of the liquid crystal layer Lc.

[0097] The liquid crystal device 300 of this embodiment further includes an element substrate 100 as a first substrate, a counter substrate 200 as a second substrate facing the element substrate 100, a liquid crystal layer Lc as an electro-optical layer sandwiched between the element substrate 100 and the counter substrate 200, and a sealing member 8 arranged to surround the liquid crystal layer Lc, and the semiconductor member 70 overlaps with the sealing member 8 in a planar view.

[0098] Thus, in a plan view, the semiconductor member 70 overlaps with the seal member 8. Therefore, the semiconductor member 70 can be efficiently disposed outside the display region A1, and a configuration can be achieved that makes it easy to narrow the frame.

[0099] The liquid crystal device 300 of this embodiment further includes an element substrate 100 as a first substrate, and a counter substrate 200 as a second substrate opposed to the element substrate 100. The Peltier element 20 is provided on the element substrate 100 or the counter substrate 200.

[0100] In this manner, the Peltier elements 20 are provided on the element substrate 100 or the counter substrate 200. In other words, one pair of Peltier elements 20 may be provided on the element substrate 100, and another pair of Peltier elements 20 may be provided on the counter substrate 200. Therefore, the cooling capacity or cooling efficiency of the Peltier element 20 can be easily increased.

[0101] The liquid crystal device 300 of this embodiment further includes an element substrate 100 as a first substrate, and an opposing substrate 200 as a second substrate opposed to the element substrate 100. The element substrate 100 has a plurality of external terminals 9 as a plurality of terminals, a side f4 as a first side along the plurality of external terminals 9, a side f1 as a second side intersecting with the side f4, and a side f3 as a third side, and a side f2 as a fourth side opposed to the side f4 and intersecting with the sides f1 and f3. The plurality of Peltier elements 20 are arranged in a region e1 between the display region A1 and the side f1 of the element substrate 100, a region e2 between the display region A1 and the side f2 of the element substrate 100, and a region e3 between the display region A1 and the side f3 of the element substrate 100, when viewed in a plane.

[0102] Thus, in a plan view, the Peltier elements 20 are arranged in an area e1 between the display area A1 and the side f1 of the element substrate 100, an area e2 between the display area A1 and the side f2 of the element substrate 100, and an area e3 between the display area A1 and the side f3 of the element substrate 100. Therefore, a Peltier element 20 with high cooling capacity or cooling efficiency can be realized.

[0103] 3. Embodiment 3 FIG. 13 is a schematic diagram showing an example of an electronic device, and is a schematic diagram showing a schematic configuration of a projection type display device 1000 as the electronic device. The projection display device 1000 is, for example, a three-panel projector equipped with three of the above-mentioned liquid crystal devices 300. The liquid crystal device 300R corresponds to a red display color, the liquid crystal device 300G corresponds to a green display color, and the liquid crystal device 300B corresponds to a blue display color. The control unit 1005 includes, for example, a processor and a memory, and controls the operations of the liquid crystal devices 300R, 300G, and 300B.

[0104] The illumination optical system 1001 supplies a red component RL of light emitted from an illumination device 1002, which is a light source, to the liquid crystal device 300R, a green component GL to the liquid crystal device 300G, and a blue component BL to the liquid crystal device 300B. Each of the liquid crystal devices 300R, 300G, and 300B functions as a light modulation device that modulates the respective color lights RL, GL, and BL supplied from the illumination optical system 1001 in accordance with a display image. The projection optical system 1003 combines the light emitted from the liquid crystal device 300R, the liquid crystal device 300G, and the liquid crystal device 300B, and projects the combined light onto the screen 1004.

[0105] As described above, the projection display device 1000 serving as the electronic device of this embodiment includes the liquid crystal device 300 described above. Therefore, by employing the liquid crystal device 300 that has high electrical reliability, the performance of the projection display device 1000 can be improved.

[0106] The electronic device is not limited to the exemplified three-panel projector. For example, it may be a single-panel, two-panel, or projector equipped with four or more liquid crystal devices 300. The electronic device may also be a smartphone, a PDA (Personal Digital Assistant), a camera, a television, a car navigation device, a personal computer, a display, electronic paper, a calculator, a videophone, a POS (Point of Sale), a printer, a scanner, a copier, a video player, or a device equipped with a touch panel.

[0107] Although the preferred embodiment has been described above, the present invention is not limited to the above embodiment. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as the above embodiment, and any configuration can be added. [Explanation of symbols]

[0108] 1...transistor, 2...capacitive element, 3...scanning line, 4...data line, 5...capacitive line, 8...sealing member, 9...external terminal, 10...pixel electrode, 12...alignment film, 20...Peltier element, 21...P-type semiconductor member, 21a, 21b...portion, 22...N-type semiconductor member, 22a, 22b...portion, 23, 23a, 23b...electrode, 24...electrode, 25, 26, 27, 28, 29...contact hole, 30...lower layer, 40...TFT layer, 41...semiconductor layer, 42...gate electrode, 43...insulating layer, 50...relay wiring layer, 51...conductive layer, 52...conductive layer, 53...conductive layer, 54...insulating layer, 60...surface layer, 70...semiconductor member, 71...P-type semiconductor region, 72...N-type semiconductor region, 72a...N N-type semiconductor region, 72b...N-type semiconductor region, 73...junction region, 74...junction region, 80...mask, 90...base, 100...element substrate, 200...opposite substrate, 210...base, 220...insulating layer, 230...lens forming layer, 231...lens, 232...light-transmitting layer, 240...surface layer, 250...common electrode, 260...alignment film, 300, 300B, 300G, 300R...liquid crystal device, 1000...projection display device, 1001...illumination optical system, 1002...illumination device, 1003...projection optical system, 1004...screen, 1005...control unit, A1...display region, A2...peripheral region, E1...image signal, G1...scanning signal, e1, e2, e3, e4...region, f1, f2, f3, f4...side

Claims

1. An electro-optical device having a Peltier element outside a display area, The Peltier element is A first member of a first conductivity type; the first member and a second member of a second conductivity type adjacent to each other in a direction along the display area; A first electrode in contact with a portion of the first member on the display area side; a second electrode provided adjacent to the first electrode in the direction and in contact with a portion of the second member on the display area side; a third electrode in contact with a portion of the first member and the second member opposite to the display area side; Electro-optical device.

2. A first substrate; a second substrate facing the first substrate; an electro-optical layer provided between the first substrate and the second substrate; a seal member provided to surround the electro-optic layer; The first member and the second member overlap with the seal member in a plan view.

2. The electro-optical device according to claim 1.

3. A first substrate; a second substrate facing the first substrate; an electro-optical layer provided between the first substrate and the second substrate; a seal member provided to surround the electro-optic layer; the first electrode and the second electrode overlap a portion between the seal member and the display area in a plan view; 2. The electro-optical device according to claim 1.

4. A first substrate; a second substrate facing the first substrate, The Peltier element is provided on the first substrate or the second substrate.

2. The electro-optical device according to claim 1.

5. A first substrate; a second substrate facing the first substrate, The first substrate is A plurality of terminals; A first side along the plurality of terminals; a second side and a third side intersecting the first side; a fourth side that faces the first side and intersects with the second side and the third side, the Peltier elements are arranged in a region between the display area and the second side of the first substrate, a region between the display area and the fourth side of the first substrate, and a region between the display area and the third side of the first substrate in a plan view.

2. The electro-optical device according to claim 1.

6. An electro-optical device having a Peltier element made of a semiconductor material outside a display area, The Peltier elements are each provided on the semiconductor member. a first region of a first conductivity type; a second region of a second conductivity type adjacent to the first region in a direction along the display region; a third region of the second conductivity type adjacent to the first region in a direction opposite to the direction; a first joint region where a portion of the first region on the display region side and a portion of the third region on the display region side are in contact with each other; a second bonding region in which a portion of the first region opposite to the display region and a portion of the second region opposite to the display region are in contact with each other; Electro-optical device.

7. A first substrate; a second substrate facing the first substrate; an electro-optical layer provided between the first substrate and the second substrate; a seal member provided to surround the electro-optic layer; The semiconductor member overlaps with the sealing member in a plan view.

7. The electro-optical device according to claim 6.

8. A first substrate; a second substrate facing the first substrate, The Peltier element is provided on the first substrate or the second substrate.

7. The electro-optical device according to claim 6.

9. A first substrate; a second substrate facing the first substrate, The first substrate is A plurality of terminals; A first side along the plurality of terminals; a second side and a third side intersecting the first side; a fourth side that faces the first side and intersects with the second side and the third side, The Peltier elements are arranged in a region between the display area and the second side of the first substrate, a region between the display area and the fourth side of the first substrate, and a region between the display area and the third side of the first substrate in a plan view.

7. The electro-optical device according to claim 6.

10. 10. An electronic device comprising the electro-optical device according to claim 1.

Images