Image sensor

Abstract

To provide image sensors that can reduce a dark current and reduce or prevent optical crosstalk.SOLUTION: An image sensor according to the present invention comprises: a semiconductor substrate including a first surface and a second surface opposite the first surface and containing a photoelectric conversion region inside; a transmission gate located on the first surface of the semiconductor substrate; an embedded insulating film placed on the first surface of the semiconductor substrate and covering the transmission gate; a pixel separation structure extending from the first surface to the second surface of the semiconductor substrate, located in a pixel separation trench through the embedded insulating film to define a plurality of pixels on the semiconductor substrate, and in which a portion of the pixel separation structure is covered with the embedded insulating film.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to image sensors, and more particularly to image sensors that include deep trench isolation structures. [Background technology]

[0002] An image sensor is a device that converts an optical image signal into an electrical signal. The image sensor has a plurality of pixels, each of which includes a photodiode region that receives incident light and converts it into an electrical signal, and a pixel circuit that outputs a pixel signal using charges generated in the photodiode region. As the integration density of the image sensor increases, the size of each pixel becomes smaller, which makes it difficult to reduce or suppress dark current. Summary of the Invention [Problem to be solved by the invention]

[0003] An object of the present invention is to provide an image sensor capable of reducing dark current and reducing or preventing optical crosstalk. [Means for solving the problem]

[0004] In order to achieve the above-mentioned object, an image sensor according to one embodiment of the present invention includes a semiconductor substrate having a first surface and a second surface opposite to the first surface and including a photoelectric conversion region therein, a transfer gate disposed on the first surface of the semiconductor substrate, a buried insulating film disposed on the first surface of the semiconductor substrate and covering the transfer gate, and a pixel isolation structure disposed in a pixel isolation trench extending from the first surface to the second surface of the semiconductor substrate and penetrating the buried insulating film, the pixel isolation structure defining a plurality of pixels in the semiconductor substrate, a portion of the pixel isolation structure being covered by the buried insulating film.

[0005] In order to achieve the above object, an image sensor according to another aspect of the present invention includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, the semiconductor substrate including a photoelectric conversion region therein, a transfer gate disposed on the first surface of the semiconductor substrate, an etch stop layer disposed on the first surface of the semiconductor substrate and covering the transfer gate, and a pixel isolation structure disposed in a pixel isolation trench extending from the first surface toward the second surface of the semiconductor substrate, the pixel isolation structure including a conductive layer including a reflective metal material, an end of the etch stop layer being disposed on the conductive layer, and the pixel isolation structure and the etch stop layer do not vertically overlap.

[0006] In order to achieve the above object, an image sensor according to yet another aspect of the present invention includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, the semiconductor substrate including a photoelectric conversion region therein, a transmission gate disposed on the first surface of the semiconductor substrate, and a pixel isolation structure disposed in a pixel isolation trench extending from the first surface to the second surface of the semiconductor substrate, the pixel isolation structure including: a conductive layer disposed in the pixel isolation trench and extending in a vertical direction perpendicular to the first surface of the semiconductor substrate; a barrier conductive layer disposed on a sidewall of the conductive layer in the pixel isolation trench; a pixel isolation insulating layer disposed on the conductive layer and the barrier conductive layer in the pixel isolation trench; and an insulating liner extending in the vertical direction on an inner wall of the pixel isolation trench and covering a sidewall of the pixel isolation insulating layer and a sidewall of the barrier conductive layer, the upper surface of the pixel isolation insulating layer being disposed at a level higher than the first surface of the semiconductor substrate. Effect of the Invention

[0007] According to the present invention, a pixel separation structure of an image sensor includes a conductive layer made of a reflective metal material, thereby reducing or preventing optical crosstalk that occurs when light is transmitted through or incident on adjacent pixels. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 is a block diagram illustrating a configuration of an image sensor according to an exemplary embodiment. [Diagram 2] FIG. 2 is a block diagram illustrating a configuration of an image sensor according to an exemplary embodiment. [Diagram 3] FIG. 2 is a readout circuit diagram of an image sensor according to an example embodiment. [Figure 4] FIG. 2 is a layout diagram illustrating an image sensor according to an example embodiment. [Diagram 5] 5 is a cross-sectional view taken along the line A1-A1' in FIG. [Figure 6] FIG. 6 is a plan view at a first vertical level of FIG. 5. [Figure 7] FIG. 6 is a plan view at a second vertical level of FIG. 5. [Figure 8] 1 illustrates a cross-sectional view of an image sensor according to an example embodiment. [Figure 9] FIG. 9 is a plan view at a second vertical level of FIG. 8. [Figure 10] 1 illustrates a cross-sectional view of an image sensor according to an example embodiment. [Figure 11] 1 illustrates a cross-sectional view of an image sensor according to an example embodiment. [Figure 12] FIG. 12 is a plan view at a second vertical level of FIG. 11. [Figure 13] 1 illustrates a cross-sectional view of an image sensor according to an example embodiment. [Figure 14] 1 illustrates a cross-sectional view of an image sensor according to an example embodiment. [Figure 15] 1 illustrates a cross-sectional view of an image sensor according to an example embodiment. [Figure 16] 1 illustrates a cross-sectional view of an image sensor according to an example embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

[0010] FIG. 1 is a block diagram illustrating a configuration of an image sensor 1100 according to an example embodiment.

[0011] Referring to FIG. 1, an image sensor 1100 includes a pixel array 1110, a controller 1130, a row driver 1120, and a pixel signal processing unit 1140.

[0012] The pixel array 1110 includes a plurality of unit pixels arranged two-dimensionally, each of which includes an organic photoelectric conversion element. The photoelectric conversion element absorbs light to generate electric charges, and an electric signal (output voltage) based on the generated electric charges is provided to a pixel signal processor 1140 via a vertical signal line. The unit pixels included in the pixel array 1110 provide output voltages one at a time in row units, so that the unit pixels belonging to one row of the pixel array 1110 are simultaneously activated by a selection signal output by a row driver 1120. The unit pixels belonging to the selected row provide output voltages based on the absorbed light to an output line of a corresponding column.

[0013] The controller 1130 controls the row driver 1120 so that the pixel array 1110 absorbs light and accumulates charges, temporarily stores the accumulated charges, or outputs an electrical signal based on the stored charges to the outside of the pixel array 1110. The controller 1130 also controls the pixel signal processor 1140 so as to sense an output voltage provided by the pixel array 1110.

[0014] The pixel signal processing unit 1140 includes a correlated double sampler (CDS) 1142, an analog-to-digital converter (ADC) 1144, and a buffer 1146. The correlated double sampler 1142 samples and holds the output voltage provided by the pixel array 1110. The correlated double sampler 1142 double samples a specific noise level and a level according to the generated output voltage, and outputs a level corresponding to the difference. In addition, the correlated double sampler 1142 receives the ramp signals generated by the ramp signal generator 1148, compares them with each other, and outputs a comparison result.

[0015] The analog-to-digital converter 1144 converts an analog signal corresponding to the level received from the correlated double sampler 1142 into a digital signal. The buffer 1146 latches the digital signal, and the latched signals are sequentially output to the outside of the image sensor 1100 and transferred to an image processor (not shown).

[0016] FIG. 2 is a block diagram illustrating a configuration of an image sensor 2000 according to an example embodiment.

[0017] 2, the image sensor 2000 includes a pixel unit 2200 and a peripheral circuit unit. The pixel unit 2200 is formed by arranging a plurality of unit pixels 2100, each including a photoelectric conversion layer, on a substrate 2010 in a two-dimensional array in a regular manner (e.g., at regular intervals).

[0018] The peripheral circuit section is disposed around the pixel section 2200, and includes a vertical drive circuit 2400, a column signal processing circuit 2500, a horizontal drive circuit 2600, an output circuit 2700, a control circuit 2800, an input / output terminal 2900, and the like.

[0019] The control circuit 2800 controls the vertical drive circuit 2400, the column signal processing circuit 2500, the horizontal drive circuit 2600, etc. For example, the control circuit 2800 generates clock signals and control signals used for the operation of the vertical drive circuit 2400, the column signal processing circuit 2500, the horizontal drive circuit 2600, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. The control circuit 2800 also inputs the clock signals and control signals to the vertical drive circuit 2400, the column signal processing circuit 2500, the horizontal drive circuit 2600, etc.

[0020] The vertical driving circuit 2400 is, for example, configured with a shift register, and selects pixel driving wiring, and supplies a pulse for driving the unit pixel to the selected pixel driving wiring, thereby driving the unit pixel in a row unit. For example, the vertical driving circuit 2400 sequentially selects and scans pulses in the vertical direction in a row unit to each unit pixel 2100 of the pixel section 2200. In addition, the vertical driving circuit 2400 supplies pixel signals based on charges generated in the photoelectric conversion layer of each unit pixel 2100 to the column signal processing circuit 2500 via the vertical signal line 2320.

[0021] The column signal processing circuit 2500 is arranged for each column of unit pixels 2100, and performs signal processing such as noise removal for each unit pixel column on signals output from one row of unit pixels 2100. For example, the column signal processing circuit 2500 performs signal processing such as CDS (Crrelated-Double Sampling) for removing noise specific to the unit pixels 2100, signal amplification, AD conversion, etc. A horizontal selection switch (not shown) is provided at the output end of the column signal processing circuit 2500.

[0022] The horizontal drive circuit 2600 is composed of, for example, a shift register, and sequentially outputs horizontal scanning pulses to sequentially select each of the column signal processing circuits 2500 and output each pixel signal of the column signal processing circuit 2500 to the horizontal signal line 2340.

[0023] The output circuit 2700 performs signal processing on signals sequentially supplied from each of the column signal processing circuits 2500 via the horizontal signal line 2340, and outputs the processed signals. For example, the output circuit 2700 may perform only buffering, or may perform black level adjustment, column non-uniformity correction, various digital signal processing, etc. On the other hand, the input / output terminal 2900 is capable of exchanging signals with the outside (for example, transmitting and / or receiving signals).

[0024] FIG. 3 is a readout circuit diagram of an image sensor according to an example embodiment.

[0025] 3, a plurality of pixels PX are arranged in a matrix (e.g., columns and rows), and each of the plurality of pixels PX includes a transmission transistor TX and a logic transistor. Here, the logic transistor includes a reset transistor RX, a selection transistor SX, and a source follower transistor (or drive transistor) SFX. The reset transistor RX includes a reset gate RG, the selection transistor SX includes a selection gate SEL, the source follower transistor SFX includes a source follower gate SF, and the transmission transistor TX includes a transmission gate TG.

[0026] Each of the pixels PX further includes a photoelectric conversion region PD and a floating diffusion region FD. The photoelectric conversion region PD generates and accumulates photocharges in proportion to the amount of light incident from the outside, and may be a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof.

[0027] The transmission gate TG transmits the charge generated in the photoelectric conversion region PD to the floating diffusion region FD. The floating diffusion region FD receives, accumulates, and stores the charge generated in the photoelectric conversion region PD. The source follower gate SF of the source follower transistor SFX is connected to the floating diffusion region FD, and the source follower transistor SFX is controlled by the amount of photocharge accumulated in the floating diffusion region FD.

[0028] The reset transistor RX periodically resets the charge stored in the floating diffusion region FD. The drain electrode of the reset transistor RX is connected to the floating diffusion region FD, and the source electrode of the reset transistor RX is connected to the power supply voltage V DD When the reset transistor RX is turned on, the power supply voltage V DD is transferred to the floating diffusion region FD. When the reset transistor RX is turned on, the charge stored in the floating diffusion region FD is discharged and the floating diffusion region FD is reset.

[0029] The source follower transistor SFX is connected to a current source (not shown) located outside the pixels PX and functions as a source follower buffer amplifier to amplify the potential change in the floating diffusion region FD and output it to the output line V OUT Output to.

[0030] The selection transistor SX selects a number of pixels PX by row, and when the selection transistor SX is turned on, the output voltage generated by the source follower transistor SFX is applied to the output line V OUT is transmitted to.

[0031] Fig. 4 is a layout diagram showing an image sensor 100 according to an example embodiment. Fig. 5 is a cross-sectional view taken along line A1-A1' in Fig. 4. Fig. 6 is a plan view at a first vertical level LV1 in Fig. 5, and Fig. 7 is a plan view at a second vertical level LV2 in Fig. 5.

[0032] 4 and 5, the image sensor 100 includes a semiconductor substrate 110 including a plurality of pixels PX.

[0033] The semiconductor substrate 110 includes a first surface 110F1 and a second surface 110F2 that are opposite to each other. In an exemplary embodiment, the semiconductor substrate 110 includes a P-type semiconductor substrate. For example, the semiconductor substrate 110 includes a P-type silicon substrate. In an exemplary embodiment, the semiconductor substrate 110 includes a P-type bulk substrate and a P-type or N-type epi layer grown thereon. In another embodiment, the semiconductor substrate 110 includes an N-type bulk substrate and a P-type or N-type epi layer grown thereon.

[0034] A plurality of pixels PX are arranged in a matrix in the semiconductor substrate 110, and a plurality of photoelectric conversion regions PD are arranged in each of the plurality of pixels PX. The photoelectric conversion region PD is a region doped with N-type impurities. For example, the photoelectric conversion region PD has an impurity concentration difference between the upper and lower portions and has a potential gradient. Alternatively, the photoelectric conversion region PD may be formed in a form in which a plurality of impurity regions are stacked vertically. A P-well region (not shown) is arranged in a partial region adjacent to the first surface 110F1 of the semiconductor substrate 110. The P-well region is arranged adjacent to the photoelectric conversion region PD and is a region doped with P-type impurities.

[0035] An isolation film 115 defining an active region ACT is formed on the first surface 110F1 of the semiconductor substrate 110. The isolation film 115 is disposed in an isolation trench 115T formed to a predetermined depth in the first surface 110F1 of the semiconductor substrate 110. The isolation film 115 includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. An interface insulating layer 115I is further disposed on an inner wall of the isolation trench 115T, and the interface insulating layer 115I is conformally interposed between the semiconductor substrate 110 and the isolation film 115.

[0036] The transistors constituting the pixel circuit PXT are disposed on the active region ACT. For example, the active region ACT is a part of the semiconductor substrate 110 on which the transmission gate TG, the source follower gate SF, the selection gate SEL, and the reset gate RG are disposed. A floating diffusion region FD is disposed within a part of the active region ACT, for example, within a part of the active region ACT adjacent to the transmission gate TG.

[0037] In an exemplary embodiment, the transmission gate TG constitutes a transmission transistor TX (see FIG. 3), which is configured to transmit the charge generated in the photoelectric conversion region PD to the floating diffusion region FD. The reset gate RG constitutes a reset transistor RX (see FIG. 3), which is configured to periodically reset the charge stored in the floating diffusion region FD. The source follower gate SF constitutes a source follower transistor SFX (see FIG. 3), which acts as a source follower buffer amplifier and is configured to buffer a signal due to the charge stored in the floating diffusion region. The selection gate SEL constitutes a selection transistor SX (see FIG. 3), which performs switching and addressing functions to select the pixel PX.

[0038] The transmission gate TG, the reset gate RG, the source follower gate SF, and the select gate SG each include a gate electrode 120. For example, the gate electrode 120 is disposed in a buried gate trench 120T or on the first surface 110F1 of the semiconductor substrate 110.

[0039] In an exemplary embodiment, the gate electrode 120 includes at least one of doped polysilicon, a metal, a metal silicide, a metal nitride, or a metal-containing film. A gate insulating layer 122 is disposed between the gate electrode 120 and the first surface 110F1 of the semiconductor substrate 110 and on an inner wall of the buried gate trench 120T. A gate spacer 124 is disposed on a sidewall of the gate electrode 120.

[0040] The floating diffusion region FD is disposed within the semiconductor substrate 110 on one side of the gate electrode 120 (e.g., the transmission gate TG). In an exemplary embodiment, the floating diffusion region FD is a region doped with a first impurity, for example, the first impurity is an N-type impurity. In some examples, the first impurity includes phosphorus or arsenic.

[0041] An etch stop layer 130 is disposed on the first surface 110F1 of the semiconductor substrate 110 to cover the gate electrode 120. The etch stop layer 130 conformally covers an upper surface of the gate electrode 120 and an upper surface and a sidewall of the gate spacer 124, and is disposed on an upper surface of the element isolation layer 115. The etch stop layer 130 includes silicon nitride or silicon oxynitride and is formed of a single layer or a double layer.

[0042] A buried insulating film 132 is disposed on the etch stop film 130. The buried insulating film 132 is disposed high enough to completely cover the gate electrode 120 on the etch stop film 130, and the top surface of the buried insulating film 132 has a flat profile. In an exemplary embodiment, the buried insulating film 132 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-k dielectric material.

[0043] A pixel separation structure 140 is disposed in at least a portion of the semiconductor substrate 110, and a plurality of pixels PX are defined by the pixel separation structure 140. The pixel separation structure 140 is disposed between one of the plurality of photoelectric conversion regions PD and an adjacent photoelectric conversion region PD. One photoelectric conversion region PD and another adjacent photoelectric conversion region PD are physically and electrically separated by the pixel separation structure 140. The pixel separation structure 140 is disposed between each of the plurality of photoelectric conversion regions PD arranged in a matrix, and has a lattice or mesh shape in a plan view.

[0044] The pixel isolation structure 140 is formed within a pixel isolation trench 140T. The pixel isolation trench 140T penetrates the semiconductor substrate 110 from the first surface 110F1 to the second surface 110F2 of the semiconductor substrate 110, and extends in the vertical direction Z beyond the first surface 110F1 of the semiconductor substrate 110 and penetrates the buried insulating film 132.

[0045] The pixel isolation trench 140T includes a first portion P1 penetrating the semiconductor substrate 110 from the first surface 110F1 to the second surface 110F2 of the semiconductor substrate 110, and a second portion P2 penetrating the buried insulating film 132 and disposed at a higher vertical level (along the Z direction) than the first portion P1. Here, being disposed at a higher vertical level indicates being disposed farther from the second surface 110F2 of the semiconductor substrate 110. For example, the second portion P2 of the pixel isolation trench 140T is disposed at a higher vertical level than the first surface 110F1 of the semiconductor substrate 110, and the first portion P1 of the pixel isolation trench 140T is disposed at a vertical level equal to or lower than the first surface 110F1 of the semiconductor substrate 110 and higher than the second surface 110F2 of the semiconductor substrate 110.

[0046] In an illustrative embodiment, a gate electrode 120 is formed on a first surface 110F1 of a semiconductor substrate 110, an etch stop layer 130 and a buried insulating layer 132 are formed to cover an upper surface of the gate electrode 120, and then a portion of the buried insulating layer 132 and a portion of the semiconductor substrate 110 are removed to form a pixel isolation trench 140T. Thus, a first portion P1 and a second portion P2 of the pixel isolation trench 140 are continuously connected to each other and have sidewalls that are aligned with each other.

[0047] In the exemplary embodiment, the pixel isolation structure 140 includes an insulating liner 142 , a conductive layer 144 , a barrier conductive layer 146 , and a pixel isolation insulating layer 148 .

[0048] The insulating liner 142 is disposed on the inner wall of the pixel isolation trench 140T. For example, the insulating liner 142 is disposed on the entire inner wall of the first portion P1 and the second portion P2 of the pixel isolation trench 140T. The insulating liner 142 extends from the second side 110F2 of the semiconductor substrate 110 to the first side 110F1 and beyond the first side 110F1 to the upper side of the buried insulating film 132. The insulating liner 142 extends such that a portion of the insulating liner 142 is disposed at the same vertical level as the upper surface of the buried insulating film 132. In some embodiments, the insulating liner 142 includes an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like. In some embodiments, the insulating liner 142 includes a metal oxide such as hafnium oxide, aluminum oxide, or tantalum oxide.

[0049] The conductive layer 144 is disposed in the first portion P1 of the pixel isolation trench 140T and extends in the vertical direction Z. In an exemplary embodiment, the conductive layer 144 includes a reflective metal material. The conductive layer 144 includes at least one of aluminum (Al), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), platinum (Pt), gold (Au), chromium (Cr), titanium (Ti), nickel (Ni), molybdenum (Mo), iron (Fe), magnesium (Mg), iridium (Ir), palladium (PD), and ruthenium (Ru). However, the material constituting the conductive layer 144 is not limited to the above-mentioned metal types, and the conductive layer 144 may include other metal materials not listed here.

[0050] In an exemplary embodiment, the conductive layer 144 has a top surface that is disposed at a level lower than the bottom surface of the element isolation film 115. The conductive layer 144 includes a reflective metal material, and therefore reflects light incident at an oblique angle toward the pixel isolation structure 140 into the pixel PX.

[0051] The barrier conductive layer 146 is disposed in the first portion P1 of the pixel isolation trench 140T and extends in the vertical direction Z. The barrier conductive layer 146 is interposed between the conductive layer 144 and the insulating liner 142 such that the conductive layer 144 is not in direct contact with the insulating liner 142. In an exemplary embodiment, the barrier conductive layer 146 includes at least one of titanium, titanium nitride, titanium aluminum, titanium silicon, cobalt, and cobalt silicon.

[0052] A pixel isolation insulating layer 148 is disposed on the conductive layer 144 and the barrier conductive layer 146 in the pixel isolation trench 140T. For example, the pixel isolation insulating layer 148 is disposed in the second portion P2 and above the first portion P1 of the pixel isolation trench 140T. The pixel isolation insulating layer 148 is covered on both side walls by the insulating liner 142.

[0053] In an exemplary embodiment, the pixel isolation insulating layer 148 has a top surface that is disposed at the same level as a top surface of the buried insulating film 132, with an insulating liner 142 interposed between the pixel isolation insulating layer 148 and the buried insulating film 132. A bottom surface of the pixel isolation insulating layer 148 is disposed at a lower level than a bottom surface of the device isolation film 115. In an exemplary embodiment, the pixel isolation insulating layer 148 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-k dielectric material.

[0054] In an illustrative embodiment, the pixel isolation structure 140 is disposed within the first portion P1 and the second portion P2 of the pixel isolation trench 140T, such that the lower side of the pixel isolation structure 140 is disposed to penetrate the interior of the semiconductor substrate 110 and the upper side of the pixel isolation structure 140 is disposed to penetrate the buried insulating film 132.

[0055] For example, Fig. 6 illustrates a plan view of the image sensor 100 at a first vertical level LV1 that is lower than the first surface 110F1 and higher than the second surface 110F2 of the semiconductor substrate 110. As illustrated in Fig. 6, the underside of the pixel isolation structure 140 (e.g., the insulating liner 142, the conductive layer 144, and the barrier conductive layer 146 of the pixel isolation structure 140) disposed in the first portion P1 of the pixel isolation trench 140T is disposed to planarly surround the multiple pixels PX of the semiconductor substrate 110. Also, Fig. 7 illustrates a plan view of the image sensor 100 at a second vertical level LV2 that is higher than the first surface 110F1 of the semiconductor substrate 110. As shown in FIG. 7, the upper side of the pixel isolation structure 140 (e.g., the insulating liner 142 and the pixel isolation insulating layer 148 of the pixel isolation structure 140) disposed in the second portion P2 of the pixel isolation trench 140T is arranged to surround in a planar manner the buried insulating film 132 at a position corresponding to each pixel PX.

[0056] 5, an upper side of the sidewall of the pixel isolation structure 140 contacts the sidewall of the buried insulating layer 132 and is covered by the buried insulating layer 132. A portion of the sidewall of the pixel isolation structure 140 contacts the device isolation layer 115 and the etch stop layer 130. In an exemplary embodiment, the etch stop layer 130 extends over the upper surface of the semiconductor substrate 110 and includes an end 130CE at a point where the etch stop layer 130 meets the second portion P2 of the pixel trench 140T. For example, the insulating liner 142 is disposed to contact the sidewall 115S of the device isolation layer 115 and contact the end 130CE of the etch stop layer 130.

[0057] In addition, an upper surface of the pixel isolation structure 140 is disposed at a level higher than the first surface 110F1 of the semiconductor substrate 110, and is disposed at the same level as an upper surface of the buried insulating film 132. A sidewall of the pixel isolation structure 140 contacts an end 130CE of the element isolation film 130, and the pixel isolation structure 140 is disposed at a position not vertically overlapping with the element isolation film 130.

[0058] In an exemplary embodiment, the insulating liner 142 is disposed in the first portion P1 and the second portion P2 of the pixel isolation trench 140T, such that a portion of the insulating liner 142 (e.g., a portion of the insulating liner 142 disposed in the second portion P2 of the pixel isolation trench 140T) is interposed between the buried insulating film 132 and the pixel isolation insulating layer 148, another portion of the insulating liner 142 (e.g., a portion of the insulating liner 142 disposed in the second portion P2 of the pixel isolation trench 140T) is interposed between the element isolation film 115 and the pixel isolation insulating layer 148, another portion of the insulating liner 142 (e.g., a portion of the insulating liner 142 disposed in the first portion P1 of the pixel isolation trench 140T) is interposed between the element isolation film 115 and the pixel isolation insulating layer 148, and yet another portion of the insulating liner 142 (e.g., a portion of the insulating liner 142 disposed in the first portion P1 of the pixel isolation trench 140T) is interposed between the semiconductor substrate 110 and the barrier conductive layer 146.

[0059] In an illustrative embodiment, the semiconductor substrate 110 has a first height h1 in the vertical direction Z. The first height h1 corresponds to the distance along the vertical direction Z from the first surface 110F1 to the second surface 110F2 of the semiconductor substrate 110. The pixel separating structure 140 has a second height h2 that is higher than the first height h1 in the vertical direction Z. In some examples, the second height h2 is 105% to 200% of the first height h1, but the ratio of the second height h2 to the first height h1 may vary depending on the dimensions of the pixels PX, the layout of the pixels PX, etc.

[0060] A barrier impurity region 110D is disposed in an internal region of the semiconductor substrate 110 disposed adjacent to the pixel isolation trench 140T. In each pixel PX, the barrier impurity region 110D is surrounded in a planar manner by the pixel isolation structure 140. The barrier impurity region 110D is a region doped with a P-type impurity disposed inside the semiconductor substrate 110, and the P-type impurity includes boron (B).

[0061] The contact 150 is disposed in a contact hole 150H penetrating the buried insulating film 132, and is electrically connected to the semiconductor substrate 110 and the gate electrode 120. The contact 150 includes a barrier layer 150M and a buried conductive layer 150F, where the barrier layer 150M is disposed on the inner wall of the contact hole 150H, and the buried conductive layer 150F fills the inside of the contact hole 150H. For example, the barrier layer 150M is disposed on the sidewall and bottom surface of the buried conductive layer 150F.

[0062] In an exemplary embodiment, buried conductive layer 150F includes at least one of doped or undoped polysilicon, a metal, a metal silicide, a metal nitride, or a metal-containing film, such as tungsten, aluminum, copper, tungsten silicide, titanium silicide, tungsten nitride, titanium nitride, doped polysilicon, etc. Barrier layer 150M includes titanium nitride, tungsten nitride, tungsten silicide, titanium silicide, etc.

[0063] A wiring layer 152 electrically connected to the contact 150 is disposed on the buried insulating film 132 , and an interlayer insulating film 154 covering the wiring layer 152 is disposed on the buried insulating film 132 .

[0064] A backside insulating layer 162 is disposed on the second side 110F2 of the semiconductor substrate 110. In an exemplary embodiment, the backside insulating layer 162 includes a metal oxide, such as hafnium oxide, aluminum oxide, or tantalum oxide. In other embodiments, the backside insulating layer 162 includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material.

[0065] A passivation layer 164 is disposed on the back insulating layer 162, and a color filter 166 and a microlens 168 are disposed on the passivation layer 164.

[0066] In general, a pixel isolation structure is formed in a pixel isolation trench using polysilicon, and a negative bias is applied to the pixel isolation structure to prevent dark current from occurring. However, as the pixel size is reduced, there is a problem in that optical crosstalk occurs in which light passes through the pixel isolation structure and is transmitted or incident on an adjacent pixel.

[0067] According to an exemplary embodiment, the pixel separating structure 140 is disposed to extend in the vertical direction Z so as to penetrate the buried insulating film 132, and the pixel separating structure 140 includes a conductive layer 144 made of a reflective metal material, thereby reducing or preventing optical crosstalk that occurs when light is transmitted or incident on adjacent pixels.

[0068] Fig. 8 is a cross-sectional view showing an image sensor 100A according to an exemplary embodiment. Fig. 9 is a plan view at a second vertical level LV2 of Fig. 8. In Figs. 8 and 9, the same reference numerals as in Figs. 1 to 7 denote the same components.

[0069] 8 and 9, the pixel isolation insulating layer 148 of the pixel isolation structure 140 includes a void 148V therein. The void 148V indicates an empty air space where an insulating material layer constituting the pixel isolation insulating layer 148 is not formed.

[0070] In an exemplary embodiment, the void 148V extends to a relatively large height in the vertical direction Z from a vertical level lower than the first surface 110F1 of the semiconductor substrate 110 to a vertical level higher than the first surface 110F1 of the semiconductor substrate 110. As shown in Fig. 8, the void 148V is disposed at a level lower than the top surface of the buried insulating film 132, and the void 148V is not exposed to the outside of the pixel separating structure 140. In another embodiment, the void 148V is disposed to extend to the same level as the top surface of the buried insulating film 132.

[0071] In an exemplary embodiment, pixel isolation insulating layer 148 is formed using a material that does not have excellent step coverage. During the process of forming pixel isolation insulating layer 148 in second portion P2 of pixel isolation trench 140T, pixel isolation insulating layer 148 does not completely fill second portion P2 of pixel isolation trench 140T, resulting in voids 148V remaining in pixel isolation insulating layer 148. Voids 148V include air spaces, and air has a relatively low dielectric constant. The inclusion of voids 148V in pixel isolation insulating layer 148 improves the conversion gain characteristics of image sensor 100A.

[0072] 10 is a cross-sectional view showing an image sensor 100B according to an exemplary embodiment, in which the same reference numerals as those in FIGS.

[0073] 10, upper surfaces of the conductive layer 144 and the barrier conductive layer 146 of the pixel isolation structure 140 are disposed at a level higher than a bottom surface of the device isolation film 115 and lower than an upper surface of the device isolation film 115. The pixel isolation insulating layer 148 of the pixel isolation structure 140 is formed on the conductive layer 144 and the barrier conductive layer 146, and a bottom surface of the pixel isolation insulating layer 148 is disposed at a level lower than an upper surface of the device isolation film 115 or a level lower than a first surface 110F1 of the semiconductor substrate 110.

[0074] Fig. 11 is a cross-sectional view showing an image sensor 100C according to an exemplary embodiment. Fig. 12 is a plan view at a second vertical level LV2 of Fig. 11. In Figs. 11 and 12, the same reference numerals as in Figs. 1 to 10 denote the same components.

[0075] 11 and 12, upper surfaces of the conductive layer 144 and the barrier conductive layer 146 of the pixel isolation structure 140 are disposed at a level higher than an upper surface of the element isolation film 115 and lower than an upper surface of the buried insulating film 132. For example, the conductive layer 144 and the barrier conductive layer 146 are disposed in a first portion P1 and a part of a second portion P2 of the pixel isolation trench 140T. A part of the barrier conductive layer 146 and a part of the insulating liner 142 are interposed between the conductive layer 144 and the buried insulating film 132 at a vertical level higher than the first surface 110F1 of the semiconductor substrate 110.

[0076] For example, as shown in FIG. 12, which illustrates a plan view at a second vertical level LV2 higher than the first surface 110F1 of the semiconductor substrate 110, the upper side of the pixel isolation structure 140 (e.g., the insulating liner 142, the conductive layer 144, and the barrier conductive layer 146 of the pixel isolation structure 140) disposed within the second portion P2 of the pixel isolation trench 140T is arranged to surround, in a planar manner, the embedded insulating film 132 at a position corresponding to each pixel PX.

[0077] In some embodiments, the pixel isolation insulating layer 148 is omitted, and the conductive layer 144 and the barrier conductive layer 146 are disposed within the entire height of the pixel isolation trench 140T, i.e., the entire height of the first portion P1 and the second portion P2. In such a case, the top surfaces of the conductive layer 144 and the barrier conductive layer 146 are disposed at the same level as the top surface of the buried insulating layer 132.

[0078] According to an illustrative embodiment, a conductive layer 144 including a reflective metal material is disposed extending in a vertical direction Z on the first surface 110F1 of the semiconductor substrate 110, so that the pixel separating structure 140 reflects light incident at an oblique angle from one pixel PX toward an adjacent pixel PX, thereby reducing or preventing optical crosstalk in the image sensor 100C.

[0079] 13 is a cross-sectional view showing an image sensor 100D according to an exemplary embodiment. In FIG. 13, the same reference numerals as in FIGS. 1 to 12 denote the same components.

[0080] 13, the contact 150 is disposed in a contact hole 150H penetrating the buried insulating film 132, and is electrically connected to the semiconductor substrate 110 and the gate electrode 120. The contact 150 includes a barrier layer 150M and a buried conductive layer 150F, where the barrier layer 150M includes the same material as the barrier conductive layer 146 of the pixel separating structure 140, and the buried conductive layer 150F includes the same material as the conductive layer 144 of the pixel separating structure 140.

[0081] In an exemplary embodiment, the buried conductive layer 150F and the conductive layer 144 include a reflective metallic material. For example, the buried conductive layer 150F and the conductive layer 144 include at least one of aluminum (Al), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), platinum (Pt), gold (Au), chromium (Cr), titanium (Ti), nickel (Ni), molybdenum (Mo), iron (Fe), magnesium (Mg), iridium (Ir), palladium (PD), and ruthenium (Ru). The barrier layer 150M and the barrier conductive layer 146 include at least one of titanium, titanium nitride, titanium aluminum, titanium silicon, cobalt, and cobalt silicon.

[0082] In an exemplary embodiment, after forming the gate electrode 120 on the semiconductor substrate 110 and forming the buried insulating film 132 covering the gate electrode 120, the buried insulating film 132, the pixel isolation trench 140T penetrating the semiconductor substrate 110, and the contact hole 150H penetrating the buried insulating film 132 are formed. Thereafter, a process of forming a barrier layer 150M in the contact hole 150H and a process of forming a barrier conductive layer 146 in the pixel isolation trench 140T are performed in the same process step, and a process of forming a buried conductive layer 150F in the contact hole 150H and a process of forming a conductive layer 144 in the pixel isolation trench 140T are performed by the same process in the same process step.

[0083] 14 is a cross-sectional view showing an image sensor 100E according to an exemplary embodiment. In FIG. 14, the same reference numerals as in FIGS. 1 to 13 denote the same components.

[0084] 14, the pixel isolation structure 140 further includes a buried conductive layer 149 disposed on the conductive layer 144. For example, the conductive layer 144 is formed relatively thin so as not to completely fill the pixel isolation trench 140T, and the buried conductive layer 149 is formed on the conductive layer 144. In an exemplary embodiment, the conductive layer 144 includes a reflective metal material, and the buried conductive layer 149 includes silicon germanium (SiGe), polysilicon, a metal, a metal nitride, a metal silicide, or the like.

[0085] 15 is a cross-sectional view showing an image sensor 100F according to an exemplary embodiment. In FIG. 15, the same reference numerals as in FIGS. 1 to 14 denote the same components.

[0086] Referring to FIG. 15, the pixel isolation trench 140T has sloped sidewalls such that the width of the second portion P2 along the horizontal direction (e.g., the X direction or Y direction) is wider than the width of the first portion P1 along the horizontal direction, and the horizontal width of the pixel isolation trench 140T at the same level as the top surface of the buried insulating film 132 is wider than the horizontal width of the pixel isolation trench 140T at the same level as the second surface 110F2 of the semiconductor substrate 110.

[0087] In the above exemplary embodiment described with reference to FIGS. 4 to 15, one pixel PX is disposed apart from other adjacent pixels PX, and each pixel PX is surrounded by the pixel separating structure 140 in a planar manner. However, in other embodiments, the pixel separating structure 140 may not be disposed in at least a part of a region between at least one pixel PX among the plurality of pixels PX and another pixel PX adjacent thereto. For example, in a structure in which two pixels PX share a floating diffusion region FD, a separating region or a cut region of the pixel separating structure 140 may be disposed between two adjacent pixels PX. Alternatively, in a structure in which four pixels PX share a floating diffusion region FD, a separating region or a cut region of the pixel separating structure 140 may be disposed between four adjacent pixels PX arranged in a matrix.

[0088] In the above-described exemplary embodiments described with reference to Figures 4 to 15, at least two gate electrodes 120 are disposed spaced apart on the first surface 110F1 of the semiconductor substrate 110 in one pixel PX. However, in other embodiments, only the transmission gate TG is disposed on the first surface 110F1 of the semiconductor substrate 110, and the gate electrodes 120 (e.g., the selection gate SEL, the reset gate RG, and the source follower gate RG) constituting the pixel circuit PXT are disposed on an additional semiconductor substrate, and the semiconductor substrate 110 and the additional semiconductor substrate are attached to each other, and the semiconductor substrate 110 and the additional semiconductor substrate are electrically connected to each other by bonding pads and / or through vias between the semiconductor substrate 110 and the additional semiconductor substrate, etc.

[0089] FIG. 16 is a cross-sectional view illustrating an image sensor 100G according to an example embodiment.

[0090] 16, in the image sensor 100G, the buried insulating film 132, the insulating liner 142, and the pixel isolation insulating layer 148 are made of the same material, so that the boundary between the buried insulating film 132 and the insulating liner 142 and the boundary between the insulating liner 142 and the pixel isolation insulating layer 148 are not discernible to the naked eye. In an exemplary embodiment, the etch stop layer 130 extends on the upper surface of the semiconductor substrate 110 and includes an end 130CE at a point where it meets the second portion P2 of the pixel trench 140T. The end 130CE of the etch stop layer 130 extends in a first horizontal direction X and a second horizontal direction Y to correspond to the planar shape of the pixel trench 140T.

[0091] An end 130CE of the etch stop layer 130 is aligned with a sidewall of the device isolation layer 115. For example, the sidewall of the device isolation layer 115 indicates a surface of the device isolation layer 115 connected to the pixel trench 140T, and the end 130CE of the etch stop layer 130 is aligned with the sidewall of the device isolation layer 115 in the vertical direction Z.

[0092] In an exemplary embodiment, the buried insulating layer 132, the insulating liner 142, and the pixel isolation insulating layer 148 include an insulating material such as silicon oxide, and in such a case, the spaces on the upper surfaces of the conductive layer 144 and the barrier conductive layer 146 disposed in the first portion P1 of the pixel trench 140T are all filled with an insulating material such as silicon oxide.

[0093] In an illustrative embodiment, in the process of forming the pixel trench 140T, a portion of the etch stop film 130 is removed to form an end 130CE of the etch stop film 130, so that the conductive layer 144 and the barrier conductive layer 146 are positioned so as not to vertically overlap the etch stop film 130.

[0094] According to the above-described exemplary embodiment, the image sensor includes a pixel separating structure extending from a first surface to a second surface of the semiconductor substrate and penetrating the buried insulating film, the pixel separating structure including a conductive layer including a reflective metal material, the conductive layer reflecting light incident toward the pixel separating structure to the inside of the pixel, thereby reducing or preventing optical cross-talk in the image sensor that occurs due to a reduction in pixel size.

[0095] As described above, the drawings and the specification disclose exemplary embodiments. Although specific terms are used in the present specification to describe the embodiments, these terms are used only for the purpose of describing the technical idea of ​​the present invention, and are not used to limit the meaning or the scope of the present invention. Therefore, a person having ordinary knowledge in the art will understand that various modifications and equivalent other embodiments are possible. [Explanation of symbols]

[0096] 1100, 2000 image sensor 1110 pixel array 1120 Row Driver 1130 Controller 1140 Pixel signal processing unit 1142 Correlated Double Sampler (CDS) 1144 Analog-to-Digital Converter (ADC) 1146 Buffer 1148 Ramp Signal Generator 2010 Substrate 2100 unit pixels 2200 pixel section 2320 Vertical signal line 2340 Horizontal signal line 2400 Vertical drive circuit 2500 Column signal processing circuit 2600 Horizontal drive circuit 2700 Output circuit 2800 Control Circuit 2900 Input / output terminal

Claims

1. a semiconductor substrate including a first surface and a second surface opposite to the first surface, the semiconductor substrate including a photoelectric conversion region therein; a transmission gate disposed on the first surface of the semiconductor substrate; a buried insulating film disposed on the first surface of the semiconductor substrate and covering the transfer gate; a pixel isolation structure disposed in a pixel isolation trench extending from the first surface toward the second surface of the semiconductor substrate and penetrating the buried insulating film, the pixel isolation structure defining a plurality of pixels in the semiconductor substrate, a portion of the pixel isolation structure being covered by the buried insulating film.

2. The pixel separating structure includes: an insulating liner disposed on an inner wall of the pixel isolation trench; a conductive layer disposed within the pixel isolation trench on the insulating liner; a pixel isolation insulating layer disposed on the inner wall of the pixel isolation trench and disposed on the conductive layer; 2. The image sensor of claim 1, further comprising: a barrier conductive layer disposed between said conductive layer and said pixel isolation insulating layer.

3. the pixel isolation trench includes a first portion penetrating the semiconductor substrate and a second portion penetrating the buried insulating film, the insulating liner being disposed on an inner wall of the first portion and an inner wall of the second portion of the pixel isolation trench; a first portion of the insulating liner disposed within the first portion of the pixel isolation trench contacting the barrier conductive layer; 3. The image sensor of claim 2, wherein the second portion of the insulating liner disposed within the second portion of the pixel isolation trench contacts the buried insulating film.

4. The image sensor of claim 2 , wherein a top surface of the pixel isolation structure is disposed at the same level as a top surface of the buried insulating film.

5. 3. The image sensor of claim 2, wherein the conductive layer comprises a reflective metallic material.

6. 3. The image sensor of claim 2, wherein the conductive layer comprises at least one of aluminum, copper, silver, cobalt, tungsten, platinum, gold, chromium, titanium, nickel, molybdenum, iron, magnesium, iridium, palladium, and ruthenium.

7. an isolation layer disposed within an isolation trench defining an active region within the semiconductor substrate; an etch stop layer disposed between the first surface of the semiconductor substrate and the buried insulating layer, between the transfer gate and the buried insulating layer, and between an upper surface of the device isolation layer and the buried insulating layer, 3. The image sensor of claim 2, wherein a sidewall of the pixel isolation structure contacts the device isolation layer and the etch stop layer.

8. The image sensor according to claim 7 , wherein an upper surface of the conductive layer is disposed at a level lower than a bottom surface of the device isolation film.

9. 8. The image sensor according to claim 7, wherein a top surface of the conductive layer is disposed at a level higher than a bottom surface of the device isolation film and lower than a top surface of the device isolation film.

10. The image sensor according to claim 7 , wherein an upper surface of the conductive layer is disposed at a level higher than the upper surface of the element isolation film.

11. The image sensor of claim 2 , wherein the pixel isolation insulating layer includes a void therein.

12. the semiconductor substrate has a first height in a vertical direction; 2. The image sensor of claim 1, wherein the pixel separating structures have a second height in the vertical direction that is greater than the first height.

13. a semiconductor substrate including a first surface and a second surface opposite to the first surface, the semiconductor substrate including a photoelectric conversion region therein; a transmission gate disposed on the first surface of the semiconductor substrate; an etch stop layer disposed on the first surface of the semiconductor substrate and covering the transfer gate; a pixel isolation structure disposed in a pixel isolation trench extending from the first surface toward the second surface of the semiconductor substrate, the pixel isolation structure including a conductive layer including a reflective metallic material; an edge of the etch stop layer is disposed on the conductive layer, and the pixel isolation structure and the etch stop layer do not vertically overlap.

14. The pixel separating structure includes: a barrier conductive layer disposed on a sidewall of the conductive layer; the pixel isolation insulating layer disposed within a second portion of the pixel isolation trench, the second portion being disposed at a higher vertical level than the first portion of the pixel isolation trench; 14. The image sensor of claim 13, further comprising: an insulating liner extending in a vertical direction perpendicular to the first surface of the semiconductor substrate on an inner wall of the pixel isolation trench and disposed between the semiconductor substrate and the barrier conductive layer.

15. a buried insulating film disposed on the etch stop film and covering the transfer gate; an isolation layer disposed in an isolation trench defining an active region in the semiconductor substrate; 15. The image sensor of claim 14, wherein the pixel isolation trench extends in the vertical direction through the buried insulating layer.

16. the edge of the etch stop layer is aligned with a sidewall of the isolation layer; 16. The image sensor of claim 15, wherein the insulating liner contacts the sidewall of the isolation layer and the edge of the etch stop layer.

17. the insulating liner is disposed on an entire inner wall of the pixel isolation trench; The image sensor of claim 16 , wherein a top surface of the conductive layer is disposed at a level lower than a bottom surface of the device isolation film.

18. 14. The image sensor of claim 13, wherein the conductive layer comprises at least one of aluminum, copper, silver, cobalt, tungsten, platinum, gold, chromium, titanium, nickel, molybdenum, iron, magnesium, iridium, palladium, and ruthenium.

19. a semiconductor substrate including a first surface and a second surface opposite to the first surface, the semiconductor substrate including a photoelectric conversion region therein; a transmission gate disposed on the first surface of the semiconductor substrate; a pixel isolation structure disposed in a pixel isolation trench extending from the first side to the second side of the semiconductor substrate; The pixel separating structure includes: a conductive layer disposed in the pixel isolation trench and extending in a vertical direction perpendicular to the first surface of the semiconductor substrate; a barrier conductive layer disposed on sidewalls of the conductive layer within the pixel isolation trench; a pixel isolation insulating layer disposed within the pixel isolation trench over the conductive layer and the barrier conductive layer; an insulating liner extending in the vertical direction on an inner wall of the pixel isolation trench and covering a sidewall of the pixel isolation insulating layer and a sidewall of the barrier conductive layer; an upper surface of the pixel isolation insulating layer being disposed at a higher level than the first surface of the semiconductor substrate.

20. an isolation film disposed within an isolation trench defining an active region within the semiconductor substrate; an etch stop layer disposed on the first surface of the semiconductor substrate and the device isolation layer, the etch stop layer covering an upper surface of the transfer gate; a buried insulating film disposed on an upper surface of the etch stop film, 20. The image sensor of claim 19, wherein the pixel isolation trench extends in the vertical direction through the buried insulating layer, and a top surface of the pixel isolation structure is disposed at the same level as a top surface of the buried insulating layer.

Images