Precision tuning of page or word of non-volatile memory cell and associated high voltage circuit for analog neural memory array in artificial neural network

Abstract

To provide a method for executing the tuning with a word or a page of a non-volatile memory cell.SOLUTION: A page- or word-based bidirectional tuning algorithm includes the steps of: erasing a word or a page of a non-volatile memory cell; executing soft programming of the word or the page of the non-volatile memory cell; executing rough programming of the word or the page of the non-volatile memory cell; executing fine programming of the word or the page of the non-volatile memory cell; and identifying given high-speed bits in the word or the page of the non-volatile memory cell and causing the aforementioned bits to be programmed by use of a sequence different from that of normal (non-high-speed and non-low speed) bits.SELECTED DRAWING: Figure 20B

Description

[Technical field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 62 / 993,008, filed March 22, 2020, entitled "Precision Tuning of a Page or Word of Non-Volatile Memory Cells And Associated High Voltage Circuits for an Analog Neural Memory Array in an Artificial Neural Network," and U.S. Patent Application No. 17 / 024,410, filed September 17, 2020, entitled "Precision Tuning of a Page or Word of Non-Volatile Memory Cells And Associated High Voltage Circuits for an Analog Neural Memory Array in an Artificial Neural Network."

[0002] FIELD OF THEINVENTION Numerous embodiments are disclosed for performing fine tuning of pages or words of non-volatile memory cells in an analog neural memory. High voltage circuits and programming sequences used during the fine tuning process are also disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain), and are used to estimate or approximate functions that may depend on multiple inputs and are generally unknown. Artificial neural networks generally contain layers of interconnected "neurons" that exchange messages.

[0004] FIG. 1 shows an artificial neural network, where the circles represent layers of inputs or neurons. The connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the artificial neural network to adapt to the inputs and learn. Typically, an artificial neural network contains multiple layers of inputs. There are typically one or more hidden layers of neurons, and an output layer of neurons that provide the output of the neural network. At each level, the neurons make decisions individually or collectively based on the data they receive from the synapses.

[0005] One of the main challenges in the development of artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In practice, practical artificial neural networks rely on a very large number of synapses, which allows high connectivity between neurons, i.e., a very high degree of parallelization of computation. In principle, such complexity can be achieved by digital supercomputers or dedicated graphic processing unit clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency compared to biological networks, which mainly perform low-precision analog computations and therefore consume much less energy. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses are too bulky given the large number of neurons and synapses.

[0006] Applicant previously disclosed an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application Serial No. 15 / 594,439, published as U.S. Patent Publication 2017 / 0337466, which is incorporated by reference. The non-volatile memory array operates as an analog neuromorphic memory. As used herein, the term neuromorphic refers to a circuit that implements a model of a neural system. The analog neuromorphic memory includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each memory cell including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate disposed above and insulated from a first portion of the channel region, and a non-floating gate disposed above and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply a first plurality of inputs by the stored weight values ​​to generate a first plurality of outputs. An array of memory cells arranged in this manner may be referred to as a vector matrix multiplication (VMM) array.

[0007] We now discuss examples of different non-volatile memory cells that may be used in a VMM. <<Non-volatile memory cells>>

[0008] Various types of known non-volatile memory cells may be used in a VMM array. For example, U.S. Pat. No. 5,029,130 ​​("the '130 patent"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the source region 14. A wordline terminal 22 (typically coupled to a wordline) has a first portion disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion extending upwardly above the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline terminal 24 is coupled to the drain region 16.

[0009] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the wordline terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim tunneling from the floating gate 20 to the wordline terminal 22 through the insulator between them.

[0010] The memory cell 210 is programmed (electrons are applied to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. An electronic current flows from the drain region 16 towards the source region 14 (the source line terminal). The electrons accelerate and become excited (heated) when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0011] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on and current flows through the channel region 18, which is sensed as the erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off and no (or very little) current flows through the channel region 18, which is sensed as the programmed or "0" state.

[0012] Table 1 shows typical voltage ranges that may be applied to the terminals of memory cell 110 to perform read, erase, and program operations. Table 1: Operation of the Flash Memory Cell 210 of FIG. 2 [Table 1] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0013] Figure 3 shows a memory cell 310 similar to memory cell 210 of Figure 2 with the addition of a control gate (CG) terminal 28. The control gate terminal 28 is biased at a high voltage (e.g., 10V) during programming, a low or negative voltage (e.g., 0v / -8V) during erasure, and a low or medium voltage (e.g., 0v / 2.5V) during reading. The other terminals are biased similarly to those of Figure 2.

[0014] FIG. 4 shows a four-gate memory cell 410 comprising a source region 14, a drain region 16, a floating gate 20 above a first portion of the channel region 18, a select gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, i.e., they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0015] Table 2 shows typical voltage ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 2: Operation of Flash Memory Cell 410 of FIG. [Table 2] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0016] Figure 5 shows a memory cell 510 similar to memory cell 410 of Figure 4, except that memory cell 510 does not include an erase gate (EG) terminal. Erasing is accomplished by biasing the substrate 18 to a high voltage and the control gate CG terminal 28 to a low or negative voltage. Alternatively, erasure is accomplished by biasing the word line terminal 22 to a positive voltage and the control gate terminal 28 to a negative voltage. Programming and reading are similar to those of Figure 4.

[0017] Figure 6 shows another type of flash memory cell, a three-gate memory cell 610. Memory cell 610 is identical to memory cell 410 of Figure 4, except that memory cell 610 does not have a separate control gate terminal. Erase and read operations (where erasure occurs through the use of the erase gate terminal) are similar to those of Figure 4, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage must be applied to the source line terminal during a program operation to compensate for the lack of control gate bias.

[0018] Table 3 shows typical voltage ranges that may be applied to the terminals of memory cell 610 to perform read, erase, and program operations. Table 3: Operation of Flash Memory Cell 610 of FIG. [Table 3] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0019] 7 shows another type of flash memory cell, a stacked gate memory cell 710. The memory cell 710 is similar to the memory cell 210 of FIG. 2, except that the floating gate 20 extends over the entire channel region 18, and a control gate terminal 22 (coupled to a word line) extends over the floating gate 20, separated by an insulating layer (not shown). Programming is performed using hot electron injection from the channel 18 into the floating gate 20 in the channel region next to the drain region 16, and erasure is performed using Fowler-Nordheim electron tunneling from the floating gate 20 to the substrate 12. Read operations work in a similar manner as previously described for the memory cell 210.

[0020] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 710 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of Flash Memory Cell 710 of FIG. [Table 4]

[0021] "Read 1" is a read mode in which the cell current is output to a bit line. "Read 2" is a read mode in which the cell current is output to a source line terminal. Optionally, in an array including rows and columns of memory cells 210, 310, 410, 510, 610, or 710, a source line may be coupled to one row of memory cells or to two adjacent rows of memory cells. That is, a source line terminal may be shared by adjacent rows of memory cells.

[0022] 8 shows a twin split gate memory cell 810. The memory cell 810 includes a floating gate (FG) 20 disposed above and insulated from the substrate 12, a control gate 28 (CG) disposed above and insulated from the floating gate 20, an erase gate 30 (EG) disposed adjacent to and insulated from the floating gate 20 and the control gate 28, and disposed above and insulated from the substrate 12, the erase gate 30 (EG) being formed in a T-shape such that the top corner of the control gate CG faces the inner corner of the T-shape erase gate to improve erase efficiency, and a drain region 16 (DR) in the substrate adjacent to the floating gate 20 (with a bit line contact 24 (BL) connected to the drain diffusion region 16 (DR)). The memory cells are formed as a memory cell pair (A on the left and B on the right) that share a common erase gate 30. This cell design differs from the memory cells described above with reference to Figures 2-7 at least in that it lacks a source region under the erase gate EG, lacks a select gate (also called a word line), and lacks a channel region in each of the memory cells. Instead, a single continuous channel region 18 extends under both memory cells (i.e., from drain region 16A of one memory cell to drain region 16B of the other memory cell). To read or program one memory cell, the control gate 28 of the other memory cell is raised to a sufficient voltage to activate the underlying channel region portion via voltage coupling to the floating gate 20 between them (e.g., to read or program cell A, the voltage of FGB 20B is raised via voltage coupling from CGB 28B to activate the channel region under FGB 20B). Erasing is performed using Fowler Nordheim electron tunneling from the floating gate 20 to the erase gate 30. Programming is performed using hot electron injection from the channel 18 to the floating gate 20, which is shown in Table 5 as Program 1. Alternatively, programming is performed using Fowler-Nordheim electron tunneling from the erase gate 30 to the floating gate 20, which is shown in Table 5 as Program 2.Alternatively, programming is performed using Fowler-Nordheim electron tunneling from the channel 18 to the floating gate 20, in which case the conditions are similar to program 2, except that the substrate 12 is biased at a low or negative voltage while the erase gate 30 is biased at a low positive voltage.

[0023] Table 5 shows typical voltage ranges that may be applied to the terminals of memory cell 810 to perform read, erase, and program operations. In this table, cell A (having terminals EG, CGA, and BLA) is assumed to be selected for a read, program, or erase operation in the respective row. Table 5: Operation of Flash Memory Cell 810 of FIG. [Table 5]

[0024] In order to utilize a memory array containing one of the non-volatile memory cell types in an artificial neural network as described above, two modifications are made: First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array; Second, a continuous (analog) programming of the memory cells is provided.

[0025] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state, independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage is analog or can at a minimum store one of many discrete values ​​(such as 16 or 64 different values), which allows every cell in the memory array to be very precisely and individually tunable, making the memory array ideal for storage and fine tuning adjustments to the synaptic weights of neural networks.

[0026] The methods and means described herein can be applied to other non-volatile memory technologies such as, without limitation, FINFET split gate flash or stack gate flash memory, NAND flash, 3D flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive random access memory), PCM (phase change memory), MRAM (magnetoresistive memory), FeRAM (ferroelectric memory), OTP (bi-level or multi-level one-time programmable) and CeRAM (strongly correlated electron memory). The methods and means described herein can be applied to volatile memory technologies used in neural networks such as, without limitation, SRAM, DRAM, and other volatile synapse cells. <<Neural network using non-volatile memory cell array>>

[0027] 9 conceptually illustrates a non-limiting example of a neural network utilizing the non-volatile memory array of the present embodiments. This example uses the non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using the non-volatile memory array-based neural network.

[0028] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, each pixel with 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping filters (kernels) of 3x3 pixels, applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels depending on the model). Specifically, the values ​​of the nine pixels in the 3x3 portion of the image (i.e., referred to as filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined and given by the first synapse of CB1 to generate one pixel of the layer of feature map C1. The 3x3 filter is then shifted one pixel to the right in the input layer S0 (i.e., add a column of 3 pixels to the right and drop a column of 3 pixels on the left), so that the 9 pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter scans the entire 32x32 pixel image of input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps of C1, until all feature maps of layer C1 have been calculated.

[0029] In this example, in layer C1, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input with a kernel, and thus each feature map is a two-dimensional array, and thus in this example layer C1 constitutes 16 layers of two-dimensional arrays (note that layers and arrays referred to herein are logical, not necessarily physical, relationships, i.e., arrays are not necessarily oriented in a physical two-dimensional array). Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0030] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions in each feature map. The purpose of the pooling function is to average nearby positions (or a max function can be used), e.g., to reduce edge position dependency, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2 going from layer S1 to layer C2 scans the maps in S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where all neurons in layer C3 connect to all maps in layer S2 through respective synapses in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e. all neurons in layer C3 connect to all neurons in layer S3. The output at S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0031] Each layer of the synapse is implemented using an array or a portion of an array of non-volatile memory cells.

[0032] FIG. 10 is a block diagram of a system that can be used for that purpose. The VMM system 32 includes non-volatile memory cells and is used as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in FIG. 6). Specifically, the VMM system 32 includes a VMM array 33 with non-volatile memory cells arranged in rows and columns, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37 that decode the respective inputs to the non-volatile memory cell array 33. Inputs to the VMM array 33 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the VMM array 33. Alternatively, the bit line decoder 36 can decode the output of the VMM array 33.

[0033] The VMM array 33 serves two purposes. First, it stores the weights used by the VMM system 32. Second, it effectively multiplies the inputs by the weights stored in the VMM array 33 and sums them per output line (source line or bit line) to generate an output, which becomes the input to the next layer or the input to the last layer. By performing multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic and is also power efficient with on-the-fly memory computation. The weights of a filter (kernel) are mapped across one or more bit lines (columns) or one or more rows across a single or multiple VMM arrays 33.

[0034] The outputs of the VMM array 33 are fed to a differential summer (such as a summing operational amplifier or a summing current mirror) 38, which sums the outputs of the VMM array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of both the positive and negative weight inputs to output a single value.

[0035] The summed output values ​​of the differential summer 38 are then fed to an activation function circuit 39 which rectifies the output. The activation function circuit 39 may provide a sigmoid function, a tanh function, a ReLU function, or any other non-linear function. The rectified output values ​​of the activation function circuit 39 become elements of the feature map of the next layer (e.g., C1 in FIG. 9) and are then applied to the next synapse to generate the next feature map layer or the last layer. Thus, in this example, the VMM array 33 constitutes a number of synapses (which receive input from a previous layer of neurons or from an input layer such as an image database), and the summer 38 and the activation function circuit 39 constitute a number of neurons.

[0036] The inputs to the VMM system 32 of FIG. 10 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, digital timing pulses (in which case a pulse-to-analog converter PAC may be required to convert the pulses to appropriate input analog levels) or digital bits (in which case a DAC is provided to convert the digital bits to appropriate input analog levels), and the outputs may be analog levels (e.g., current, voltage, or charge), binary levels, digital pulses, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0037] FIG. 11 is a block diagram illustrating the use of multiple layers of the VMM system 32, labeled in the figure as VMM systems 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 11, an input (denoted Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to the input VMM system 32a. The converted analog input can be a voltage or a current. The first layer input D / A conversion can be done by using a function or a LUT (look-up table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM system 32a. The input conversion can also be done by an analog-to-analog (A / A) converter to convert an external analog input to a mapped analog input to the input VMM system 32a. The input conversion can also be done by a digital-to-digital pulse (D / P) converter to convert an external digital input to a mapped digital pulse(s) to the input VMM system 32a.

[0038] The output generated by the input VMM system 32a is then provided as input to the next VMM system (hidden level 1) 32b, which in turn generates an output that is provided as input to the next VMM system (hidden level 2) 32c, and so on. The various layers of the VMM systems 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each of the VMM systems 32a, 32b, 32c, 32d, and 32e may be a standalone physical system with a corresponding non-volatile memory array, or the multiple VMM systems may utilize different portions of the same physical non-volatile memory array, or the multiple VMM systems may utilize overlapping portions of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d, and 32e may also be time multiplexed to various portions of its array or neurons. The example shown in Figure 11 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example and that the system may instead include more than two hidden layers and more than two fully connected layers. <<VMMアレイ> >

[0039] Figure 12 shows a neuron VMM array 1200 that is particularly suited for the memory cells 310 shown in Figure 3 and is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1200 includes a memory array 1201 of non-volatile memory cells and a reference array 1202 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array can be located at the bottom.

[0040] In the VMM array 1200, control gate lines such as control gate line 1203 run vertically (so that row-wise reference array 1202 is orthogonal to control gate line 1203) and erase gate lines such as erase gate line 1204 run horizontally. Here, inputs to the VMM array 1200 are provided to the control gate lines (CG0, CG1, CG2, CG3) and outputs of the VMM array 1200 appear on the source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current applied to each source line (SL0, SL1, respectively) performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0041] As described herein for neural networks, the non-volatile memory cells of the VMM array 1200 are preferably configured to operate in the sub-threshold region.

[0042] The non-volatile reference memory cells and non-volatile memory cells described herein are biased in weak inversion as follows: Ids=Io * e (Vg-Vth) / nVt =w * Io * e (Vg) / nVt In the formula, w=e (-Vth) / nVt and where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the (effective or equivalent) threshold voltage of the memory cell, and Vt is the thermal voltage = k * where T / q, k is the Boltzmann constant, T is temperature in Kelvin, q is the electron charge, n is the slope coefficient = 1 + (Cdep / Cox), Cdep = capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is (Wt / L) * u * Cox * (n-1) * Vt 2where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0043] If an IV log converter is used to convert the input current Ids to an input voltage Vg using a memory cell (such as a reference memory cell or a peripheral memory cell) or transistor, then Vg is: Vg=n * Vt * log[Ids / wp * Io] where wp is the w of the reference or periphery memory cell.

[0044] For a memory array used as a vector matrix multiplier VMM array, the output current is: Iout=wa * Io * e (Vg) / nVt , i.e. Iout = (wa / wp) * Iin=W * Iin W=wa / wp=e (Vthp-Vtha) / nVt Iin=wp * Io * e (Vg) / nVt where wa=W of each memory cell of the memory array, Vthp is the (equivalent or effective) threshold voltage of the reference memory cell (or surrounding memory cell or transistor), and Vtha is the (equivalent or effective) threshold voltage of the array memory cell.

[0045] The word line or control gate can be used as the input of the memory cell for an input voltage.

[0046] Alternatively, the non-volatile memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=Beta * (Vgs-Vth) * Vds; beta=u * Cox * Wt / L W α (Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs-Vth).

[0047] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region. The bit line or source line can be used as the output of the memory cell.

[0048] For an IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region, or resistors can be used to linearly convert input and output currents to input and output voltages.

[0049] Alternatively, the memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2 * beta * (Vgs-Vth) 2 ;beta=u * Cox * Wt / L Wα(Vgs-Vth) 2 , that is, the weight W is (Vgs-Vth) 2 is proportional to.

[0050] The word lines, control gates, or erase gates can be used as inputs for memory cells operating in the saturation region, and the bit lines or source lines can be used as outputs for output neurons.

[0051] Alternatively, the memory cells of the VMM arrays described herein may be used in all regions or combinations thereof (subthreshold, linear, or saturation) for each layer or layers of a neural network.

[0052] FIG. 13 shows a neuron VMM array 1300 that is particularly suited for the memory cells 210 shown in FIG. 2 and used as synapses between an input layer and the next layer. The VMM array 1300 includes a memory array 1303 of non-volatile memory cells, a reference array 1301 of a first non-volatile reference memory cell, and a reference array 1302 of a second non-volatile reference memory cell. The reference arrays 1301 and 1302 arranged in columns of the array function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1314 (only some of which are shown) with current inputs flowing into them. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference mini-array matrix (not shown) or from a bandgap-based reference circuit.

[0053] The memory array 1303 serves two purposes. First, it stores the weights used by the VMM array 1300 in each memory cell. Second, it effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1301 and 1302 convert to input voltages and provide to word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory cell array 1303, and then adds all the results (memory cell currents) to generate outputs for each bit line (BL0-BLN), which are the inputs to the next layer or the last layer. With the memory array 1303 performing the multiplication and addition functions, the need for separate multiplication and addition logic is eliminated and is also power efficient. Here, voltage inputs are provided to word lines WL0, WL1, WL2, and WL3, and outputs appear on the respective bit lines BL0-BLN during read (inference) operations. The current placed on each bit line BL0-BLN performs a function of the sum of the currents from all the non-volatile memory cells connected to that particular bit line.

[0054] Table 6 shows the operating voltages for VMM array 1300. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells, and FLT indicates floating, i.e., no voltage is applied. The rows show the operations of read, erase, and program. Table 6: Operation of VMM Array 1300 in FIG. 13 [Table 6]

[0055] FIG. 14 shows a neuron VMM array 1400 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1400 includes a memory array 1403 of non-volatile memory cells, a reference array 1401 of first non-volatile reference memory cells, and a reference array 1402 of second non-volatile reference memory cells. The reference arrays 1401 and 1402 run in the row direction of the VMM array 1400. The VMM array is similar to the VMM 1300, except that the word lines run vertically in the VMM array 1400. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3) and outputs appear on the source lines (SL0, SL1) during a read operation. The current applied to each source line performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0056] Table 7 shows the operating voltages for the VMM array 1400. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells. The rows show the operations of read, erase, and program. Table 7: Operation of VMM Array 1400 in FIG. 14 [Table 7]

[0057] 15 shows a neuron VMM array 1500 that is particularly suited for the memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between the input layer and the next layer. The VMM array 1500 includes a memory array 1503 of non-volatile memory cells, a reference array 1501 of a first non-volatile reference memory cell, and a reference array 1502 of a second non-volatile reference memory cell. The reference arrays 1501 and 1502 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1512 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Multiplexer 1512 includes a corresponding multiplexer 1505 and cascoding transistor 1504 to ensure a constant voltage on each bit line (e.g., BLR0) of the first and second non-volatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0058] The memory array 1503 serves two purposes. First, it stores the weights used by the VMM array 1500. Second, the memory array 1503 multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1501 and 1502 convert to input voltages and provide to the control gates (CG0, CG1, CG2, and CG3)) by the weights stored in the memory cell array, and then adds all the results (cell currents) to generate an output that appears on BL0-BLN and is the input to the next layer or the input to the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic circuits and is also power efficient, where the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during read operations. The current applied to each bit line is a function of the sum of all the currents from the memory cells connected to that particular bit line.

[0059] The VMM array 1500 implements one-way tuning of the non-volatile memory cells in the memory array 1503. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be done, for example, using the precision programming techniques described below. If too much charge is added to the floating gate (in which case an incorrect value is stored in the cell), the cell must be erased and the series of partial programming operations must be redone. As shown, two rows that share the same erase gate (such as EG0 or EG1) must be erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0060] Table 8 shows the operating voltages for the VMM array 1500. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 8: Operation of VMM Array 1500 in FIG. 15 [Table 8]

[0061] FIG. 16 shows a neuron VMM array 1600, which is particularly suited for the memory cells 310 shown in FIG. 3 and is utilized as part of synapses and neurons between the input layer and the next layer. The VMM array 1600 comprises a memory array 1603 of non-volatile memory cells, a reference array 1601 or a first non-volatile reference memory cell, and a reference array 1602 of a second non-volatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 run vertically, and the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 run horizontally. The VMM array 1600 is similar to the VMM array 1600 except that the VMM array 1600 implements bidirectional tuning, where each individual cell can be fully erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate through the use of separate vertical EG lines. As shown, reference arrays 1601 and 1602 convert the input currents in terminals BLR0, BLR1, BLR2 and BLR3 into control gate voltages CG0, CG1, CG2 and CG3 (through the action of diode-connected reference cells via multiplexer 1614) which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0-BLN, each of which sums all the currents from the non-volatile memory cells connected to that particular bit line.

[0062] Table 9 shows the operating voltages for the VMM array 1600. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 9: Operation of VMM Array 1600 in FIG. 16 [Table 9]

[0063] The input to the VMM array can be analog levels, binary levels, timing pulses, or digital bits, and the output can be analog levels, binary levels, timing pulses, or digital bits (in this case an output ADC is required to convert the output analog level current or voltage to digital bits).

[0064] For each memory cell in the VMM array, each weight W can be implemented by a single memory cell, by a differential cell, or by two blended memory cells (an average of two or more cells). In the case of a differential cell, two memory cells are required to implement weight w as a differential weight (w=w+-w-). In the case of two blended memory cells, two memory cells are required to implement weight w as an average of two cells.

[0065] It is essential to program and erase non-volatile memory cells accurately and precisely to ensure that the proper amount of charge is present on the floating gate to store the proper weight in the cell.

[0066] What is needed is a VMM system that allows fine tuning on a word or page basis, where a word typically includes 8-64 memory cells each storing multiple logical bits (i.e., multi-level cells each storing, for example, 3-8 bits), and a page includes 64 memory cells each storing multiple logical bits. What is further needed is a high voltage circuit to generate the necessary voltages. What is further needed is an improved programming sequence to minimize the occurrence of undesirable effects such as erase gate upsets and control gate upsets. Summary of the Invention

[0067] Numerous embodiments are disclosed for performing fine tuning of pages or words of non-volatile memory cells in an analog neural memory. High voltage circuits are also disclosed that are used to generate high voltages applied to the terminals of the non-volatile memory cells during the fine tuning process. Programming sequences for applying voltages to the terminals to minimize the occurrence of anomalies during fine tuning are also disclosed.

[0068] In one embodiment, an analog neural memory system includes an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to a word line terminal of a row of the non-volatile memory cells; a plurality of bit lines, each bit line coupled to a bit line terminal of a column of the non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to an erase gate terminal of a word of the non-volatile memory cells.

[0069] In another embodiment, an analog neural memory system includes an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to a word line terminal of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to a bit line terminal of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to an erase gate terminal of a page of non-volatile memory cells, the page including two words of non-volatile memory cells in adjacent rows.

[0070] In another embodiment, an analog neural memory system includes an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to a word line terminal of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to a bit line terminal of a column of non-volatile memory cells; and a plurality of erase gate lines, each erase gate line coupled to an erase gate terminal of a page of non-volatile memory cells, the page including two words of non-volatile memory cells in adjacent rows.

[0071] In another embodiment, a method of performing tuning on a word or page of non-volatile memory cells includes the steps of erasing the word or page of non-volatile memory cells, performing soft programming of the word or page of non-volatile memory cells, performing coarse programming of the word or page of non-volatile memory cells, performing fine programming of the word or page of non-volatile memory cells, and identifying any fast bits in the word or page of non-volatile memory cells so that they may be programmed using a different sequence than the normal (non-fast and non-slow) bits.

[0072] In another embodiment, a method of programming words of non-volatile memory cells in an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a control gate terminal, a source line terminal, and an erase gate terminal, the method includes ramping up a voltage of the control gate terminal of the word of the non-volatile memory cell during a first period of time, ramping up a voltage of the source line terminal of the word of the non-volatile memory cell during a second period after the first period of time, and ramping up a voltage of the erase gate line terminal of the word of the non-volatile memory cell during a third period of time after the second period of time.

[0073] In another embodiment, a method of programming words of non-volatile memory cells in an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a control gate terminal, a source line terminal, and an erase gate terminal, the method includes ramping up a voltage of the control gate terminal of the word of the non-volatile memory cell to an intermediate voltage during a first period of time, ramping up a voltage of the source line terminal of the word of the non-volatile memory cell during a second period after the first period, ramping up a voltage of the erase gate line terminal of the word of the non-volatile memory cell during a third period of time after the second period, and further ramping up the voltage of the control gate terminal of the word of the non-volatile memory cell during a fourth period of time after the third period.

[0074] In another embodiment, a method of programming words of non-volatile memory cells in an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a control gate terminal, a source line terminal, and an erase gate terminal, the method includes ramping up a voltage of the control gate terminal of the word of the non-volatile memory cell to a first intermediate voltage during a first period of time, ramping up a voltage of the source line terminal of the word of the non-volatile memory cell to a second intermediate voltage during a second period of time after the first period, ramping up a voltage of the erase gate line terminal of the word of the non-volatile memory cell, further ramping up the voltage of the source line terminal of the word of the non-volatile memory cell, and further ramping up the voltage of the control gate terminal of the word of the non-volatile memory cell to a third intermediate voltage during a third period of time after the third period, and further ramping up the voltage of the control gate terminal of the word of the non-volatile memory cell during a fourth period of time after the third period.

[0075] In another embodiment, a method of programming words of non-volatile memory cells in an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a control gate terminal, a source line terminal, and an erase gate terminal, the method includes ramping up a voltage of the source line terminal of the word of the non-volatile memory cell during a first period of time, and ramping up a voltage of the erase gate line terminal of the word of the non-volatile memory cell and ramping up a voltage of the control gate terminal of the word of the non-volatile memory cell during a second period after the first period.

[0076] In another embodiment, an analog neural memory system includes an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to a word line terminal of a row of the non-volatile memory cells; a plurality of bit lines, each bit line coupled to a bit line terminal of a column of the non-volatile memory cells; and a circuit decoder block including an erase gate decoder for providing an erase gate decode signal, a control gate decoder for providing two control gate signals, and a source line decoder for providing a source line decode signal.

[0077] In another embodiment, an analog neural memory system includes an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to a word line terminal of a row of the non-volatile memory cells; a plurality of bit lines, each bit line coupled to a bit line terminal of a column of the non-volatile memory cells; and a circuit decoder block including an erase gate decoder for providing an erase gate decode signal, a control gate decoder for providing four control gate signals, and a source line decoder for providing a source line decode signal.

[0078] In another embodiment, an analog neural memory system includes an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to a word line terminal of a row of the non-volatile memory cells; a plurality of bit lines, each bit line coupled to a bit line terminal of a column of the non-volatile memory cells; and a circuit decoder block including an erase gate decoder for providing two erase gate decode signals, a control gate decoder for providing eight control gate signals, and a source line decoder for providing a source line decode signal.

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[0115] [Brief description of the drawings]

[0116] [Figure 1] 1 illustrates a prior art artificial neural network. [Diagram 2] 1 shows a prior art split-gate flash memory cell. [Diagram 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Diagram 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] 1 illustrates another prior art split-gate flash memory cell. [Figure 7] 1 shows a prior art stacked gate flash memory cell. [Figure 8] 1 shows a prior art twin split gate memory cell. [Figure 9] 1 illustrates various levels of an exemplary artificial neural network that utilizes one or more VMM arrays. [Figure 10] 1 illustrates a VMM system that includes a VMM array and other circuitry. [Figure 11] 1 illustrates an exemplary artificial neural network that utilizes one or more VMM systems. [Figure 12] 1 illustrates one embodiment of a VMM array. [Figure 13] 1 illustrates another embodiment of a VMM array. [Figure 14] 1 illustrates another embodiment of a VMM array. [Figure 15] 1 illustrates another embodiment of a VMM array. [Figure 16] 1 illustrates another embodiment of a VMM array. [Figure 17] 1 illustrates one embodiment of a VMM array with page-based erase capability. [Figure 18] 1 illustrates one embodiment of a VMM array with word-based erasure capability. [Figure 19] 1 illustrates another embodiment of a VMM array with word-based erasure capability. [Figure 20A] 1 illustrates a page or word based bidirectional tuning algorithm. [Figure 20B] 1 illustrates a page or word based bidirectional tuning algorithm. [Figure 21A] 1 shows a fast bit algorithm. [Figure 21B] 4 shows the slow bit algorithm. [Figure 22] 1 shows a VMM system. [Figure 23] The high voltage generation block is shown. [Figure 24] High voltage maximum circuit is shown. [Diagram 25] 3 shows another high voltage generation block. [Figure 26] 3 shows another high voltage generation block. [Figure 27A] 1 illustrates an embodiment of a ramp-down circuit. [Figure 27B] 1 illustrates an embodiment of a ramp-down circuit. [Figure 28] A ramp-up circuit is shown. [Figure 29A] 1 illustrates an embodiment of a high voltage decode circuit. [Figure 29B] 1 illustrates an embodiment of a high voltage decode circuit. [Figure 29C] 1 illustrates an embodiment of a high voltage decode circuit. [Figure 30A] 1 illustrates an embodiment of a high voltage decode circuit. [Figure 30B] 1 illustrates an embodiment of a high voltage decode circuit. [Figure 30C] 1 illustrates an embodiment of a high voltage decode circuit. [Figure 30D] 1 illustrates an embodiment of a high voltage decode circuit. [Diagram 31] The program sequence is shown. [Diagram 32] 4 shows another program sequence. [Diagram 33] 4 shows another program sequence. [Diagram 34] 4 shows another program sequence. [Diagram 35] 1 shows an erase sequence. [Figure 36A] 1 illustrates an embodiment of a high voltage decode circuit. [Figure 36B] 1 illustrates an embodiment of a high voltage decode circuit. [Figure 36C] 1 illustrates an embodiment of a high voltage decode circuit. [Figure 37] 1 shows a high voltage latch circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0117] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays. <<Improved VMM system with page or word based tuning>>

[0118] FIG. 17 illustrates a VMM array 1700. The VMM array 1700 implements bidirectional tuning of a page of non-volatile memory cells. Here, an exemplary page 1701 includes two words, each in a different row. A word includes multiple memory cells, e.g., 8-64. A particular word may include only one cell or a few cells. Pairs of adjacent rows share a source line, such as SL0 or SL1. All cells in the page 1701 share a common erase gate line, controlled by an erase gate enable transistor 1702, which controls the provision of a voltage to the erase gate terminal EGW of all cells in the exemplary page set 1701. Here, all cells in the page 1701 may be erased simultaneously. Then, the cells in the page 1701 may be bidirectionally tuned via program and erase operations, and some cells in the page 1701 may be unidirectionally tuned via a program operation. The program operation may include precision programming techniques described below with reference to FIG. 20 and FIG. 21. If too much electronic charge is placed on the floating gate (causing the wrong current value, i.e., a lower current value than intended, to be stored in the cell), the cell must be erased and the partial programming sequence must be repeated.

[0119] FIG. 18 illustrates a VMM array 1800. The VMM array 1800 implements bidirectional tuning of a word of non-volatile memory cells, where an exemplary word 1801 includes multiple cells in a row. All cells in the word 1801 share a common erase gate line controlled by an erase gate enable transistor 1802, which controls the provision of a voltage to the erase gate terminals of all cells in the word 1801. Now, all cells in the word 1801 can be erased simultaneously. The cells in the word 1801 can then be bidirectionally tuned via program and erase operations. The program operation can include precision programming techniques described below. If too much electronic charge is placed on the floating gate (resulting in an incorrect current value, i.e., a current value lower than the intended current value being stored in the cell), the cell needs to be erased and the partial programming operation sequence needs to be restarted.

[0120] FIG. 19 illustrates a VMM array 1900. The VMM array 1900 implements bidirectional tuning of words of non-volatile memory cells. Here, an exemplary word 1901 includes two half-words of cells. Each half-word belongs to a row that shares an erase gate. All cells in the word 1901 share a common erase gate line connected to an erase gate terminal EGW. Unlike the VMM arrays 1800 and 1700, there is no erase gate enable transistor. Here, all cells in the word 1901 can be erased simultaneously. The cells in the word 1901 can then be bidirectionally tuned via program and erase operations. The program operation can include precision programming techniques described below. If too much electronic charge is placed on the floating gate (resulting in an incorrect current value, i.e., a current value lower than the intended current value being stored in the cell), the cell needs to be erased and the partial programming operation sequence needs to be restarted.

[0121] Although not shown in Figures 17, 18, and 19, source line pull-down bit lines, tuning bit lines (used for ultra-fine programming), dummy bit lines, and redundant bit lines may be used, as described in U.S. Provisional Patent Application No. 62 / 981,757, entitled "Ultra-Precise Tuning of Analog Neural Memory Cells In A Deep Learning Artificial Neural Network," filed February 26, 2020, which is incorporated by reference herein.

[0122] FIG. 20A illustrates a page / word tuning algorithm 2000 that may be applied to the VMM arrays 1700, 1800, or 1900 of FIGS.

[0123] First, a word or page is erased (step 2001). Second, deep programming is performed on unused cells (step 2002). Deep programming is used to program the cells to a state (or target level) having a small cell current during a read operation, e.g., in the <pA range. Third, coarse programming is performed on the cells within a word or page (step 2003). Coarse programming is used to program the cells within 50 to 500% of the target using a coarse target level, e.g., a large (coarse) increment voltage and / or program current and / or program timing. Fourth, fine programming is performed on the cells within a word or page (step 2004). Fine programming is used to program the cells within + / -5 to 30% of the target using a fine target level, e.g., a small (fine) increment program voltage and / or program current and / or program timing. Fifth, ultra-fine programming is optionally performed on the cells within a word or page (step 2005). Ultra-fine programming is used to program the cells to the final target level using precise very small increment voltages and / or program currents and / or program timings. The percentage achieved within the final target level of the coarse / fine / ultra-fine programming is traded off against the size of the increment level and / or program timing in order to minimize noise such as program quantization noise (size of the increment), interference noise, various coupling noises, FG-FG coupling noise, etc.

[0124] FIG. 20B illustrates a page / word tuning algorithm 2050 that may be applied to the VMM arrays 1700, 1800, or 1900 of FIGS. 17-19. The page / word tuning algorithm 2050 is similar to the page / word tuning algorithm 2000 of FIG. 20A, except that the page / word tuning algorithm 2050 further includes steps for processing fast or slow bits. Steps 2001-2005 occur similarly to FIG. 20A. In step 2006, or alternatively step 2003, a determination is made whether the word or page contains any fast or slow bits (step 2006). Fast bits are bits that require a shorter programming period than normal bits to reach a desired level, and slow bits are bits that require a longer programming period than normal bits to reach a desired level. A fast bit can be detected by monitoring the program speed of the cell, such as by measuring delta Ir / delta tprog (change in current over time, e.g., current change over K consecutive pulses)>a predefined R factor, e.g., K=2 pulses. A slow bit can be detected by monitoring the program speed delta Ir / delta tprog<a predefined R factor. If no, the algorithm stops. If yes, a fast or slow bit cell is identified and flagged. Any programming of that word or page thereafter will utilize the fast or slow bit algorithm, as discussed below with reference to Figures 21A and 21B.

[0125] Applicant has previously disclosed various techniques for performing coarse, fine, and ultra-fine programming in U.S. Provisional Patent Application No. 62 / 981,757, filed February 26, 2020, entitled "Ultra-Precise Tuning of Analog Neural Memory Cells in a Deep Learning Artificial Neural Network," which is incorporated herein by reference.

[0126] FIG. 21A shows a fast bit algorithm 2100. It is executed when a word or page is determined to contain one or more fast bit cells, also known as fast bits. First, the word or page is erased or partially erased (step 2101). Second, the fast bits are programmed and verified (step 2102). This is done, for example, with lower than default (or constant) voltage increments and / or lower than default program currents and / or lower than default timings. Next, normal bits, i.e., all bits not flagged as fast or slow bits, are programmed and verified (step 2103). This is done, for example, with default settings for coarse / fine / ultra-fine voltage increments and / or program currents and / or timings.

[0127] FIG. 21B shows the slow bit algorithm 2150. It is executed when a word or page is determined to contain one or more slow bitcells. First, the word or page is erased or partially erased (step 2151). Second, the slow bitcells are programmed and verified (step 2152). This is done, for example, with larger than default voltage increments and / or larger than default program currents and / or larger than default timings. Next, normal bits, i.e., all bits not flagged as slow or fast bits, are programmed and verified (step 2153). This is done, for example, with default settings for coarse / fine / ultra-fine voltage increments and / or program currents and / or timings.

[0128] In one embodiment, the slow bitcells are tuned first to avoid disturbing other cells in the same page / word, then the fast bitcells, then the normal bitcells.

[0129] In one embodiment, the slow bitcells are tuned first (to avoid disturbing other cells in the same page / word), then the normal bitcells, then the fast bitcells.

[0130] 22 shows a block diagram of a VMM system 2200. The VMM system 2200 includes a VMM array 2201, a row decoder 2202, a high voltage decoder 2203, a column decoder 2204, a bit line driver 2205, an input circuit 2206, an output circuit 2207, a control logic 2208, and a bias generator 2209. The VMM system 2200 further includes a high voltage generation block 2210, including a charge pump 2211, a charge pump regulator 2212, and a high voltage level generator 2213. The VMM system 2200 further includes a (program / erase, or also known as weight tuning) algorithm controller 2214, an analog circuit 2215, a control logic 2216, and a test control logic 2217. The systems and methods described below may be implemented in the VMM system 2200.

[0131] The input circuit 2206 may include circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter), an AAC (analog-to-analog converter such as a current-to-voltage converter), a PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 2206 may implement a normalization, a linear or nonlinear up / downscaling function, or an arithmetic function. The input circuit 2206 may implement a temperature compensation function for the input. The input circuit 2206 may implement an activation function such as ReLU or sigmoid. The output circuit 2207 may include circuits such as an ADC (analog-to-digital converter for converting neuron analog output to digital bits), an AAC (analog converter such as a current-to-voltage converter), an APC (analog-to-pulse converter), or any other type of converter. The output circuit 2207 may implement an activation function such as ReLU or sigmoid. The output circuit 2207 may implement statistical normalization, regularization, up / down scaling functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) of the neuron outputs. The output circuit 2207 may implement temperature compensation functions for the neuron outputs or array outputs (such as bit line outputs) to keep the power consumption of the array approximately constant, or to increase the accuracy of the array (neuron) outputs, such as by keeping the IV slope approximately the same.

[0132] Figure 23 shows a high voltage generation block 2300, which is one embodiment of the high voltage generation block 2210 of Figure 22. The high voltage generation block 2300 includes a charge pump 2211 and a charge pump regulator 2212, which generate various high voltages and are controlled by an enable signal, here labeled as EN_CP. The charge pump 2211 and the charge pump regulator 2212 provide the high voltages necessary to control a gate high voltage generator 2301, an erase gate high voltage generator 2302, and a source line high voltage generator 2303, which are controlled by enable signals, respectively labeled EN_CGGEN, EN_EGGEN, and EN_SLGEN, to provide high voltage signals to the control gate lines, erase gate lines, and source lines, respectively, as needed during program, erase, or read operations in the VMM array.

[0133] 24 shows a high voltage maximum circuit used to provide a high voltage power supply that identifies the highest voltage between a first high voltage HV1 and a second high voltage HV2 and outputs the highest voltage. Comparator 2401 receives HV1div and HV2div, which are level-shifted and divided (i.e., low voltage) versions of HV1 and HV2, respectively. Comparator 2401 outputs a high signal on line COMPO if HV1 is higher than HV2, and outputs a low signal on line COMPO if HV1 is lower than HV2. The output of comparator 2401 on line COMPO is provided to high voltage level shifter 2402 and high voltage level shifter 2403. When the output of comparator 2401 is low, high voltage level shifter 2402 outputs a low signal on line 2402B, and high voltage level shifter 2403 outputs a low signal on line 2403A. When the output of comparator 2401 is high, high voltage level shifter 2402 outputs a low signal on line 2402A and high voltage level shifter 2403 outputs a low signal on line 2403B. PMOS transistors 2404, 2405, 2406, and 2407 are configured with their gates coupled to corresponding ones of lines 2402A, 2402B, 2403A, and 2403B as shown. When high voltage level shifter 2402 outputs a low signal on line 2402B and high voltage level shifter 2403 outputs a low signal on line 2403A, the high voltage output 2408 corresponds to HV2 and there is less voltage drop across PMOS transistors 2406, 2407. If high voltage level shifter 2402 outputs a low signal on line 2402A and high voltage level shifter 2403 outputs a low signal on line 2403B, then the high voltage output 2408 corresponds to HV1 and the voltage drop across PMOS transistors 2404, 2405 will be less.

[0134] 25 shows a high voltage generation block 2500, which is another embodiment of the high voltage generation block 2412. Here, the high voltage generation block 2500 includes a charge pump and regulator 2501 enabled by a signal EN_CP, a high voltage incremental reference generator 2503, and a high voltage buffer operational amplifier 2502. The voltage at the output of the charge pump regulator 2503 can be controlled based on a signal sent to the gate of a MOS transistor in the high voltage incremental reference generator 2503 by trimming the portion of the output voltage HVSUP output by the charge pump 2501 that is fed to the input of the high voltage operational amplifier HVOPA.

[0135] 26 shows a high voltage generation block 2600, which is another embodiment of the high voltage generation block 2412. The high voltage generation block 2600 receives an input VIN (low voltage signal) and generates an HV output (high voltage signal) as an output, and includes an operational amplifier 2603, a variable resistor 2601, and a variable resistor 2602, where the gain of the operational amplifier 2601 depends on the value of the variable resistor 2601 and / or the variable resistor 2602. Thus, the high voltage increment value is controlled by the value of the variable resistor 2601 and / or the resistor 2602.

[0136] 27A illustrates a ramp-down control circuit 2700 including a clamp PMOS transistor 2701, an enable NMOS transistor 2702, and a current bias NMOS transistor 2703, configured as shown. The ramp-down circuit 2700 receives a voltage HV to be ramped down at the source of PMOS transistor 2701 and generates an output signal VHV_DET at the drain of PMOS transistor 2701, which has a peak value of HV and will ramp down towards ground in response to a low-to-high transition of a signal ENRMP provided to the gate of enable NMOS transistor 2702. The output signal VHV_DET is ramped down from the HV value to a Vcas+Vt PH value by a current controlled by current bias NMOS transistor 2703 when ENRMP is equal to high.

[0137] 27B shows another ramp-down control circuit 2750, which includes a cascoding NMOS transistor 2751, a shunt NMOS transistor 2753 (which provides a ramp current), an enable NMOS transistor 2572, a current source 2754, and a capacitor 2755. The ramp-down speed of the HV node is controlled by I / C (=I or reference current source 2754 / capacitance of capacitor 2755).

[0138] 28 shows a ramp-up circuit 2800 including an NMOS cascoding transistor 2801, an enable NMOS transistor 2802, a current shunt NMOS transistor 2803, a current source 2805, and a capacitor 2804 configured as shown. The ramp-up circuit 2800 controls the ramping rate of the HV node with the ratio I / C (=I reference current source 2805 / capacitance of capacitor 2804) by shunting the current through NMOS transistor 2803. The ramp rate of the HV node is such that the current injected through capacitor 2804 is equal to the current source 2805.

[0139] 29A, 29B, and 29C show a VMM high voltage decode circuit including a word line decoder circuit 2901, a source line decoder circuit 2904, and a high voltage level shifter 2908 suitable for use in a memory cell of the type shown in FIG.

[0140] In Figure 29A, word line decoder circuit 2901 includes a PMOS select transistor 2902 (controlled by signal HVO_B) and an NMOS deselect transistor 2903 (controlled by signal HVO_B), configured as shown. HVSUP is a high voltage supply, such as that provided by a charge pump and regulator. WLSUP provides a voltage supply to the word line WL when HVO_B is enabled.

[0141] 29B, source line decoder circuit 2904 includes an NMOS monitor transistor 2905 (controlled by signal HVO), a drive transistor 2906 (controlled by signal HVO), and a deselect transistor 2907 (controlled by signal HVO_B), configured as shown. When signal HVO is high, the voltage appearing on line SLSUP passes through line SL and appears on monitor line SL_MON. When signal HVO_B is high, line SL is pulled down.

[0142] 29C, a high voltage level shifter 2908 receives an enable signal EN and outputs a high voltage signal HVO and its complement HVO_B between HVSUP, e.g., 12V, and an HVSUP_LOW supply, e.g., 0V (if HVSUP is equal to a mid-level, e.g., about 5V) or 2.5V (if HVSUP is equal to, e.g., 12V). For example, HVO can be 5V and HVO_B can be 0V, or HVO can be 12V and HVO_B can be 2.5V.

[0143] 30A-30D show a VMM high voltage decode circuit including an erase gate decoder circuit 3001, a control gate decoder circuit 3004, a source line decoder circuit 3007, and a high voltage level shifter 3011 suitable for use in a memory cell of the type shown in FIG.

[0144] In Figures 30A and 30B, the erase gate decoder circuit 3001 and the control gate decoder circuit 3004 use the same design as the word line decoder circuit 2901 of Figure 29A.

[0145] In FIG. 30C, source line decoder circuit 3007 uses the same design as source line decoder circuit 2904 of FIG.

[0146] In FIG. 30D, high voltage level shifter 3011 uses the same design as high voltage level shifter 2908 in FIG.

[0147] 31-34 illustrate a programming sequence of voltages applied to the control gate, source line and erase gate terminals of one or more non-volatile memory cells during a program operation.

[0148] 31 shows a program sequence 3100 in which the control gate voltage CG ramps up during a first period, then the source line voltage SL ramps up during a second period, and then the erase gate voltage EG ramps up during a third period. All three voltages reach steady state at their peak values ​​during a fourth period, then the ramping sequence reverses, with the erase gate voltage EG ramping down during a fifth period, the source line voltage SL ramping down during a sixth period, and the control gate voltage CG ramping down during a seventh period. The program sequence 3100 minimizes the occurrence of erase gate anomalies.

[0149] 32 shows a program sequence 3200 in which the control gate voltage CG ramps up to an intermediate value during a first period, then the source line voltage SL ramps up to its peak value during a second period, then the erase gate voltage EG ramps up to its peak value during a third period, then the control gate voltage CG ramps up to its peak value during a fourth period, all three voltages reach a steady state at their peak values ​​during a fifth period, then the control gate voltage CG ramps down to an intermediate value during a sixth period, the erase gate voltage EG ramps down during a seventh period, the source line voltage SL ramps down during an eighth period, and the control gate voltage CG ramps down to ground during a ninth period.

[0150] 33 shows a program sequence 3300 in which the control gate voltage CG first ramps up to a first intermediate value during a first period, then the source line voltage SL ramps up to a second intermediate value during a second period. Then, during a third period, the control gate voltage CG ramps up to a third intermediate value while the source line voltage SL ramps up to its peak voltage and the erase gate voltage EG ramps up to its peak voltage. Finally, during a fourth period, the control gate voltage CG ramps up to its peak voltage. Then, all three voltages reach steady state at their peak values ​​during a fifth period. Then, during a sixth period, the control gate voltage CG ramps down to a third intermediate value, then during a seventh period, the source line voltage SL ramps down to a second intermediate value, then during an eighth period, the control gate voltage CG ramps down to the first intermediate value, then during a ninth period, the erase gate voltage EG ramps down to ground, then during a tenth period, the source line voltage SL ramps down to ground, then during an eleventh period, the control gate voltage CG ramps down to ground.

[0151] 34 shows a program sequence 3400 in which the source line voltage SL ramps up to a peak value during a first period, then the control gate line voltage CG ramps up to its peak value during a second period, and simultaneously the erase gate voltage EG ramps up to its peak value. Then, during a third period, all three voltages reach steady state at their peak values. Then, the control gate line voltage CG ramps down during a fourth period, and simultaneously the erase gate voltage EG ramps down, and then, during a fifth period, the source line voltage SL ramps down. The program sequence 3400 minimizes the occurrence of control gate anomalies.

[0152] FIG. 35 shows an erase sequence 3500 in which the inhibit control gate line or inhibit source line (CG-inh or SL-inh applied to unselected cells during operation) ramps up during a first period, and then the erase gate voltage EG ramps up during a second period. Then all voltages reach steady state at their peak value during a third period. Then the erase gate voltage EG ramps down during a fourth period, and then the inhibit control gate line or inhibit source line (CG-inh or SL-inh) ramps down during a fifth period. This sequence is suitable for arrays suitable for bidirectional tuning, such as, for example, FIG. 12, FIG. 14, FIG. 16, FIG. 19.

[0153] Figures 36A, 36B, and 36C show a high voltage decoder 3600 utilizing the decode sub-circuit blocks 3001 (EG decoder), 3004 (CG decoder), and 3007 (SL decoder) of Figure 30. Different arrangements of the sub-circuit blocks are made as shown to optimize for different configurations and optimizations.

[0154] 36A shows a circuit decoder block 3601 that includes a circuit decoder block 3602. The circuit decoder block 3602 includes an EG decoder that provides one EG decoded signal, a CG decoder that provides two CG decoded signals, and an SL decoder that provides one SL decoded signal.

[0155] 36B shows a circuit decoder block 3611 that includes a circuit decoder block 3612. The circuit decoder block 3612 includes an EG decoder that provides one EG decoded signal, a CG decoder that provides four CG decoded signals, and an SL decoder that provides one SL decoded signal.

[0156] 36C shows a circuit decoder block 3621 that includes a circuit decoder block 3622. The circuit decoder block 3622 includes an EG decoder that provides two EG decoded signals, a CG decoder that provides eight CG decoded signals, and an SL decoder that provides one SL decoded signal.

[0157] FIG. 37 shows a high voltage latch circuit 3700. The high voltage latch circuit 3700 includes a cross-coupled high voltage transistor inverter formed by PMOS transistors 3711 and 3712, NMOS transistors 3713 and 3714, and enable transistors 3715 and 3716. The enable signals ENB 3706 and EN 3705 are logic signals (e.g., 0V / Vdd) when VHVSUP 3701 is at an intermediate voltage (e.g., about 1.8-5V) and are at another intermediate voltage (e.g., both signals EN 3705=ENB 3706=Vdd=1.8V) when VHVSUP 3701 is at a voltage greater than the intermediate HV voltage (e.g., >5V) and when VHVSUP_LOW 3702 is at an intermediate level such as 1.8V. An output HVOUT 3704 and a complementary signal HVOUTB 3703 are generated.

[0158] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly on" (with no intermediate material, element, or gap disposed between them) and "indirectly on" (with an intermediate material, element, or gap disposed between them). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed between them) and "indirectly adjacent" (with an intermediate material, element, or gap disposed between them), "attached" includes "directly attached" (with no intermediate material, element, or gap disposed between them) and "indirectly attached to" (with an intermediate material, element, or gap disposed between them), and "electrically coupled" includes "directly electrically coupled" (without an intermediate material or element disposed between them that electrically connects the elements together) and "indirectly electrically coupled to" (with an intermediate material or element disposed between them that electrically connects the elements together). For example, forming an element "above a substrate" can include forming the element directly on the substrate, with no intermediate materials / elements between them, and forming the element indirectly on the substrate, with one or more intermediate materials / elements between them.

Claims

1. 1. An analog neural memory system, comprising: an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to a word line terminal of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to a bit line terminal of a column of non-volatile memory cells; 1. An analog neural memory system comprising: a plurality of erase gate enable transistors, each erase gate enable transistor coupled to an erase gate terminal of a word of a non-volatile memory cell.

2. a plurality of erase gate lines, each erase gate line coupled to an erase gate enable transistor; 10. The system of claim 1, wherein a word of non-volatile memory cells can be erased simultaneously by turning on the erase gate enable transistors.

3. 2. The system of claim 1, wherein a word in a first row and a word in a second row adjacent to the first row share one source line.

4. 2. The system of claim 1, wherein each word comprises one cell.

5. The system of claim 1 , wherein each word includes two or more cells.

6. 1. An analog neural memory system, comprising: an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to a word line terminal of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to a bit line terminal of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to an erase gate terminal of a page of non-volatile memory cells, the page including two words of non-volatile memory cells in adjacent rows.

7. a plurality of erase gate lines, each erase gate line coupled to an erase gate enable transistor; 7. The system of claim 6, wherein a word of non-volatile memory cells can be erased simultaneously by turning on the erase gate enable transistors.

8. 1. An analog neural memory system, comprising: an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to a word line terminal of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to a bit line terminal of a column of non-volatile memory cells; a plurality of erase gate lines, each of which is coupled to an erase gate terminal of a page of non-volatile memory cells, the page including two words of non-volatile memory cells in adjacent rows;

9. 9. The system of claim 8, wherein non-volatile memory cells forming a word can be simultaneously programmed or erased by turning on an erase gate enable transistor coupled to a corresponding one of the plurality of erase gate lines.

10. The system of claim 8 , wherein the erase gate lines are orthogonal to the control gate lines.

11. 1. A method for performing tuning on a word or page of non-volatile memory cells, the method comprising: performing programming of a word of said non-volatile memory cells or a page of said non-volatile memory cells; and identifying any high speed bits within the word of the non-volatile memory cells or the page of the non-volatile memory cells.

12. 12. The method of claim 11, wherein the identifying step comprises monitoring a programming rate of each cell in the word or page.

13. 12. The method of claim 11, wherein the identifying step comprises monitoring current over time during programming of each cell in the word or page.

14. 12. The method of claim 11, further comprising erasing a word of the non-volatile memory cells or a page of the non-volatile memory cells.

15. 12. The method of claim 11, further comprising performing soft programming of a word of the non-volatile memory cells or a page of the non-volatile memory cells.

16. 12. The method of claim 11, wherein the step of performing programming comprises coarse programming of a word of the non-volatile memory cells or a page of the non-volatile memory cells.

17. 17. The method of claim 16, wherein the step of performing programming comprises fine programming of a word of the non-volatile memory cells or a page of the non-volatile memory cells.

18. 20. The method of claim 17, further comprising, after the step of performing fine programming, performing ultra-fine programming of a word of the non-volatile memory cells or a page of the non-volatile memory cells.

19. erasing a word of the non-volatile memory cells or a page of the non-volatile memory cells; programming and verifying high speed bits in a word of said non-volatile memory cells or in a page of said non-volatile memory cells; and programming and verifying non-fast bits in the word of the non-volatile memory cells or the page of the non-volatile memory cells; The method of claim 11 , wherein the programming of the fast bits and the programming of the non-fast bits utilize different programming sequences.

20. 1. A method of programming a word of non-volatile memory cells in an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a control gate terminal, a source line terminal, and an erase gate terminal, the method comprising: ramping up a voltage at a control gate terminal of a word of said non-volatile memory cell during a first period of time; ramping up the voltage of the source line terminal of the word of the non-volatile memory cell during a second period after the first period; and ramping up a voltage on the erase gate line terminal of the word of the non-volatile memory cell during a third period of time after the second period of time.

21. ramping down the voltage on the erase gate line terminal of the word of the non-volatile memory cell during a fourth period after the third period; ramping down the voltage on the source line terminal of the word of the non-volatile memory cell during a fifth period after the fourth period; 21. The method of claim 20, further comprising: ramping down the voltage at the control gate terminal of the word of the non-volatile memory cell during a sixth period of time after the fifth period of time.

22. 21. The method of claim 20, wherein the array of non-volatile memory cells forms an analog neural memory.

23. 1. A method of programming a word of non-volatile memory cells in an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a control gate terminal, a source line terminal, and an erase gate terminal, the method comprising: ramping up a control gate voltage of a control gate terminal of a word of said non-volatile memory cell to an intermediate voltage during a first time period; ramping up a source line voltage on the source line terminal of the word of the non-volatile memory cell during a second period after the first period; ramping up an erase gate voltage on the erase gate line terminal of a word of the non-volatile memory cell during a third period after the second period; and ramping up the control gate voltage of a control gate terminal of a word of the non-volatile memory cell during a fourth period of time after the third period of time.

24. during a fourth period after the third period, ramping down the control gate voltages of the control gate terminals of the words of the non-volatile memory cells to an intermediate voltage; ramping down the erase gate voltage on the erase gate line terminal of the word of the non-volatile memory cell during a fifth period after the fourth period; during a sixth period after the fifth period, ramping down the source line voltage of the source line terminal of the word of the non-volatile memory cell; 24. The method of claim 23, further comprising: during a seventh period after the sixth period, ramping down the control gate voltages of control gate terminals of words of the non-volatile memory cells.

25. 24. The method of claim 23, wherein the array of non-volatile memory cells forms an analog neural memory.

26. 1. A method of programming a word of non-volatile memory cells in an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a control gate terminal, a source line terminal, and an erase gate terminal, the method comprising: ramping up a voltage at a control gate terminal of a word of said non-volatile memory cell to a first intermediate voltage during a first period of time; ramping up the voltage of the source line terminal of the word of the non-volatile memory cell to a second intermediate voltage during a second period after the first period; during a third period after the second period, ramping up a voltage on the erase gate line terminal of the word of the non-volatile memory cell, further ramping up the voltage on the source line terminal of the word of the non-volatile memory cell, and further ramping up the voltage on the control gate terminal of the word of the non-volatile memory cell to a third intermediate voltage; and ramping up the voltage at the control gate terminal of the word of the non-volatile memory cell during a fourth period of time after the third period of time.

27. during a fifth period after the fourth period, ramping down the voltage at the control gate terminal of the word of the non-volatile memory cell to the third intermediate voltage; during a sixth period after the fifth period, ramping down the voltage of the source line terminal of the word of the non-volatile memory cell to the second intermediate voltage; during a seventh period after the sixth period, ramping down the voltage at the control gate terminal of the word of the non-volatile memory cell to the first intermediate voltage; ramping down the voltage at the erase gate terminal of a word of the non-volatile memory cell during an eighth period after the seventh period; ramping down the voltages on source line terminals of words of the non-volatile memory cells during an eighth period after the seventh period; 27. The method of claim 26, further comprising: ramping down the voltage at the control gate terminal of the word of the non-volatile memory cell during a ninth period after the eighth period.

28. 27. The method of claim 26, wherein the array of non-volatile memory cells forms an analog neural memory.

29. 1. A method of programming a word of non-volatile memory cells in an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a control gate terminal, a source line terminal, and an erase gate terminal, the method comprising: ramping up a voltage on the source line terminal of a word of the non-volatile memory cell during a first period; and ramping up a voltage at the erase gate line terminal of the word of the non-volatile memory cell and ramping up a voltage at a control gate terminal of the word of the non-volatile memory cell during a second period of time after the first period of time.

30. during a third period after the second period, ramping down the voltage on the erase gate line terminal of the word of the non-volatile memory cell and ramping down the voltage on the control gate terminal of the word of the non-volatile memory cell; 30. The method of claim 29, further comprising: ramping down the voltage on the source line terminal of the word of the non-volatile memory cell during a fourth period of time after the third period of time.

31. 30. The method of claim 29, wherein the array of non-volatile memory cells forms an analog neural memory.

32. 1. A method of programming a word of non-volatile memory cells in an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a control gate terminal, a source line terminal, and an erase gate terminal, the method comprising: A method comprising: ramping up a voltage at a control gate terminal of a word of said non-volatile memory cell over a period of time by a plurality of ramp steps.

33. 33. The method of claim 32, further comprising ramping up the voltage of the source line terminal of the word of the non-volatile memory cell.

34. 33. The method of claim 32, further comprising ramping up the voltage of the erase gate line terminal of the word of the non-volatile memory cells.

35. 33. The method of claim 32, wherein the array of non-volatile memory cells forms an analog neural memory.

36. 1. An analog neural memory system, comprising: an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to a word line terminal of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to a bit line terminal of a column of non-volatile memory cells; and a circuit decoder block including an erase gate decoder for providing an erase gate decode signal, a control gate decoder for providing two control gate signals, and a source line decoder for providing a source line decode signal.

37. 1. An analog neural memory system, comprising: an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to a word line terminal of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to a bit line terminal of a column of non-volatile memory cells; and a circuit decoder block including: an erase gate decoder for providing an erase gate decode signal; a control gate decoder for providing four control gate signals; and a source line decoder for providing a source line decode signal.

38. 40. The system of claim 37, further comprising a high voltage latch.

39. 1. An analog neural memory system, comprising: an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell including a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to a word line terminal of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to a bit line terminal of a column of non-volatile memory cells; and a circuit decoder block including: an erase gate decoder for providing two erase gate decode signals, a control gate decoder for providing eight control gate signals, and a source line decoder for providing a source line decode signal.

40. 40. The system of claim 39, further comprising a high voltage latch circuit.

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