Exposure method

By utilizing electrostatic repulsion with graphene or graphite to stabilize the mask and photoresist gap, the method addresses particle generation and alignment errors, ensuring precise pattern formation in integrated circuit manufacturing.

JP2025013083APending Publication Date: 2025-01-24筿原康子
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Patent Information

Application Number
JP2023136671
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2023-07-14
Publication Date
2025-01-24

AI Technical Summary

Technical Problem

Existing exposure methods for integrated circuits face issues with fine particle generation due to high pressure between the mask and photoresist, and positioning errors due to varying separation distances during alignment.

Method used

The method employs electrostatic repulsion using graphene or graphite to maintain a minute gap between the mask and photoresist, utilizing the high Young's modulus of graphene or graphite to stabilize the mask and enable precise alignment, with electrostatic forces maintaining a consistent distance.

Benefits of technology

This approach reduces mask vibration and particle adhesion, enabling accurate alignment and reduced positioning errors, facilitating high-precision pattern formation in integrated circuit manufacturing.

✦ Generated by Eureka AI based on patent content.

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Abstract

To provide an exposure method for manufacturing an inexpensive circuit having a high degree of integration.SOLUTION: A mask is suspended and fixed on a graphene or graphite plate, a lower surface of a pattern of the mask is covered by graphene or graphite, a photoresist is also covered by graphene via the ice layer, or graphene is firmly adhered onto the photoresist to cover it by an electrostatic force, an electrostatic repulsive force is allowed to work between the mask and the graphene cover of the photoresist, and the mask and the photoresist are separated in parallel by a fine distance and positioning is performed.SELECTED DRAWING: Figure 1
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Description

[0001] The present invention relates to an exposure method for manufacturing integrated circuits. [Background technology]

[0002] Since increasing the density of integrated circuits leads to higher performance, efforts to increase density have continued up to now.

[0003] Therefore, there has been a demand for an inexpensive exposure method that can obtain fine patterns with low running costs, which is essential for the production of integrated circuits. [Prior art documents]

[0004] [Patent Document 1] Patent Publication No. 2023-69982 Summary of the Invention [Problem to be solved by the invention]

[0005] When aligning the mask and photoresist in contact exposure or proximity exposure, if they are performed in close contact, the greater the pressure between the mask and photoresist, the greater the amount of fine particles generated. Also, if they are aligned with a small distance between them, the greater the distance, the greater the alignment error during contact exposure. [Means for solving the problem]

[0006] In order to achieve the above object, the method of the present invention utilizes electrostatic repulsion to obtain a minute gap between the mask and the photoresist by suspending and fixing the mask on a graphene or graphite plate. Effect of the Invention

[0007] Since the exposure method of the present invention employs the above-described method, the mask is unlikely to vibrate in the planar direction of the graphene or graphite, which is elastic and has a very high Young's modulus, and is robust, and can easily move within a small distance in the direction perpendicular to the graphene or graphite plane.

[0008] Also, when a mask pattern is sandwiched between graphene or graphite, different potentials are applied to the graphene or graphite on both sides of the mask pattern, and the graphene cover covering the photoresist is applied with the same potential as the graphene or graphite facing the mask, the distance between the two electrodes is x, and the distance between the two electrodes is 1 / x 2 This generates an electric repulsive force proportional to the distance between the photoresist and the mask, and the distance can be made very small and almost constant. [Brief description of the drawings]

[0009] [Figure 1] An explanatory diagram of contact exposure of the exposure method of the present invention when exposed to electron beam or EUV light. [Diagram 2] An explanatory diagram of the exposure method of the present invention when exposed to extremely short wavelength ultraviolet light. EXAMPLES

[0010] During electron beam or EUV light exposure as shown in Figure 1, the electron beam source side and the exposed area side are separated by a graphene partition 1, and the exposed area 2 is at a very low atmospheric pressure. A graphene or graphite plate 3 is placed on the exposed area 2 side, and a mask 7 with a pattern 6 sandwiched between the graphene or graphite upper surface 4 and the graphene or graphite lower surface 5 is hung below.

[0011] Underneath this is a solid layer of ice 10 on the upper surface of the photoresist 9 on the wafer 8, and a graphene envelope 11 is placed on top of this.

[0012] At this time, a positive potential is applied to the graphene or graphite upper surface 4, and a negative potential is applied to the graphene or graphite lower surface 5, sandwiching the pattern 6 therein from above and below to form a mask whose interior is at atmospheric pressure slightly higher than the very low atmospheric pressure of the exposed area 2.

[0013] A negative potential is applied to the graphene cover 11. If the distance between the graphene cover 11 and the graphene or graphite lower surface 5 is x, then 1 / x 2The mask 7 is separated from the graphene cover 11 by a minute distance by an electrostatic repulsive force proportional to the electrostatic force. At this time, the mask 7 is approximately parallel to the graphene cover 11.

[0014] In this state, the mask 7 is aligned with the wafer 8, and then the mask 7 is brought into close contact with the graphene cover 11 and exposed to electron beams or EUV light. At this time, since the graphene or graphite plate 3 has a very high Young's modulus and is strong, the mask 7 hardly vibrates in the planar direction of the graphene or graphite plate 3, and can be moved slightly with a weak force in the direction perpendicular to the graphene or graphite plate 3. Therefore, the positioning of the mask 7 can be performed accurately.

[0015] During electron beam exposure, the pattern 6 of the mask 7 is made of a slightly conductive material to prevent charging due to the electron beam. During EUV exposure, the pattern 6 of the mask 7 is made of an insulator.

[0016] When exposing to ultrashort wavelength ultraviolet light as shown in Fig. 2, a graphene or graphite upper surface 14 is attached to a mask 13 made of quartz or fluorite on a graphene or graphite plate 12, and a pattern 15 is formed on the lower surface. At this time, the pattern 15 is formed by phase difference. Then, a graphene or graphite lower surface 16 is attached to the lower surface of the pattern 15. The graphene or graphite upper surface 14 and the graphene or graphite lower surface 16 are at different potentials and face each other with a pattern 15 made of an insulator sandwiched therebetween.

[0017] A photoresist 18 is applied to a wafer 17, a layer of ice 19 is applied to the photoresist 18, and the ice layer 19 is covered with a graphene cover 20. The graphene cover 20 and the graphene or graphite underside 16 are at the same potential. The graphene cover 20 and the graphene or graphite underside 16 are aligned at a small distance by electrostatic repulsion, and in that state, exposure is performed by proximity exposure, or the mask 13 is placed in close contact with the graphene cover 20 for exposure.

[0018] When the masks 7, 13 are in close contact with the graphene covers 11, 20, fine particles inevitably adhere to the masks 7, 13. However, since the patterns 6, 15 are covered with the graphene or graphite undersides 5, 16, fine particles do not become trapped between the patterns 6, 15, and the masks 7, 13 can be washed frequently with steam.

[0019] In one embodiment, the ice layers 10, 19 are not provided, and the photoresist 9, 18 and the graphene covers 11, 20 are directly bonded together by electrostatic force. [Industrial Applicability]

[0020] The present invention is utilized in the exposure process during integrated circuit fabrication. [Explanation of symbols] 1 Graphene barrier 2 Exposed area 3,12 Graphene or graphite plate 4,14 Graphene or graphite top surface 5,16 Graphene or graphite underside 6,15 Patterns 7,13 Mask 8,17 Wafer 9,18 Photoresist 10,19 Ice layer 11,20 Graphene cover

Claims

1. An exposure method in which a mask is suspended below the plane of a graphene or graphite plate and exposed by contact or proximity exposure.

2. 2. The exposure method according to claim 1, wherein different potentials are applied to the graphene or graphite on both sides of a mask having a slightly conductive pattern structure or an insulator structure sandwiched between the graphene or graphite, and the same potential is applied to the graphene covering the photoresist as to the graphene or graphite on the opposing mask side, thereby repelling the mask and the photoresist by electrostatic force, and aligning the mask and the photoresist by separating them by a minute distance.

Citation Information

Patent Citations

  • Exposure method

    JP2023069982A