Storage device and control method thereof

Abstract

To provide a storage device capable of suitably performing PLP processing and a control method thereof.SOLUTION: A storage device includes a non-volatile memory, a controller that controls the non-volatile memory, a volatile memory to be used by the controller, a power supply circuit that generates a power supply voltage using power supplied from an external power supply, and a capacitor to be used as a backup power supply when the power supplied to the power supply circuit is shut down. The controller includes: a determination unit which determines whether the charges remain in the capacitor even after processing for the power supply shutdown ends; and a storage unit which stores, when it is determined that the charges remain in the capacitor, predetermined write data stored in the volatile memory to the non-volatile memory.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a storage device and a control method thereof. [Background technology]

[0002] In a storage device having a PLP (Power Loss Protection) function, it is desirable to reduce the amount of data stored during PLP processing in order to reduce the capacity of the PLP capacitor. However, if the amount of data stored during PLP processing is reduced, there is a risk that the startup time when the storage device is started up thereafter will be longer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication US2016 / 0070336 Summary of the Invention [Problem to be solved by the invention]

[0004] A storage device capable of suitably performing PLP processing and a control method thereof are provided. [Means for solving the problem]

[0005] According to an embodiment, the storage device includes a non-volatile memory, a controller that controls the non-volatile memory, a volatile memory used by the controller, a power supply circuit that generates a power supply voltage using power supplied from an external power supply, and a capacitor that is used as a backup power supply when the power supply to the power supply circuit is interrupted. The controller includes a determination unit that determines whether or not the capacitor has a remaining charge even after a process that is performed when the power supply is interrupted is completed, and a storage unit that causes the non-volatile memory to store predetermined write data stored in the volatile memory when it is determined that the capacitor has a remaining charge. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing a configuration of an information processing system 1 according to a first embodiment. [Diagram 2] 3 is a diagram showing an example of a look-up table (LUT) and user data according to the first embodiment. FIG. [Diagram 3] 2 is a block diagram showing a functional configuration of a controller 13 according to the first embodiment. FIG. [Figure 4] 13 is a flowchart showing the flow of storing and discarding a subordinate table T3 by the information processing system 1 according to the first embodiment. [Diagram 5] 13 is a flowchart showing a flow of storing and discarding the middle level table T2 by the information processing system 1 according to the first embodiment. [Figure 6] 2 is a sequence diagram showing the flow of operations of the information processing system 1 according to the first embodiment. FIG. [Figure 7] FIG. 4 is a diagram showing an operation flow of an information processing system according to a first comparative example. [Figure 8] FIG. 11 is a diagram showing an operation flow of an information processing system according to a second comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In Fig. 1 to Fig. 8, the same components are denoted by the same reference numerals.

[0008] (First embodiment)

[0009] FIG. 1 is a block diagram showing the configuration of an information processing system 1 according to the first embodiment.

[0010] The information processing system 1 of this embodiment includes a storage device 2 and a host 3.

[0011] The storage device 2 is a memory device that functions as a data storage. The storage device 2 is, for example, a semiconductor storage device. The storage device 2 is, for example, an SSD (Solid State Drive). The storage device 2 has a PLP function. The process performed by the storage device 2 when it exercises the PLP function is called a PLP process.

[0012] The host 3 is an information processing device external to the storage device 2. The host 3 is, for example, a PC (Personal Computer).

[0013] The storage device 2 includes a non-volatile memory 11, a volatile memory 12, a controller 13, a power supply circuit 14, a PLP capacitor 15, and a capacitance measuring circuit 16.

[0014] The nonvolatile memory 11 is a nonvolatile memory that stores data transmitted from the host 3 to the storage device 2.

[0015] The volatile memory 12 is a volatile memory that temporarily stores various data.

[0016] The controller 13 is a device that controls the operation of the storage device 2. The controller 13 expands the data stored in the non-volatile memory 11 into the volatile memory 12.

[0017] The power supply circuit 14 is a circuit that uses power supplied from an external power source to generate a power supply voltage used in the storage device 2. The power supply circuit 14 is connected to the controller 13, supplies power to the controller 13, and is controlled by the controller 13.

[0018] The PLP capacitor 15 is a capacitor used as a backup power source for the storage device 2. The charge stored in the PLP capacitor 15 is used instead of power. If the power supply is interrupted while data is being written to the nonvolatile memory 11, the charge stored in the PLP capacitor 15 is used to write the data being written to the nonvolatile memory 11 (PLP function). The PLP capacitor 15 is electrically connected to the power supply circuit 14.

[0019] The capacitance measuring circuit 16 is a circuit that measures the capacitance of the PLP capacitor 15. The capacitance measuring circuit 16 is electrically connected to the power supply circuit 14 and the PLP capacitor 15. The capacitance measuring circuit 16 outputs the capacitance measurement result to the power supply circuit 14.

[0020] The controller 13 includes a CPU (Central Processing Unit) 13a, a host interface 13b, a non-volatile memory interface 13c, a volatile memory interface 13d, and a bus line 13e.

[0021] The CPU 13a is a device that performs various information processing. For example, a program stored in the nonvolatile memory 11 is expanded in the volatile memory 12 and executed by the CPU 13a. The CPU 13a can access the nonvolatile memory 11 via the nonvolatile memory interface 13c. The CPU 13a can access the volatile memory 12 via the volatile memory interface 13d. The CPU 13a can access the nonvolatile memory 11 by using a lookup table expanded in the volatile memory 12.

[0022] The host interface 13b is an interface for transmitting and receiving data between the host 3 and the storage device 2.

[0023] The nonvolatile memory interface 13c is an interface for transmitting and receiving data between the nonvolatile memory 11 and the controller 13.

[0024] The volatile memory interface 13 d is an interface for transmitting and receiving data between the volatile memory 12 and the controller 13 .

[0025] The bus line 13e is a wiring that connects the CPU 13a, the host interface 13b, the nonvolatile memory interface 13c, the volatile memory interface 13d, and the power supply circuit 14 to one another.

[0026] FIG. 2 is a diagram showing an example of a look-up table (LUT) and user data according to the first embodiment.

[0027] The lookup table T is a table that converts a logical address specified by the host 3 into a physical address of the non-volatile memory 11.

[0028] The user data D is data of a user of the host 3. The user data D is stored in the non-volatile memory 11 in cluster units. Here, the user data D includes 4096 clusters D1 to D4096. The number of clusters of the user data D may be other than 4096.

[0029] The lookup table T includes an upper table T1, a middle table T2, and a lower table T3. The middle table T2 is also called the upper lookup table. The middle table T2 is also called the second table. The lower table T3 is also called the lower lookup table. The lower table T3 is also called the first table.

[0030] The high-level table T1 includes four addresses as physical addresses corresponding to the four segments T2-1 to T2-4 of the middle-level table T2. These four addresses are called the addresses of the middle-level table T2.

[0031] The middle table T2 includes 128 addresses as physical addresses corresponding to the 128 segments T3-1 to T3-128 of the lower table T3. The 128 addresses are called addresses of the lower table T3. Segment T2-1 includes physical addresses of segments T3-1 to T3-32. Segment T2-2 includes physical addresses of segments T3-33 to T3-64. Segment T2-3 includes physical addresses of segments T3-65 to T3-96. Segment T2-4 includes physical addresses of segments T3-97 to T3-128. In this way, each segment of the middle table T2 includes physical addresses of 32 segments of the lower table T3. The addresses of the lower table T3 are also called second addresses.

[0032] The lower table T3 includes 4096 addresses as physical addresses of 4096 clusters D1 to D4096 of the user data D. The 4096 addresses are called addresses of the user data D. Each segment of the lower table T3 includes physical addresses of 32 clusters of the user data D. The addresses of the user data D are also called first addresses.

[0033] FIG. 3 is a block diagram showing the functional configuration of the controller 13 according to the first embodiment.

[0034] The controller 13 of this embodiment includes a detection unit 21, a FW (firmware) processing unit 22, a HW (hardware) processing unit 23, a storage unit 24, and a determination unit 25. These functions are realized, for example, by developing firmware stored in the non-volatile memory 11 into the volatile memory 12 and executing it by the CPU 13a.

[0035] The detection unit 21 is a functional unit that detects various FW events that occur in the storage device 2. For example, the detection unit 21 detects a PLP as a FW event.

[0036] The FW processing unit 22 is a functional unit that performs FW processing, which is processing related to the firmware of the storage device 2. For example, the FW processing unit 22 copies the FW work memory to the volatile memory 12 as the FW processing during the PLP processing.

[0037] The HW processing unit 23 is a functional unit that performs HW processing, which is processing related to the hardware of the storage device 2. For example, the HW processing unit 23 deletes the HW queue as HW processing during PLP processing.

[0038] The storage unit 24 is a functional unit that stores data stored in the volatile memory 12 in the nonvolatile memory 11. For example, the storage unit 24 stores write data (write data) of the volatile memory 12 in the nonvolatile memory 11 as the PLP process. The write data is, for example, expanded data, which is data obtained by expanding data stored in the nonvolatile memory 11 in the volatile memory 12, or derived data, which is data derived from the expanded data. For example, part of data of a lookup table stored in the nonvolatile memory 11 expanded in the volatile memory 12 is the write data (expanded data). In addition, when the lookup table expanded in the volatile memory 12 is changed to a new lookup table, the data itself after the change, a change history from the data before the change to the data after the change, and the like are the write data (derived data).

[0039] The determination unit 25 is a functional unit that determines the remaining amount of charge in the PLP capacitor 15. For example, the determination unit 25 determines whether or not there is still a remaining amount of charge in the PLP capacitor 15 after the end of the normal processing as the PLP processing. The normal processing is the PLP processing that is performed before the determination unit 25 determines whether or not there is still a remaining amount of charge in the PLP capacitor 15. On the other hand, the additional processing is the PLP processing that is performed after the determination unit 25 determines that there is still a remaining amount of charge in the PLP capacitor 15.

[0040] FIG. 4 is a flowchart showing the flow of storing and discarding the lower-level table T3 by the information processing system 1 according to the first embodiment.

[0041] When data stored in volatile memory 12 is stored in non-volatile memory 11 by the memory unit 24 (START), the memory unit 24 transmits a storage notification to the judgment unit 25, indicating that the data stored in volatile memory 12 has been stored in non-volatile memory 11 (S10).

[0042] Upon receiving the storage notification, the determination unit 25 determines whether or not the lower-level table T3 expanded in the volatile memory 12 has changed (S11). In this determination, the determination unit 25 compares the lower-level table T3 expanded in the volatile memory 12 with the lower-level table T3 stored in the non-volatile memory 11 to determine whether or not the lower-level table T3 expanded in the volatile memory 12 has changed.

[0043] If the lower-level table T3 expanded in the volatile memory 12 has changed (S11 YES), the determination unit 25 determines whether or not the detection unit 21 has detected a PLP as a FW event (S12).

[0044] If the lower-level table T3 expanded in the volatile memory 12 has not changed (S11 NO), the processing of the lower-level table T3 ends (END).

[0045] If detection unit 21 does not detect a PLP as a FW event (S12 NO), storage unit 24 stores in non-volatile memory 11 the change history from lower-level table T3 before the change to lower-level table T3 after the change (S13). The change history stored in non-volatile memory 11 is used by storage unit 24 to update lower-level table T3 in non-volatile memory 11. Storing the change history of lower-level table T3 ends the processing of lower-level table T3.

[0046] When the detection unit 21 detects a PLP as a FW event (YES in S12), the determination unit 25 determines whether or not there is any charge remaining in the PLP capacitor 15 (S14).

[0047] If there is no remaining charge in the PLP capacitor 15 (S14 NO), the determination unit 25 transmits a determination result notification, which means that there is no remaining charge in the PLP capacitor 15, to the storage unit 24 (S15).

[0048] The storage unit 24 discards the change history of the lower-level table T3 in response to the determination result notification from the determination unit 25 (S16). By discarding the change history of the lower-level table T3, the processing of the lower-level table T3 ends (END).

[0049] If the PLP capacitor 15 has a remaining charge (YES in S14), the determination unit 25 transmits a determination result notification indicating that the PLP capacitor 15 has a remaining charge to the storage unit 24 (S17).

[0050] In response to the determination result notification from the determination unit 25, the storage unit 24 stores the change history of the lower table T3 in the non-volatile memory 11 (S18). The change history stored in the non-volatile memory 11 is used by the storage unit 24 to update the lower table T3 in the non-volatile memory 11. When the change history of the lower table T3 is stored, the processing of the lower table T3 is completed (END).

[0051] FIG. 5 is a flowchart showing the flow of storing and discarding the middle level table T2 by the information processing system 1 according to the first embodiment.

[0052] When data stored in volatile memory 12 is stored in non-volatile memory 11 by the memory unit 24 (START), the memory unit 24 transmits a storage notification to the judgment unit 25, indicating that the data stored in volatile memory 12 has been stored in non-volatile memory 11 (S20).

[0053] Upon receiving the storage notification, the determination unit 25 determines whether or not the middle-level table T2 expanded in the volatile memory 12 has changed (S21). In this determination, the determination unit 25 compares the middle-level table T2 expanded in the volatile memory 12 with the middle-level table T2 stored in the non-volatile memory 11 to determine whether or not the middle-level table T2 expanded in the volatile memory 12 has changed.

[0054] If the middle level table T2 expanded in the volatile memory 12 has changed (S21 YES), the determination unit 25 determines whether or not a PLP has been detected as a FW event by the detection unit 21 (S22).

[0055] If the middle-level table T2 expanded in the volatile memory 12 has not changed (S21 NO), the processing of the middle-level table T2 ends (END).

[0056] If the detection unit 21 does not detect a PLP as a FW event (S22 NO), the storage unit 24 stores the changed middle-level table T2 in the non-volatile memory 11 as a snapshot (S23). The snapshot of the changed middle-level table T2 is all data of the changed middle-level table T2 at a certain point in time. A part of the snapshot stored in the non-volatile memory 11 is used by the storage unit 24 to update the middle-level table T2 in the non-volatile memory 11. The reason why a change history is stored for the lower table T3 and a snapshot is stored for the middle-level table T2 is that the amount of data in the lower table T3 is generally large and the amount of data in the middle-level table T2 is generally small. The processing of the middle-level table T2 ends when the changed middle-level table T2 is stored (END).

[0057] If the detection unit 21 detects a PLP as a FW event (YES in S22), the determination unit 25 determines whether or not there is any charge remaining in the PLP capacitor 15 (S24).

[0058] If there is no remaining charge in the PLP capacitor 15 (NO in S24), the determination unit 25 transmits a determination result notification, which means that there is no remaining charge in the PLP capacitor 15, to the storage unit 24 (S25).

[0059] The storage unit 24 discards the changed middle-level table T2 (S26) in response to the determination result notification from the determination unit 25. By discarding the changed middle-level table T2, the processing of the middle-level table T2 ends (END).

[0060] If the PLP capacitor 15 has a remaining charge (YES in S24), the determination unit 25 transmits a determination result notification indicating that the PLP capacitor 15 has a remaining charge to the storage unit 24 (S27).

[0061] In response to the determination result notification from determination unit 25, storage unit 24 stores the changed middle table T2 in non-volatile memory 11 (S28). The changed middle table T2 is stored as a snapshot. A portion of the snapshot stored in non-volatile memory 11 is used by storage unit 24 to update the middle table T2 in non-volatile memory 11. When the changed middle table T2 is stored, the processing of the middle table T2 is completed (END).

[0062] Next, the operation of the information processing system 1 of this embodiment will be described with reference to FIG.

[0063] FIG. 6 is a sequence diagram showing the flow of operations of the information processing system 1 according to the first embodiment.

[0064] When detecting a PLP, the detection unit 21 transmits a PLP detection notification indicating that a PLP has been detected to the FW processing unit 22 and the HW processing unit 23 (S101).

[0065] When receiving a PLP detection notification from the detection unit 21, the FW processing unit 22 copies data in the FW work memory in the non-volatile memory 11 to the volatile memory 12. The FW work memory is an area used for information processing related to FW. When the FW processing unit 22 finishes copying the data in the FW work memory, it transmits a copy completion notification, which means that copying of the data in the FW work memory has finished, to the storage unit 24 (S102).

[0066] When receiving a PLP detection notification from the detection unit 21, the HW processing unit 23 deletes the HW queue from the non-volatile memory 11. The HW queue is data for HW-related information processing that is waiting for its turn to be processed. When the HW processing unit 23 finishes deleting the HW queue, it transmits a deletion completion notification, which means that the deletion of the HW queue has been completed, to the storage unit 24 (S103).

[0067] When receiving the copy completion notification and the deletion completion notification from the FW processing unit 22 and the HW processing unit 23, the storage unit 24 stores at least a part of the write data stored in the volatile memory 12 as a snapshot in the non-volatile memory 11. When the storage unit 24 finishes storing the snapshot, it transmits a normal processing completion notification, which means that the normal processing has ended, to the determination unit 25 (S104).

[0068] When receiving the normal processing end notification from the storage unit 24, the determination unit 25 determines whether or not there is any charge remaining in the PLP capacitor 15 (S111).

[0069] When it is determined whether or not there is a remaining amount of charge, the determination unit 25 transmits a determination result notification indicating the determination result as to whether or not there is a remaining amount of charge to the storage unit 24 (S112).

[0070] When the storage unit 24 receives a notification of the determination result from the determination unit 25, the storage unit 24 performs processing according to the determination result.

[0071] When a determination result notification that there is remaining charge ([Remaining Amount]) is received, the storage unit 24 stores the change history of the lower-level table T3 and the changed intermediate-level table T2 in the non-volatile memory 11 (S113).

[0072] When a determination result notification is received that there is no remaining charge ([No remaining charge]), the storage unit 24 discards the change history of the lower-level table T3 and the changed intermediate-level table T2 (S114).

[0073] The determination unit 25 may determine whether the remaining charge of the PLP capacitor 15 is sufficient even after the normal processing is completed. For example, the determination unit 25 may determine whether the remaining charge of the PLP capacitor 15 is greater than a reference value at the end of the normal processing. The reason for making such a determination is that if the remaining charge is insufficient, the above process cannot be completed. Furthermore, the determination unit 25 may obtain a physical quantity based on the remaining charge as the remaining charge used for the determination, instead of obtaining the remaining charge itself. The physical quantity based on the remaining charge is, for example, the voltage of the electrodes of the PLP capacitor 15, or the usable time of the PLP capacitor 15 calculated from the remaining charge.

[0074] According to this embodiment, by discarding the change history of the lower table T3 and the changed middle-level table T2 during PLP processing, it is possible to reduce the amount of data stored during PLP processing and reduce the capacity of the PLP capacitor 15. Furthermore, according to this embodiment, by storing the change history of the lower table T3 and the changed middle-level table T2, it is possible to prevent the startup time of the storage device 2 from becoming longer. According to this embodiment, it is possible to both prevent the startup time of the storage device 2 from becoming longer and reduce the amount of data stored during PLP processing. According to this embodiment, it is possible to preferably perform PLP processing.

[0075] Next, the operation of the information processing systems of the first and second comparative examples will be described with reference to FIGS.

[0076] FIG. 7 is a diagram showing a flow of operations of the information processing system according to the first comparative example.

[0077] When the power supply to the power supply circuit is cut off (power cut), the storage device starts the PLP process. The PLP process is performed using the PLP capacitor as a backup power source. When the PLP process starts, the detection unit detects a PLP as a FW event (S1).

[0078] When the detector detects a PLP, the FW processor and the HW processor each copy the data in the FW work memory to a volatile memory and delete the HW queue (S2).

[0079] When the deletion of the HW queue is completed, the storage unit stores the lookup table stored in the volatile memory in the non-volatile memory (S3). For example, the storage unit stores the change history of the lower table stored in the volatile memory in the non-volatile memory. This is called LUT flash. The FW processing unit further copies the data in the FW work memory to the volatile memory.

[0080] When the above LUT flush and copy are completed, the storage unit stores at least a part of the write data stored in the volatile memory in the non-volatile memory as a snapshot (S4). For example, the storage unit stores the middle table stored in the volatile memory in the non-volatile memory as a snapshot.

[0081] The PLP process ends when the snapshot storage etc. is complete, and before the charge on the PLP capacitor runs out.

[0082] The lower level table in the non-volatile memory is updated by the storage unit using the change history stored in the non-volatile memory, and the middle level table in the non-volatile memory is updated by the storage unit using a part of the snapshots stored in the non-volatile memory.

[0083] FIG. 8 is a diagram showing a flow of operations of an information processing system according to a second comparative example.

[0084] When the power supply to the power supply circuit is cut off (power cut), the storage device starts the PLP process. The PLP process is performed using the PLP capacitor as a backup power source. When the PLP process starts, the detection unit detects a PLP as a FW event (S1).

[0085] When the detector detects a PLP, the FW processor and the HW processor each copy the data in the FW work memory to a volatile memory and delete the HW queue (S2).

[0086] In this comparative example, S3 is not performed. Therefore, when copying of data in the FW work memory and deletion of the HW queue are completed, the storage unit stores at least a part of the write data stored in the volatile memory in the non-volatile memory as a snapshot (S4). At this time, the storage unit does not store the middle table stored in the volatile memory as a snapshot in the non-volatile memory. As a result, the change history of the lower table and the middle table after the change are not stored in the non-volatile memory.

[0087] The PLP process ends when the snapshot storage etc. is complete, and before the charge on the PLP capacitor runs out.

[0088] According to this comparative example, it is possible to reduce the time required for PLP processing (PLP time) compared to the first comparative example. This is because the processing of S3 is not performed and the processing of S4 is reduced. However, in this comparative example, there is a risk that the startup time when starting up the storage device again will be longer. This is because the update history of the lower table and the middle table after the change were not stored in the PLP processing, and so these need to be restored when starting up the storage device.

[0089] In this comparative example, a time lag occurs between the end of the PLP process and the time when the remaining charge in the PLP capacitor runs out, because the PLP time is shortened.

[0090] The embodiments are illustrative and the scope of the invention is not limited thereto. [Explanation of symbols]

[0091] 1. Information Processing Systems 2 Storage device 3 Host 11 Non-volatile memory 12 Volatile Memory 13 Controller 13a CPU 13b Host Interface 13c Non-volatile Memory Interface 13d Volatile Memory Interface 13e Bus Line 14 Power circuit 15 PLP Capacitor 16 Capacitance measurement circuit 21 Detection unit 22 FW processing section 23 Hardware Processing Unit 24 Memory section 25 Judgment section

Claims

1. A non-volatile memory; A controller for controlling the non-volatile memory; a volatile memory for use by the controller; a power supply circuit that generates a power supply voltage using power supplied from an external power supply; a capacitor used as a backup power supply when the supply of power to the power supply circuit is interrupted; The controller: a determination unit that determines whether or not there is a remaining charge in the capacitor even after a process that is performed when the power supply is interrupted is completed; a storage unit that stores predetermined write data stored in the volatile memory in the nonvolatile memory when it is determined that the capacitor has a remaining charge; A storage device comprising:

2. 2. The storage device according to claim 1, wherein the predetermined write data is expanded data obtained by expanding memory data stored in the nonvolatile memory into the volatile memory, or derived data derived from the expanded data.

3. The storage device according to claim 2 , wherein the storage unit updates the stored data in the non-volatile memory by using the derived data stored in the non-volatile memory from the volatile memory.

4. 2. The storage device according to claim 1, wherein said predetermined write data is a part of an address conversion table for converting an external logical address of said storage device into an internal physical address of said storage device.

5. 5. The storage device according to claim 4, wherein said address conversion table includes a table of first addresses which are addresses of clusters of user data, and a table of second addresses which are addresses of segments including a plurality of first addresses.

6. the predetermined write data is expanded data obtained by expanding data stored in the nonvolatile memory into the volatile memory, or derived data derived from the expanded data, the stored data is the address conversion table, the expanded data is a table of the first addresses; The storage device according to claim 5 .

7. the derived data is a history of changes to the table of the first address; the storage unit updates the table of the first addresses in the non-volatile memory by using the change history stored in the non-volatile memory from the volatile memory. The storage device according to claim 6.

8. the predetermined write data is expanded data obtained by expanding data stored in the nonvolatile memory into the volatile memory, or derived data derived from the expanded data, the stored data is the address conversion table, the expanded data is a table of the second addresses; The storage device according to claim 5 .

9. the derived data is a table of the second addresses that have changed since the derived data was developed in the volatile memory, The storage unit stores the table of the second addresses from the volatile memory to the non-volatile memory as a snapshot; the storage unit updates the table of the second addresses in the non-volatile memory using a portion of the snapshot stored in the non-volatile memory from the volatile memory; The storage device according to claim 8.

10. A non-volatile memory; A controller for controlling the non-volatile memory; a volatile memory for use by the controller; a power supply circuit that generates a power supply voltage using power supplied from an external power supply; a capacitor used as a backup power source when the supply of power to the power supply circuit is interrupted; A method for controlling a storage device comprising: determining by the controller whether or not there is any charge remaining in the capacitor even after the process to be performed when the power supply is interrupted is completed; when it is determined that there is a remaining charge in the capacitor, the controller causes the predetermined write data stored in the volatile memory to be stored in the non-volatile memory; A method for controlling a storage device, comprising:

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