Power amplifier

Abstract

To provide a power amplifier that meets various requirements for preventing damage to power amplification transistors.SOLUTION: In a power amplifier circuit, a voltage detection circuit 10 outputs a first detection signal det1 giving notice of whether a power supply voltage Vcc applied to a power amplifier transistor is equal to or higher than a first threshold Vth and a second detection signal det2 giving notice of whether the power supply voltage Vcc is equal to or higher than a second threshold, which is larger than the first threshold; a bias circuit 30 supplies a bias current Ibb to the power amplifier transistor; a bias power supply circuit 50 generates a bias power supply current IeC to be supplied to the bias circuit; and a bias control circuit 70 controls the bias circuit. Under the control by the bias control circuit, the bias circuit operates in one of an on-mode in which the bias power supply current is supplied to the power amplifier transistor as a bias current, and an off-mode in which the bias current is supplied at the level lower than that in the on-mode or the supply is stopped.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a power amplifier device. [Background technology]

[0002] Patent Document 1 discloses a power amplifier circuit for high frequency signals having an overcurrent or overvoltage protection function. In the power amplifier circuit disclosed in Patent Document 1, the level of the power supply current supplied to the collector of the power amplifier transistor is limited so as to prevent the power amplifier transistor from being destroyed when an overcurrent or overvoltage occurs. In addition, when an overcurrent or overvoltage occurs, the current supplied to the base of a bias transistor for supplying a bias current to the power amplifier transistor is cut off, thereby stopping the operation of the power amplifier transistor. This prevents the amplifier transistor from being destroyed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2020 / 080332 Summary of the Invention [Problem to be solved by the invention]

[0004] Due to various internal and external factors and the characteristics of the power amplifier circuit, it becomes necessary to limit the level of the power supply current and change the conditions for stopping operation in order to prevent the breakdown of the power amplifier transistor. An object of the present invention is to provide a power amplifier device that can meet various requirements for preventing the breakdown of the power amplifier transistor. [Means for solving the problem]

[0005] According to one aspect of the present invention, a power amplifying transistor for amplifying the power of a high frequency signal; a voltage detection circuit that outputs a first detection signal indicating whether a power supply voltage applied to the power amplification transistor is equal to or higher than a first threshold and a second detection signal indicating whether a power supply voltage applied to the power amplification transistor is equal to or higher than a second threshold that is larger than the first threshold; a bias circuit for supplying a bias current to the power amplifier transistor; a bias power supply circuit for generating a bias power supply current to be supplied to the bias circuit; a bias control circuit for controlling the bias circuit; Equipped with the bias power supply circuit operates in one of a plurality of current generation modes for generating the bias power supply current having different levels; the plurality of current generation modes include a weak limit mode in which, when the first detection signal notifies that the power supply voltage is equal to or higher than the first threshold, the bias power supply current is reduced compared to when the first detection signal notifies that the power supply voltage is lower than the first threshold; the bias circuit, under control of the bias control circuit, operates in one of an on mode in which the bias power supply current generated by the bias power supply circuit is supplied to the power amplification transistor as the bias current, and an off mode in which the level of the bias current is lowered from that in the on mode or the supply is stopped; There is provided a power amplification device in which the bias control circuit can operate the bias circuit in the off mode when notified by the second detection signal that the power supply voltage is equal to or higher than the second threshold. Effect of the Invention

[0006] By selecting one mode from a plurality of current generation modes, the level of the bias power supply current can be changed. By lowering the level of the bias power supply current, the bias current of the power amplifier transistor is lowered, and as a result, the power supply current flowing into the collector is lowered. By lowering the power supply current, it is possible to suppress the destruction of the power amplifier transistor. By selecting one mode from a plurality of current generation modes, it is possible to flexibly respond to various requests for suppressing the destruction of the power amplifier transistor. By operating the bias circuit in the off mode, the amplification operation of the power amplifier transistor is stopped, and the destruction of the power amplifier transistor can be suppressed. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram of a power amplifier circuit according to a first embodiment. [Diagram 2] FIG. 2 is an equivalent circuit diagram of the voltage selection circuit. [Diagram 3] FIG. 3 is an equivalent circuit diagram of the first voltage-current conversion circuit of the bias power supply circuit. [Figure 4] FIG. 4 is a table showing the relationship between the first detection signal det1, the first mode selection signals p3 and p4, and the current generation modes. [Diagram 5] FIG. 5 is an equivalent circuit diagram of the second voltage-current conversion circuit of the bias control circuit. [Figure 6] FIG. 6 is a table showing the relationship between the second detection signal det2, the second mode selection signals p1 and p2, and the operation modes of the bias circuit. [Figure 7] FIG. 7 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to the H level, p4 is set to the L level, the bias power supply circuit operates in the limited mode, and the second mode selection signal p1 is set to the H level, p2 is set to the L level, and the bias circuit operates in the strong off mode. [Figure 8]FIG. 8 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to the H level and p4 is set to the L level, the bias power supply circuit operates in the limited mode, and the second mode selection signal p1 is set to the L level and p2 is set to the H level, the bias circuit operates in the weak off mode. [Figure 9] FIG. 9 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to the L level, the bias power supply circuit operates in the non-limit mode, and the second mode selection signals p1 and p2 are set to the H level and the L level, the bias circuit operates in the strong off mode. [Figure 10] FIG. 10 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to the L level, the bias power supply circuit operates in the non-limit mode, and the second mode selection signals p1 and p2 are set to the L level and the H level, the bias circuit operates in the weak-off mode. [Figure 11] FIG. 11 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to the L level and p4 is set to the H level, the bias power supply circuit operates in the strong restriction mode, and the second mode selection signals p1 and p2 are both set to the L level, and the bias circuit operates in the on mode. [Figure 12] FIG. 12 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to the L level, the bias power supply circuit operates in the non-limit mode, and the second mode selection signals p1 and p2 are both set to the L level, the bias circuit operates in the on mode. [Figure 13] FIG. 13 is an equivalent circuit diagram of a bias power supply circuit of a power amplifier circuit according to a modification of the first embodiment. [Figure 14] FIG. 14 is a block diagram of a power amplifier according to the second embodiment. [Figure 15] FIG. 15 is an equivalent circuit diagram of the first voltage-current conversion circuit of the power amplifier according to the second embodiment. [Figure 16]FIG. 16 is a table showing the relationship between the first mode selection signals p3, p4, and p5, the bias power supply current IeC, and the current generation mode of the bias power supply circuit in the power amplifier circuit according to the second embodiment. [Figure 17] FIG. 17 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to the L level, p5 is set to the H level, the bias power supply circuit operates in the variable limit mode, and the second mode selection signal p1 is set to the H level, p2 is set to the L level, and the bias circuit operates in the strong off mode (FIG. 6). [Figure 18] FIG. 18 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3, p4 are both set to the L level, p5 is set to the H level, the bias power supply circuit operates in the variable limit mode, and the second mode selection signal p1 is set to the L level, p2 is set to the H level, and the bias circuit operates in the weak off mode (FIG. 6). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] [First Example] A power amplifier according to a first embodiment will be described with reference to FIGS. 1 to 12. FIG. 1 is a block diagram of a power amplifier circuit according to Example 1. The power amplifier circuit according to Example 1 includes a power amplifier transistor 90, a voltage detection circuit 10, a bias circuit 30, a bias power supply circuit 50, and a bias control circuit .

[0009] As the power amplifier transistor 90, for example, a heterojunction bipolar transistor is used. A high frequency signal RFin is input to the base of the power amplifier transistor 90 via a DC cut capacitor 92. A power supply voltage Vcc is applied to the collector of the power amplifier transistor 90 via a choke coil 91. This causes a direct power supply current Icc to be supplied to the collector of the power amplifier transistor 90. An amplified high frequency signal RFout is output from the collector of the power amplifier transistor 90. Note that in the following embodiments, a field effect transistor may be used as each of the transistors including the power amplifier transistor 90. In this case, the configuration of each embodiment can be understood by replacing the base and gate of each transistor with the collector as the drain and the emitter with the source.

[0010] Next, the configuration and functions of the voltage detection circuit 10 will be described. The voltage detection circuit 10 includes a first comparator 11, a second comparator 12, a voltage divider circuit 13, and a voltage selection circuit 14. A reference voltage Vref3 and selection signals sel1 and sel2 are input to the voltage selection circuit 14. The voltage selection circuit 14 divides the reference voltage Vref3 in accordance with each of the selection signals sel1 and sel2 to generate a first voltage Vd1 and a second voltage Vd2. The second voltage Vd2 is higher than the first voltage Vd1.

[0011] The voltage divider circuit 13 divides the power supply voltage Vcc to generate a divided voltage value Vccd. The first comparator 11 compares the divided voltage value Vccd with the first voltage Vd1 and outputs the comparison result as a first detection signal det1. The second comparator 12 compares the divided voltage value Vccd with the second voltage Vd2 and outputs the comparison result as a second detection signal det2. The first comparator 11 is substantially the same as comparing the power supply voltage Vcc (indicated in parentheses in FIG. 1) before division of the divided voltage value Vccd with a first threshold value Vth1 (indicated in parentheses in FIG. 1) corresponding to the first voltage Vd1, and the second comparator 12 is substantially the same as comparing the power supply voltage Vcc with a second threshold value Vth2 (indicated in parentheses in FIG. 1) corresponding to the second voltage Vd2. The second threshold value Vth2 is higher than the first threshold value Vth1.

[0012] That is, the voltage detection circuit 10 detects whether the power supply voltage Vcc is equal to or greater than the first threshold Vth1, outputs the detection result as the first detection signal det1, and detects whether the power supply voltage Vcc is equal to or greater than the second threshold Vth2, and outputs the detection result as the second detection signal det2. As an example, the first comparator 11 sets the first detection signal det1 to an L level when the power supply voltage Vcc is less than the first threshold Vth1, and sets the first detection signal det1 to an H level when the power supply voltage Vcc is equal to or greater than the first threshold Vth1. The second comparator 12 sets the second detection signal det2 to an L level when the power supply voltage Vcc is less than the second threshold Vth2, and sets the second detection signal det2 to an H level when the power supply voltage Vcc is equal to or greater than the second threshold Vth2. It is preferable that the first comparator 11 and the second comparator 12 have a hysteresis characteristic.

[0013] Next, the detailed configuration of the voltage selection circuit 14 will be described with reference to FIG. 2 is an equivalent circuit diagram of the voltage selection circuit 14. The voltage selection circuit 14 includes a multi-stage voltage dividing circuit 15 in which a plurality of resistance elements are connected in multiple stages, and a plurality of switches 16 connected to a plurality of voltage extraction nodes of the multi-stage voltage dividing circuit 15. One of the plurality of switches 16 is selected by a selection signal sel1 and becomes conductive. As a result, the voltage (corresponding to the first voltage Vd1) of the voltage extraction node to which the conductive switch 16 is connected is input to one input node of the first comparator 11. The divided voltage value Vccd of the power supply voltage Vcc generated by the voltage dividing circuit 13 is input to the other input node of the first comparator 11. The circuit that generates the second voltage Vd2 (FIG. 1) input to the second comparator 12 is also the same as the circuit that generates the first voltage Vd1, and one of the plurality of switches is selected by the selection signal sel2.

[0014] Next, the bias circuit 30 will be described. 1, the bias circuit 30 includes a bias transistor 31, a resistor element 32, and a diode circuit 33. For example, a heterojunction bipolar transistor is used as the bias transistor 31. The diode circuit 33 includes two diode-connected heterojunction bipolar transistors, and the two heterojunction bipolar transistors are connected in series. A bias power supply current IeC input from a bias power supply circuit 50 is supplied to the collector of the bias transistor 31. An emitter current of the bias transistor 31 is supplied to the base of the power amplification transistor 90 as a bias current Ibb.

[0015] A bias control current IB input from a bias control circuit 70 is supplied to the base of the bias transistor 31 via a resistance element 32. A part of the bias control current IB flows to ground via a diode circuit 33. The base current (control current) of the bias transistor 31 is controlled by the bias control current IB.

[0016] The bias circuit 30 receives the bias control current IB from the bias control circuit 70 and can operate in either of the operation modes of "on mode" and "off mode". In the on mode, the bias power supply current IeC is supplied to the power amplifier transistor 90 as the bias current Ibb. In the off mode, the level of the bias current Ibb is lowered from that in the on mode and supplied to the power amplifier transistor 90, or the supply is stopped. The mode in which the level of the bias current Ibb is lowered from that in the on mode and supplied to the power amplifier transistor 90 is called "weak off mode", and the mode in which the supply of the bias current Ibb is stopped is called "strong off mode". In the weak off mode, since the level of the bias current Ibb is low, the power amplifier transistor 90 does not substantially perform an amplification operation. In other words, in the weak off mode, the power amplifier transistor 90 does not perform an amplification operation with a positive gain.

[0017] Next, the bias power supply circuit 50 will be described. The bias power supply circuit 50 includes a first voltage-current conversion circuit 51 and a first decoder 52. The first voltage-current conversion circuit 51 generates a bias power supply current IeC by converting a reference voltage Vref1 into a current in response to a command from the first decoder 52. The generated bias power supply current IeC is supplied to the bias circuit 30. The first decoder 52 provides a command to the first voltage-current conversion circuit 51 based on the first mode selection signals p3, p4, the first control signal cnt1, and the first detection signal det1.

[0018] As will be described later, the level of the bias power supply current IeC changes in response to a first detection signal det1 from the voltage detection circuit 10. The detailed configuration and operation of the bias power supply circuit 50 will be described later with reference to FIGS.

[0019] Next, the bias control circuit 70 will be described. The bias control circuit 70 includes a second voltage-current conversion circuit 71 and a second decoder 72. The second voltage-current conversion circuit 71 generates a bias control current IB by converting a reference voltage Vref2 into a current in response to a command from the second decoder 72. The generated bias control current IB is supplied to the bias circuit 30. The second decoder 72 provides a command to the second voltage-current conversion circuit 71 based on the second mode selection signals p1, p2, the second control signal cnt2, and the second detection signal det2.

[0020] As will be described later, the level of the bias control current IB changes in response to the second detection signal det2 from the voltage detection circuit 10. The detailed configuration and operation of the bias control circuit 70 will be described later with reference to FIGS.

[0021] Next, the configuration and operation of the bias power supply circuit 50 will be described with reference to FIGS.

[0022] FIG. 3 is an equivalent circuit diagram of the first voltage-current conversion circuit 51 of the bias power supply circuit 50. A first constant current source 57 is configured by an operational amplifier 53, an n-channel MOSFET 54, three resistor elements 55, and three switches 56. A reference voltage Vref1 is applied to the non-inverting input node of the operational amplifier 53. The three resistor elements 55 have different resistance values. A switch 56 is connected in series to each of the three resistor elements 55. Three series circuits each consisting of the resistor element 55 and the switch 56 are connected in parallel. The switch 56 is turned on and off by a command from the first decoder 52. When one switch 56 is selected from the three switches 56 and made conductive, the first constant current source 57 generates a constant level of current according to the resistance value of the resistor element 55 connected to the conductive switch 56.

[0023] 3 shows a configuration in which the resistance value is switched using three resistance elements 55 and three switches 56, but the method of switching the resistance value is not limited to this. For example, instead of providing a plurality of resistance elements with different resistance values ​​as many as the number of resistance values ​​to be realized as shown in FIG 3, a configuration may be adopted in which a resistance element group including a plurality of resistance elements with the same resistance value and a plurality of switches for switching the connections between these plurality of resistance elements is provided, and the combined resistance value of this resistance element group is switched.

[0024] Two p-channel MOSFETs configure a first current mirror 58. A battery voltage VBAT is applied to the sources of the two p-channel MOSFETs. The drain current of the n-channel MOSFET 54 (current generated by the first constant current source 57) is multiplied by K by the first current mirror 58 consisting of two p-channel MOSFETs to generate a bias power supply current IeC. The bias power supply current IeC is supplied to the bias circuit 30.

[0025] A first control signal cnt1, a first detection signal det1, and first mode selection signals p3 and p4 are input to the first decoder 52. The first control signal cnt1 stops the operation of the first voltage-current conversion circuit 51 and adjusts the amount of current based on switching of the resistance values ​​of the circuit including the three resistance elements 55.

[0026] The bias power supply circuit 50 can operate in any one of a plurality of current generation modes that generate bias power supply currents IeC of different levels. For example, when a table as shown in FIG. 4, which will be described later, is stored in the first decoder 52, the bias power supply circuit 50 can operate in any one of a plurality of current generation modes that generate bias power supply currents IeC of different levels. Next, the relationship between the first detection signal det1, the first mode selection signals p3 and p4, and the current generation modes will be described with reference to FIG. 4.

[0027] 4 is a table showing the relationship between the first detection signal det1, the first mode selection signals p3 and p4, and the current generation mode. When the first detection signal det1 is at the L level, that is, when the power supply voltage Vcc is less than the first threshold value Vth1, the bias power supply circuit 50 sets the level of the bias power supply current IeC to IeC1 regardless of the values ​​of the first mode selection signals p3 and p4.

[0028] When the first detection signal det1 is at H level, i.e., when the power supply voltage Vcc is equal to or higher than the first threshold Vth1, the bias power supply circuit 50 sets the level of the bias power supply current IeC in accordance with the values ​​of the first mode selection signals p3, p4. When the first mode selection signals p3, p4 are both at L level, the level of the bias power supply current IeC is set to IeC1. When the bias current Ibb at the level IeC1 is supplied to the power amplification transistor 90 (FIG. 1), the power amplification transistor 90 performs normal amplification operation. The current generation mode in which the level of the bias power supply current IeC is set to IeC1 is referred to as the "unlimited mode."

[0029] When the first mode selection signal p3 is at L level and p4 is at H level, the level of the bias power supply current IeC is set to IeCL. The level IeCL is a low level at which the power amplifier transistor 90 (FIG. 1) does not substantially perform an amplification operation even if the bias current Ibb at this level is supplied to the power amplifier transistor 90. The current generation mode in which the level of the bias power supply current IeC is set to IeCL is referred to as the "strong limiting mode."

[0030] When the first mode selection signal p3 is at H level and p4 is at L level, the level of the bias power supply current IeC is set to a constant level IeC2 lower than IeC1. In this state, the bias current Ibb supplied to the power amplification transistor 90 is lower than in the non-limiting mode. The power amplification transistor 90 performs an amplification operation with the operating point changed. The current generation mode in which the level of the bias power supply current IeC is set to IeC2 is referred to as the "weak limiting mode." In addition, since the limited level IeC2 is a constant value, it may also be referred to as the "constant limiting mode."

[0031] Next, the configuration and operation of the bias control circuit 70 will be described with reference to FIGS.

[0032] 5 is an equivalent circuit diagram of the second voltage-current conversion circuit 71 of the bias control circuit 70. The basic circuit configuration of the second voltage-current conversion circuit 71 is the same as the circuit configuration of the first voltage-current conversion circuit 51, and includes a second constant current source 77 and a second current mirror 78.

[0033] The second constant current source 77 includes an operational amplifier 73, an n-channel MOSFET 74, two resistor elements 75, and two switches 76. A reference voltage Vref2 is applied to the non-inverting input node of the operational amplifier 73. The two resistor elements 75 have different resistance values. The switch 76 is turned on and off in response to a command from the second decoder 72. When one of the two switches 56 is selected and made conductive, the second constant current source 77 generates a constant level of current according to the resistance value of the resistor element 75 connected to the conductive switch 76.

[0034] The drain current of the n-channel MOSFET 74 (current generated by the second constant current source 77) is multiplied by K in the second current mirror 78 to generate the bias control current IB. Note that the current multiplication factor of the second current mirror 78 is usually different from the current multiplication factor of the first current mirror 58 (FIG. 3). The bias control current IB is supplied to the bias circuit 30.

[0035] A second control signal cnt2, a second detection signal det2, and second mode selection signals p1 and p2 are input to the second decoder 72. The second control signal cnt2 stops the operation of the second voltage-current conversion circuit 71 and adjusts the amount of current. The bias control circuit 70 switches the operation mode of the bias circuit 30 between an on mode and an off mode by generating bias control currents IB of different levels. Next, the relationship between the second detection signal det2, the second mode selection signals p1 and p2, and the operation mode of the bias circuit 30 will be described with reference to FIG. 6.

[0036] 6 is a table showing the relationship between the second detection signal det2, the second mode selection signals p1 and p2, and the operation modes of the bias circuit 30. For example, when a table such as that shown in FIG. 6 is stored in the second decoder 72, it can be said that the bias circuit 30 can operate in any of a plurality of operation modes, or that the bias control circuit 70 can operate the bias circuit 30 in any of a plurality of operation modes. When the second detection signal det2 is at an L level, that is, when the power supply voltage Vcc is less than the second threshold value Vth2, the bias control circuit 70 sets the level of the bias control current IB to the normal level Lon regardless of the values ​​of the second mode selection signals p1 and p2.

[0037] When the second detection signal det2 is at H level, ie, when the power supply voltage Vcc is equal to or higher than the second threshold Vth2, the bias control circuit 70 sets the level of the bias control current IB in accordance with the values ​​of the second mode selection signals p1, p2.

[0038] When the second mode selection signals p1 and p2 are both at the L level, the level of the bias control current IB is set to the normal level Lon. When the bias control current IB of the normal level Lon is supplied to the bias circuit 30 (FIG. 1), the bias current Ibb supplied to the power amplification transistor 90 becomes approximately the same level as the bias power supply current IeC. The operating mode of the bias circuit 30 when the level of the bias control current IB is set to the normal level Lon is referred to as the "on mode."

[0039] When the second mode selection signal p1 is at L level and p2 is at H level, the level of the bias control current IB is set to a low level Llow. When the bias control current IB of the low level Llow is supplied to the bias circuit 30 (FIG. 1), the bias current Ibb supplied to the power amplification transistor 90 is reduced compared to the bias current Ibb in the on mode. In this state, the power amplification transistor 90 does not substantially perform amplification. The operation mode of the bias circuit 30 when the level of the bias control current IB is set to the low level Llow is referred to as the "weak off mode."

[0040] When the second mode selection signal p1 is at the H level and p2 is at the L level, the level of the bias control current IB is set to the off level Loff. Specifically, the supply of the bias control current IB is stopped. At this time, the bias current Ibb is no longer supplied to the power amplification transistor 90, and the amplification operation of the power amplification transistor 90 is stopped. The operation mode of the bias circuit 30 when the level of the bias control current IB is set to the off level Loff is referred to as the "strong off mode."

[0041] Next, the relationship between the power supply voltage Vcc and the power supply current Icc of the power amplifier transistor 90 will be described with reference to Figures 7 to 12. Figures 7 to 12 are graphs showing the relationship between the power supply voltage Vcc and the power supply current Icc of the power amplifier transistor 90. The horizontal axis represents the power supply voltage Vcc, and the vertical axis represents the power supply current Icc. The approximate breakdown region 60 of the power amplifier transistor 90 is shown by a hatched figure.

[0042] FIG. 7 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to the H level, p4 is set to the L level, the bias power supply circuit 50 operates in the limited mode, and the second mode selection signal p1 is set to the H level, p2 is set to the L level, and the bias circuit 30 operates in the strong off mode.

[0043] When the power supply voltage Vcc is less than the first threshold Vth1 (the first detection signal det1 is at the L level), the level of the bias power supply current IeC becomes IeC1, and when the power supply voltage Vcc is equal to or greater than the first threshold Vth1 (the first detection signal det1 is at the H level), the level of the bias power supply current IeC becomes IeC2, which is lower than IeC1. When the power supply voltage Vcc is less than the second threshold Vth2 (the second detection signal det2 is at the L level), the bias control current IB becomes the normal level Lon, and the bias circuit 30 (FIG. 1) operates in the on mode.

[0044] When the bias circuit 30 operates in the on mode, the power supply current Icc is proportional to the bias power supply current IeC. Specifically, the level of the power supply current Icc is approximately equal to the bias power supply current IeC multiplied by the current amplification factor hfe of the power amplifier transistor 90. For example, when the level of the bias power supply current IeC is IeC1, the level Icc1 of the power supply current Icc is equal to hfe×IeC1. When the level of the bias power supply current IeC is IeC2, the level Icc2 of the power supply current Icc is equal to hfe×IeC2.

[0045] When the power supply voltage Vcc becomes equal to or higher than the second threshold Vth2 (the second detection signal det2 becomes the off level Loff), the bias control current IB becomes the off level Loff, and the bias circuit 30 operates in the strong off mode. This causes the power supply current Icc to become almost zero. That is, the power supply current Icc decreases in a two-step manner as the power supply voltage Vcc increases.

[0046] When an excessive voltage (a voltage equal to or greater than the second threshold Vth2) is applied to the power amplifier transistor 90, the amplifying operation of the power amplifier transistor 90 is stopped, thereby preventing damage to the power amplifier transistor 90. As the power supply voltage Vcc increases, the power supply current Icc decreases in a two-step manner, making it possible to effectively use the safe operating area of ​​the power amplifier transistor 90.

[0047] FIG. 8 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to the H level, p4 is set to the L level, the bias power supply circuit 50 operates in the limited mode, and the second mode selection signal p1 is set to the L level, p2 is set to the H level, and the bias circuit 30 operates in the weak off mode.

[0048] The relationship between the power supply voltage Vcc and the power supply current Icc when the power supply voltage Vcc is less than the second threshold Vth2 is the same as that shown in FIG. 7. When the power supply voltage Vcc becomes equal to or greater than the second threshold Vth2 (the second detection signal det2 is at H level), the bias control circuit 70 sets the bias control current IB to a low level Low. As a result, the operation mode of the bias circuit 30 becomes the weak off mode, and the level of the power supply current Icc drops to IccL. At this level IccL, the power amplifier transistor 90 does not substantially perform an amplification operation.

[0049] Even if the power supply voltage Vcc becomes equal to or higher than the second threshold Vth2, the supply of the bias power supply current IeC is not completely stopped (i.e., the supply of the bias current Ibb is not completely stopped), so the recovery time is shorter than when the supply of the bias power supply current IeC is completely stopped.

[0050] FIG. 9 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to the L level, the bias power supply circuit 50 operates in the non-limit mode, and the second mode selection signals p1 and p2 are set to the H level and the L level, the bias circuit 30 operates in the strong off mode.

[0051] Since the bias power supply circuit 50 operates in the non-limiting mode, the level of the bias power supply current IeC is set to IeC1 regardless of whether the power supply voltage Vcc is equal to or higher than the first threshold Vth1. When the power supply voltage Vcc is less than the second threshold Vth2 (the second detection signal det2 is at the L level), the bias control current IB is set to the normal level Lon, so that the level of the power supply current Icc becomes Icc1 (hfe×IeC1).

[0052] When the power supply voltage Vcc becomes equal to or higher than the second threshold Vth2 (the second detection signal det2 is at the H level), the bias control current IB is set to the off level Loff. Therefore, the power supply current Icc becomes almost zero, as in the case of Fig. 7. In other words, when the power supply voltage Vcc increases, the power supply current Icc decreases in a single step.

[0053] FIG. 10 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to the L level, the bias power supply circuit 50 operates in the non-limit mode, and the second mode selection signal p1 is set to the L level, p2 is set to the H level, and the bias circuit 30 operates in the weak-off mode.

[0054] When the power supply voltage Vcc is less than the second threshold Vth2 (the second detection signal det2 is at the L level), the level of the power supply current Icc is the same as in the case of Fig. 9. When the power supply voltage Vcc becomes equal to or greater than the second threshold Vth2 (the second detection signal det2 is at the H level), the level of the power supply current Icc drops to IccL, as in the case of Fig. 8. In other words, when the power supply voltage Vcc increases, the power supply current Icc drops in a single step.

[0055] 11 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to the L level, p4 is set to the H level, the bias power supply circuit 50 operates in the strong restriction mode, and the second mode selection signals p1 and p2 are both set to the L level, and the bias circuit 30 operates in the on mode. The level of the bias control current IB is set to the normal level Lon regardless of the power supply voltage Vcc.

[0056] When the power supply voltage Vcc is less than the first threshold Vth1 (the first detection signal det1 is at the L level), the level of the bias power supply current IeC is set to IeC1, and the level of the power supply current Icc becomes Icc1 (hfe×IeC1). When the power supply voltage Vcc becomes equal to or greater than the first threshold Vth1 (the first detection signal det1 is at the H level), the level of the bias power supply current IeC is set to IeCL, and the level of the power supply current Icc decreases to IccL (hfe×IeCL). In other words, when the power supply voltage Vcc increases, the power supply current Icc decreases in a one-step manner.

[0057] 12 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to the L level, the bias power supply circuit 50 operates in the non-limit mode, and the second mode selection signals p1 and p2 are both set to the L level, the bias circuit 30 operates in the on mode. Regardless of the power supply voltage Vcc, the level of the bias control current IB is set to the normal level Lon, and the level of the bias power supply current IeC is set to IeC1.

[0058] For this reason, the level of the power supply current Icc is a fixed value Icc1 (hfe×IeC1) regardless of the power supply voltage Vcc.

[0059] Next, the excellent effects of the first embodiment will be described. In the first embodiment, as shown in Fig. 4 and Fig. 6, the level of the bias power supply current IeC and the operation mode of the bias circuit 30 can be changed by setting the second mode selection signals p1, p2 and the first mode selection signals p3, p4. For example, as shown in Fig. 7 and Fig. 8, the power supply current Icc of the power amplifier transistor 90 can be reduced in two steps with an increase in the power supply voltage Vcc. Furthermore, as shown in Figs. 9, 10, and 11, the power supply current Icc of the power amplifier transistor 90 can be reduced in one step. In addition, as shown in Fig. 12, the power supply current Icc of the power amplifier transistor 90 can be maintained approximately constant regardless of the power supply voltage Vcc.

[0060] In this way, the power supply current Icc can be flexibly reduced according to the characteristics of the power amplifying transistor 90, and the amplifying operation can be substantially stopped.

[0061] Next, a bias power supply circuit for a power amplifier circuit according to a modification of the first embodiment will be described with reference to FIG.

[0062] 13 is an equivalent circuit diagram of a bias power supply circuit 50 of a power amplifier circuit according to a modification of the first embodiment. In the first embodiment (FIG. 3), the level of the bias power supply current IeC is changed by changing the level of the current generated by the first constant current source 57. In contrast, in the modification shown in FIG. 13, the level of the current generated by the first constant current source 57 is constant. In this modification, the level of the bias power supply current IeC is changed by changing the current magnification of the first current mirror 58 according to the output of the first decoder 52.

[0063] Specifically, the circuit on the output side of the first current mirror 58 is composed of a parallel circuit of multiple transistors. The gate of at least one of the multiple transistors constituting the parallel circuit is connected to the gate of the transistor on the input side via a switch 59. The switch 59 is switched between conductive and non-conductive states by the output of the first decoder 52. By switching the switch 59 between conductive and non-conductive states, the current magnification of the first current mirror 58 can be changed.

[0064] As with the first voltage-current conversion circuit 51 shown in FIG. 13, the second voltage-current conversion circuit 71 (FIG. 5) of the bias control circuit 70 may have a fixed value of resistance element 75 (FIG. 5) without connecting switch 76, and the current magnification of the second current mirror 78 (FIG. 5) may be made variable.

[0065] Next, another modification of the first embodiment will be described. In the first embodiment, a bipolar transistor is used as the bias transistor 31, but a MOSFET may also be used. In this case, the bias power supply current IeC is supplied to the drain of the MOSFET. The bias control circuit 70 controls the gate bias of the MOSFET to switch the bias circuit 30 shown in FIG. 6 between the on mode, weak off mode, and strong off mode.

[0066] [Second Example] Next, a power amplifier according to a second embodiment will be described with reference to Fig. 14 to Fig. 18. Below, a description of the configuration common to the power amplifier according to the first embodiment described with reference to Fig. 1 to Fig. 12 will be omitted.

[0067] 14 is a block diagram of a power amplifier according to the second embodiment. In the first embodiment (FIG. 1), the output of the first decoder 52 and a reference voltage Vref1 are input to the first voltage-to-current converter circuit 51. In the second embodiment, the first voltage-to-current converter circuit 51 is further input with a divided value Vccd of the power supply voltage Vcc generated by the voltage divider circuit 13 and a first voltage Vd1 generated by the voltage selection circuit 14. Furthermore, in addition to the first mode selection signals p3 and p4, a third first mode selection signal p5 is input to the first decoder 52.

[0068] The first voltage-current conversion circuit 51 changes the level of the bias power supply current IeC based on the difference between a divided voltage value Vccd of the power supply voltage Vcc and a first voltage Vd1 (corresponding to a first threshold value Vth1).

[0069] 15 is an equivalent circuit diagram of the first voltage-current conversion circuit 51. The first voltage-current conversion circuit 51 of the power amplifier according to this modification includes a differential current generation circuit 80 in addition to a first constant current source 57 and a first current mirror 58. The differential current generation circuit 80 generates a differential current Idif having a level according to the difference between the power supply voltage Vcc and a first threshold value Vth1.

[0070] Next, the configuration and operation of the differential current generating circuit 80 will be described. A current source is configured by a third operational amplifier 81, a transistor 83, two resistance elements 84 connected in parallel, switches 85 connected in series to each of the resistance elements 84, and a fourth operational amplifier 82. The switch 85 is on / off controlled by the output of the first decoder 52.

[0071] A voltage corresponding to the difference between a divided value Vccd of the power supply voltage Vcc and a first voltage Vd1 (corresponding to a first threshold value Vth1) is applied to both ends of the resistance element 84. A current having a magnitude determined by the voltage (hereinafter referred to as a difference voltage) corresponding to the difference between the divided value Vccd of the power supply voltage Vcc and the first voltage Vd1 (corresponding to a first threshold value Vth1) and the resistance value of the resistance element 84 flows through the transistor 83.

[0072] Transistors 83 and 87 form a current mirror. When switch 86 is turned on, this current mirror operates and a current flows through transistor 87. Switch 86 is on / off controlled by the output of first decoder 52. The current flowing through transistor 87 is output to the outside as differential current Idif. The level of differential current Idif increases linearly with respect to the differential voltage. Furthermore, the rate of change of differential current Idif with respect to the differential voltage decreases as the resistance value of resistor element 84 increases.

[0073] The differential current Idif acts to reduce the current generated by the first constant current source 57. Therefore, the level of the bias power supply current IeC decreases according to the differential voltage. That is, when the differential voltage increases, the amount of decrease in the bias power supply current IeC increases.

[0074] 16 is a diagram showing the relationship between the first mode selection signals p3, p4, and p5 and the bias power supply current IeC and the current generation mode of the bias power supply circuit 50. When the first mode selection signal p5 is at an L level, the switch 86 is in a non-conductive state and the differential current Idif does not flow. Therefore, the operation of the bias power supply circuit 50 is the same as that of the first embodiment (FIG. 4).

[0075] When the first mode selection signal p5 is at H level and the first mode selection signals p3 and p4 are both at L level, if the first detection signal det1 becomes H level, the first decoder 52 turns on at least one of the switches 85 and 86. This causes the level IeC2 of the bias power supply current IeC to decrease according to the differential voltage. This current generation mode is called a "weak limit mode." It may also be called a variable limit mode to distinguish it from the constant limit mode (FIG. 4).

[0076] FIG. 17 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3, p4 are both set to the L level, p5 is set to the H level, the bias power supply circuit 50 operates in the variable limit mode, and the second mode selection signal p1 is set to the H level, p2 is set to the L level, and the bias circuit 30 operates in the strong off mode (FIG. 6).

[0077] In the example shown in Fig. 7 of the first embodiment, when the power supply voltage Vcc is equal to or greater than the first threshold Vth1, the level of the bias power supply current IeC drops to a constant value IeC2. In contrast, in the example shown in Fig. 17, when the power supply voltage Vcc is equal to or greater than the first threshold Vth1 (the first detection signal det1 is at H level), the level IeC2 of the bias power supply current IeC drops gradually and continuously as the power supply voltage Vcc rises. Similarly, the level Icc2 (hfe x IeC2) of the power supply current Icc also drops gradually and continuously, for example, linearly.

[0078] When the power supply voltage Vcc further increases and exceeds the second threshold Vth2 (the second detection signal det2 is at the H level), the bias control current IB goes to the off level Loff, and the supply of the bias power supply current IeC is stopped, thereby stopping the amplification operation of the power amplifier transistor 90 (FIG. 1).

[0079] FIG. 18 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3, p4 are both set to the L level, p5 is set to the H level, the bias power supply circuit 50 operates in the variable limit mode, and the second mode selection signal p1 is set to the L level, p2 is set to the H level, and the bias circuit 30 operates in the weak off mode (FIG. 6).

[0080] The relationship between the power supply voltage Vcc and the power supply current Icc when the power supply voltage Vcc is less than the second threshold Vth2 is the same as in the case of Fig. 17. When the power supply voltage Vcc becomes equal to or greater than the second threshold Vth2 (the second detection signal det2 is at the H level), the bias control current IB becomes the low level Llow, and the level of the bias power supply current IeC drops to IccL.

[0081] Next, the excellent effects of the second embodiment will be described. In the second embodiment, as in the first embodiment, the power supply current Icc can be flexibly reduced and the amplification operation can be substantially stopped in accordance with the characteristics of the power amplifier transistor 90. Furthermore, in the second embodiment, the bias power supply current IeC is gradually reduced with an increase in the power supply voltage Vcc, so that the safe operating area of ​​the power amplifier transistor 90 can be used more effectively.

[0082] The above-mentioned embodiments are merely examples, and it goes without saying that partial replacement or combination of the configurations shown in different embodiments is possible. Similar effects due to similar configurations of multiple embodiments are not mentioned in each embodiment. Furthermore, the present invention is not limited to the above-mentioned embodiments. For example, it will be obvious to those skilled in the art that various modifications, improvements, combinations, etc. are possible.

[0083] Based on the above examples described in this specification, the following invention is disclosed. <1> a power amplifying transistor for amplifying the power of a high frequency signal; a voltage detection circuit that outputs a first detection signal indicating whether a power supply voltage applied to the power amplification transistor is equal to or higher than a first threshold and a second detection signal indicating whether a power supply voltage applied to the power amplification transistor is equal to or higher than a second threshold that is larger than the first threshold; a bias circuit for supplying a bias current to the power amplifier transistor; a bias power supply circuit for generating a bias power supply current to be supplied to the bias circuit; a bias control circuit for controlling the bias circuit; Equipped with the bias power supply circuit operates in one of a plurality of current generation modes for generating the bias power supply current having different levels; the plurality of current generation modes include a weak limit mode in which, when the first detection signal notifies that the power supply voltage is equal to or higher than the first threshold, the bias power supply current is reduced compared to when the first detection signal notifies that the power supply voltage is lower than the first threshold; the bias circuit, under control of the bias control circuit, operates in one of an on mode in which the bias power supply current generated by the bias power supply circuit is supplied to the power amplification transistor as the bias current, and an off mode in which the level of the bias current is lowered from that in the on mode or the supply is stopped; The bias control circuit is capable of operating the bias circuit in the off mode when notified by the second detection signal that the power supply voltage is equal to or higher than the second threshold.

[0084] <2> The weak limit mode includes a fixed limit mode that reduces the bias power supply current to a fixed level that is lower than the level when the power supply voltage is notified to be less than the first threshold. <1> The power amplifier device according to claim 1 .

[0085] <3> The weak limit mode includes a variable limit mode that, as the power supply voltage increases, increases the amount of reduction in the level of the bias power supply current relative to the level of the bias power supply current when the power supply voltage is notified to be less than the first threshold. <1> or <2> The power amplifier device according to claim 1 .

[0086] <4> The bias power supply circuit includes: a first decoder that decodes a first mode selection signal that selects the current generation mode and the first detection signal; a first constant current source that changes the level of a current generated in response to an output from the first decoder; a first current mirror that outputs the current generated by the first constant current source as the bias power supply current; Includes <2> The power amplifier device according to claim 1 .

[0087] <5> The bias power supply circuit includes: a first decoder that decodes a first mode selection signal that selects the current generation mode and the first detection signal; A first constant current source; a first current mirror that changes a magnification of the current generated by the first constant current source in response to an output from the first decoder and outputs the current as the bias power supply current; Includes <2> The power amplifier device according to claim 1 .

[0088] <6> The bias power supply circuit includes: a first decoder that decodes a first mode selection signal that selects the current generation mode and the first detection signal; A first constant current source; a first current mirror that changes a magnification of the current generated by the first constant current source in response to an output from the first decoder and outputs the current as the bias power supply current; Includes <2> The power amplifier device according to claim 1 .

[0089] <7> The bias power supply circuit includes: a first decoder that decodes a first mode selection signal that selects the current generation mode and the first detection signal; a current source that changes the level of a current generated in response to an output from the first decoder and a difference between the power supply voltage and the first threshold; a first current mirror that outputs the current generated by the current source as the bias power supply current; Includes <3> The power amplifier device according to claim 1 .

[0090] <8> The plurality of current generation modes further includes an unrestricted mode in which the bias power supply current is maintained at a fixed value regardless of a state of the first detection signal. <1> ~ <7> 13. A power amplifying device according to claim 12, wherein:

[0091] <9> The plurality of current generation modes further includes a strong limiting mode in which, when the first detection signal notifies that the power supply voltage is equal to or higher than the first threshold, the level of the bias power supply current is reduced to a level at which the power amplifier transistor does not perform an amplifying operation. <1> ~ <8> 13. A power amplifying device according to claim 12, wherein:

[0092] <10> The bias control circuit can operate the bias circuit in a strong off mode in which the supply of the bias current to the power amplifier transistor is stopped when the bias circuit operates in the off mode. <1> ~ <9> 13. A power amplifying device according to claim 12, wherein:

[0093] <11> The bias control circuit can operate the bias circuit in the off mode in a weak off mode in which the bias current, the level of which is a reduced level of the bias power supply current, is supplied from the bias circuit to the power amplification transistor. <1> ~ <10> 13. A power amplifying device according to claim 12, wherein:

[0094] <12> The voltage detection circuit includes: a first comparator that compares the power supply voltage with the first threshold and outputs a comparison result as the first detection signal; a second comparator that compares the power supply voltage with the second threshold value and outputs a comparison result as the second detection signal; Claims including <1> ~ <11> 13. A power amplifying device according to claim 12, wherein:

[0095] <13> the bias circuit includes a bias transistor that supplies the bias current to the power amplification transistor; The emitter or source of the bias transistor is connected to the base or gate of the power amplifier transistor, the bias power supply current is supplied to the collector or drain of the bias transistor, and the control current of the bias transistor is controlled by the bias control circuit. <1> ~ <12> 13. A power amplifying device according to claim 12, wherein:

[0096] <14> The bias control circuit includes: a second decoder that decodes a second mode selection signal that selects the operation mode of the bias circuit and the second detection signal; a second constant current source that changes the level of the current it generates in response to an output from the second decoder; a second current mirror that supplies a current generated by the second constant current source to the bias circuit; Includes <1> ~ <13> 13. A power amplifying device according to claim 12, wherein:

[0097] <15> The bias control circuit includes: a second decoder that decodes a second mode selection signal that selects the operation mode of the bias circuit and the second detection signal; A second constant current source; a second current mirror that changes a magnification of the current generated by the second constant current source in response to an output from the second decoder and supplies the current to the bias circuit; Includes <1> ~ <13> 13. A power amplifying device according to claim 12, wherein: [Explanation of symbols]

[0098] 10 Voltage detection circuit 11 First comparator 12 Second Comparator 13 Voltage divider circuit 14 Voltage selection circuit 15 Multi-stage voltage divider circuit 16 Switch 30 Bias Circuit 31 Bias transistor 32 Resistance element 33 Diode Circuit 50 Bias power supply circuit 51 First voltage-current conversion circuit 52 First Decoder 53 Operational Amplifier 54 n-channel MOSFET 55 Resistance element 56 Switch 57 1st constant current source 58 First current mirror 60 Destruction Zone 70 Bias control circuit 71 Second voltage-current conversion circuit 72 Second Decoder 73 Operational Amplifiers 75 Resistance element 76 Switch 77 Second constant current source 78 Second current mirror 80 Differential current generation circuit 81 3rd operational amplifier 82 4th Op Amp 83 Transistor 84 Resistance element 85, 86 Switch 87 Transistors 90 Power Amplification Transistor 91 Choke coil 92 DC cut capacitor

Claims

1. a power amplifying transistor for amplifying the power of a high frequency signal; a voltage detection circuit that outputs a first detection signal indicating whether a power supply voltage applied to the power amplification transistor is equal to or higher than a first threshold and a second detection signal indicating whether a power supply voltage applied to the power amplification transistor is equal to or higher than a second threshold that is larger than the first threshold; a bias circuit for supplying a bias current to the power amplifier transistor; a bias power supply circuit for generating a bias power supply current to be supplied to the bias circuit; a bias control circuit for controlling the bias circuit; Equipped with the bias power supply circuit operates in one of a plurality of current generation modes for generating the bias power supply current having different levels; the plurality of current generation modes include a weak limit mode in which, when it is notified by the first detection signal that the power supply voltage is equal to or higher than the first threshold, the bias power supply current is reduced compared to when it is notified that the power supply voltage is lower than the first threshold; the bias circuit, under control of the bias control circuit, operates in one of an on mode in which the bias power supply current generated by the bias power supply circuit is supplied to the power amplification transistor as the bias current, and an off mode in which the level of the bias current is lowered from that in the on mode or the supply is stopped; The bias control circuit is capable of operating the bias circuit in the off mode when notified by the second detection signal that the power supply voltage is equal to or higher than the second threshold.

2. 2. The power amplifier according to claim 1, wherein the weak limit mode includes a constant limit mode in which the bias power supply current is reduced to a constant level lower than the level when the power supply voltage is notified to be less than the first threshold.

3. 3. The power amplifier device according to claim 1, wherein the weak limit mode includes a variable limit mode in which, as the power supply voltage increases, an amount of decrease in the level of the bias power supply current is increased relative to the level of the bias power supply current when it is notified that the power supply voltage is less than the first threshold.

4. The bias power supply circuit includes: a first decoder for decoding a first mode selection signal for selecting the current generation mode and the first detection signal; a first constant current source that changes the level of a current generated in response to an output from the first decoder; a first current mirror that outputs a current generated by the first constant current source as the bias power supply current; The power amplifier device according to claim 2 ,

5. The bias power supply circuit includes: a first decoder for decoding a first mode selection signal for selecting the current generation mode and the first detection signal; A first constant current source; a first current mirror that changes a magnification of the current generated by the first constant current source in response to an output from the first decoder and outputs the current as the bias power supply current; The power amplifier device according to claim 2 ,

6. The bias power supply circuit includes: a first decoder for decoding a first mode selection signal for selecting the current generation mode and the first detection signal; A first constant current source; a first current mirror that changes a magnification of the current generated by the first constant current source in response to an output from the first decoder and outputs the current as the bias power supply current; The power amplifier device according to claim 2 ,

7. The bias power supply circuit includes: a first decoder for decoding a first mode selection signal for selecting the current generation mode and the first detection signal; a current source that changes the level of a current generated in response to an output from the first decoder and a difference between the power supply voltage and the first threshold; a first current mirror that outputs the current generated by the current source as the bias power supply current; The power amplifier device according to claim 3 ,

8. 3. The power amplifier device according to claim 1, wherein the plurality of current generation modes further include an unlimited mode in which the bias power supply current is maintained at a fixed value regardless of a state of the first detection signal.

9. 3. The power amplifier device according to claim 1, wherein the plurality of current generation modes further include a strong limiting mode in which, when the first detection signal notifies that the power supply voltage is equal to or higher than the first threshold, a level of the bias power supply current is reduced to a level at which the power amplifier transistor does not perform an amplifying operation.

10. 3. The power amplifier device according to claim 1, wherein the bias control circuit can operate in a strong off mode in which the supply of the bias current to the power amplifier transistor is stopped when the bias circuit is operated in the off mode.

11. 3. The power amplifier device according to claim 1, wherein the bias control circuit can operate the bias circuit in a weak off mode in which the bias current, which has a reduced level of the bias power supply current, is supplied from the bias circuit to the power amplifier transistor when the bias circuit is operated in the off mode.

12. The voltage detection circuit includes: a first comparator that compares the power supply voltage with the first threshold value and outputs a comparison result as the first detection signal; a second comparator that compares the power supply voltage with the second threshold value and outputs a comparison result as the second detection signal; 3. The power amplifier device according to claim 1, further comprising:

13. the bias circuit includes a bias transistor that supplies the bias current to the power amplification transistor; 3. The power amplifier according to claim 1, wherein the emitter or source of the bias transistor is connected to the base or gate of the power amplifier transistor, the bias power supply current is supplied to the collector or drain of the bias transistor, and the control current of the bias transistor is controlled by the bias control circuit.

14. The bias control circuit includes: a second decoder for decoding a second mode selection signal for selecting the operation mode of the bias circuit and the second detection signal; a second constant current source that changes the level of the current it generates in response to an output from the second decoder; a second current mirror that supplies a current generated by the second constant current source to the bias circuit; 3. The power amplifier device according to claim 1, further comprising:

15. The bias control circuit includes: a second decoder for decoding a second mode selection signal for selecting the operation mode of the bias circuit and the second detection signal; A second constant current source; a second current mirror that changes a magnification of the current generated by the second constant current source in response to an output from the second decoder and supplies the current to the bias circuit; 3. The power amplifier device according to claim 1, further comprising:

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