Integrated circuit

Abstract

To provide an integrated circuit that realizes non-volatile characteristics using a vertically stacked gate-around-type transistor structure (GAA), such as the multi-bridge channel FET (MBCFET), which has high speed and low cost characteristics.SOLUTION: In a plurality of lateral FETs (GAA10, 11, 12) having the same conductivity type of the channel portion vertically stacked at the same position on the same plane, an insulating film capable of storing information in a nonvolatile manner is used as a gate insulating film in at least one element of the plurality of lateral FETs.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] This relates to an integrated circuit using gate-all-around transistors. [Background technology]

[0002] In the past, LSIs have progressed in accordance with Moore's Law as planar transistors have become increasingly miniaturized, and there has been steady progress in increasing capacity, reducing costs, increasing speed, and reducing power consumption.

[0003] As a result, MPUs, which are representative of logic LSIs, have achieved GHz operation using more than one billion planar transistors, and NAND flash memory, which uses planar transistors and is the memory LSI with the highest capacity, has been increased to 64 Gbit (Reference 1).

[0004] However, miniaturization of this planar transistor has been approaching its limit in recent years due to short channel effects and the like.

[0005] In order to solve the problem of the difficulty of miniaturizing planar transistors in the past, the gate-around transistor (hereafter abbreviated as GAA), which can use all four sides as a channel, and the MBCFET (Multi Bridge Channel FET), which is more suitable for high speed than GAA by stacking multiple GAA vertically, have been proposed. These have realized high speed and low cost characteristics without relying on miniaturization.

[0006] The previously proposed GAA or stacked GAA, which is stacked vertically, as typified by MBCFET, uses oxide or high-dielectric films as gate insulating films, and thus can achieve high speed and low cost characteristics. However, since GAA or stacked GAA alone cannot store nonvolatile information, it has not been possible to realize various memories and logic circuits using nonvolatile elements, such as nonvolatile memories, nonvolatile logic circuits that store output information of logic circuits on top of them, and product-sum circuits using nonvolatile elements. References 1M. Sako et al., “A Low-Power 64Gb MLC NAND-Flash Memory in 15nm CMOS Technology”, ISSCC Dig.Tech.Papers, 2015. Summary of the Invention Problem that the invention is trying to solve

[0007] A means for storing information in a non-volatile manner, and a non-volatile memory or non-volatile logic circuit using such a means, have not been proposed using a gate-around-type transistor structure (GAA) that can realize high speed and low cost, or a stacked GAA structure formed by stacking such a structure.

[0008] This is realized by stacking multiple lateral FETs vertically at the same position on the same plane, with the same conductivity type in the channel portion, and using an insulating film capable of storing information non-volatilely as the gate insulating film in at least one of the multiple lateral FETs.

[0009] This invention makes it possible to realize non-volatile characteristics in vertically stacked GAA, such as MBCFET, which has high speed and low cost characteristics. As a result, it is possible to realize various memories and logic circuits using non-volatile elements, such as non-volatile memories with small pattern area at low cost, non-volatile logic circuits that store output information of logic circuits at the top, and product-sum operation circuits using non-volatile elements with improved processing capabilities at low cost. BEST MODE FOR CARRYING OUT THEINVENTION

[0010] A first embodiment of an integrated circuit according to the present invention will now be described with reference to the drawings. [First embodiment] (Configuration of the first embodiment)

[0011] A first embodiment of the present invention will now be described. In Figure 1, ferroelectric transistors (FeFETs) are used as multiple lateral FETs with the same conductivity type of the channel part stacked vertically at the same position on the same plane. Figure 1 shows a stacked GAA with three GAAs stacked, and FeFETs are used for all three GAAs 10, 11, and 12.

[0012] Referring to FIG. 2, a second embodiment of the present invention will now be described. It is the same as the first embodiment in that it uses multiple lateral FETs with the same conductivity type of the channel part stacked vertically at the same position on the same plane. In Figure 2, one of the stacked GAAs, GAA20, which is made up of three stacked GAAs, uses an FeFET, and the remaining two GAAs use oxide films or high dielectric films as the gate insulating film.

[0013] A first modified example of the first embodiment of the present invention will now be described. Figure 3 shows a two-layer stacked GAA. FeFETs 30 and 31 form the first stacked GAA, and FeFETs 32 and 33 form the second stacked GAA. Within the same stacked GAA, the source electrodes of the stacked GAA are connected vertically as source lines 36 and 37 on the top and bottom, respectively. Similarly, within the same stacked GAA, the drain electrodes of the stacked GAA are connected vertically as bit lines 38 and 39 on the top and bottom, respectively. 34 and 35 respectively indicate the gate signal (word line) of the FeFET on the upper layer and the gate signal (word line) of the FeFET on the lower layer.

[0014] By increasing the number of vertically stacked layers and the number of stacked GAA, a large-capacity FeRAM with high speed and low cost can be realized. In Fig. 3, if 30 is a selected FeFET, 34 is a selected word line, 36 is a selected source line, and 38 is a selected bit line. On the other hand, 35 is an unselected word line, 37 is an unselected source line, and 39 is an unselected bit line.

[0015] When programming this large-capacity FeRAM, a high programming voltage VPP is applied to 34, and FeFET 30 is programmed with 36 and 38 at ground potential. To prevent erroneous writing to the remaining FeFETs, ground potential is applied to 35, and an intermediate voltage for non-selection (e.g., VPP / 2) is applied to 37 and 39. When reading, a low read voltage is applied to 34, and 36 is at ground potential, and the program information for 30 is read out to 38.

[0016] A second modification of the first embodiment of the present invention will now be described. FIG. 4 shows a case where two stacked GAA layers are stacked. FeFETs 40 and 41 form the first stacked GAA, and FeFETs 42 and 43 form the second stacked GAA. This configuration realizes a multiply-and-accumulate circuit using non-volatile elements. The source electrodes of the two stacked GAAs are used to program the FeFET in the upper layer and as input signals 461 and 462 to the multiply-and-accumulate operation. On the other hand, the source electrodes of the two stacked GAAs are used to program the FeFET in the lower layer and as input signals 471 and 472 to the multiply-and-accumulate operation. Bit lines 48 and 49 output the results of the multiply-and-accumulate operation in the different stacked GAA layers.

[0017] In Fig. 4, first, FeFETs 40-43 are programmed to store the weights in the product-sum operation as the resistance values ​​of each FeFET. When programming, for example, when programming FeFET 40, a program voltage corresponding to the weight value is applied to 44, and a ground voltage is applied to 461, 471, and 45. On the other hand, to prevent programming of FeFETs 42 and 43, an intermediate voltage is applied to 462 and 472.

[0018] Next, when performing a product-sum operation using the programmed information, the same input voltage is applied to the sources of the FeFETs in the same stacking location (in Figure 4, the same input voltage is applied to 461 and 462 in the upper layer, and the same input voltage is applied to 471 and 472 in the lower layer). The same gate voltage above the threshold voltage is applied to gate voltages 44 and 45. As a result, the calculation results of the product-sum operation circuits in each stacked GAA are output as current values ​​to bit lines 48 and 49. Another possible method is to make the gate voltages 44 and 45 common and separate the voltages of the bit lines 48 and 49 between the upper and lower GAA layers. In that case, different voltages are applied to the hit and source lines of the upper and lower GAA layers during programming (the source and drain voltages of the same FeFET are made the same) to control the amount of programming (change in threshold voltage) to the FeFET. When performing a multiplication and accumulation operation after programming, the bit lines connected to the upper and lower GAA layers are connected to evaluate the multiplication and accumulation operation.

[0019] A third modification of the first embodiment of the present invention will now be described. The basic configuration is a sum-of-products circuit having the same configuration as the first modified example of the first embodiment. The weights are programmed into the FeFET in the same way as in modified example 1 of the first embodiment. The feature of the sum-of-products operation is that, while in modified example 2 of the first embodiment, the input is made from the source, in modified example 3, the input is made from the gate. In other words, different input signals are applied to gates 34 and 35 during the sum-of-products operation. Normally, in the case of triode operation, the drain current of the FeFET is proportional to the value obtained by subtracting the programmed threshold voltage from the gate voltage. Therefore, it was thought that it would be difficult to control the weights and input voltages independently in the method of inputting the input signal to the gate voltage when the programmed threshold values ​​are different. (In the sum-of-products operation, the weights and input signals need to be controlled independently.)

[0020] Therefore, in the third modification, when the FeFET operates in subthreshold mode, the drain current is expressed as an exponential function of the gate voltage, threshold voltage, and drain voltage, so the drain current can be expressed as the product of the input voltage to the gate and the threshold value related to the weight. As a result, the weight and the input voltage to the gate can be controlled independently, which was a problem in the conventional method.

[0021] A fourth modified example of the first embodiment of the present invention will now be described (FIG. 5). The basic configuration is a multiplication and accumulation circuit having the same configuration as the first modification of the first embodiment. The weight programming to the FeFET is the same as the first modification of the first embodiment. The multiplication and accumulation is characterized in that, while the second modification of the first embodiment inputs from the source, the fourth modification inputs from the gate. In other words, different input signals are applied to the gates 34 and 35 during the multiplication and accumulation. Normally, in the case of triode operation, the drain current of the FeFET is proportional to the value obtained by subtracting the programmed threshold voltage from the gate voltage. Therefore, it was thought that it would be difficult to control the weight and input voltage independently using a method in which an input signal is input to the gate voltage when the programmed threshold values ​​are different.

[0022] Therefore, in the fourth modification, in addition to the evaluation FeFET, a new reference FeFET (constituting the FeFET array 51) is provided. The programmed threshold voltage of the evaluation FeFET is then similarly programmed into the reference FeFET. Then, during product-sum operations, the input signal to the gate is controlled according to the threshold voltage of the reference FeFET. Different gate input signals are input to gates 34 and 35. As a result, even when the drain current is in triode operation, it is always possible to express it in the form of a product of the input voltage to the gate and the weight.

[0023] To achieve the above operation, a circuit 52 that detects the threshold voltage of the reference FeFET and a conversion circuit 53 to a gate input signal according to the threshold voltage are required. The conversion circuit to a gate input signal can be a circuit that converts from the threshold voltage to a gate input signal by analytical calculation, or a table method that refers to the relationship between the two.

[0024] Referring to FIG. 6, a first modification of the second embodiment of the present invention will now be described. In Fig. 6, a non-volatile logic circuit can be realized that stores the output information of a logic circuit on its upper part. In a stacked type GAA, a FeFET 65 that stores the calculation result of 67 is stacked on top of a logic circuit 67 composed of GAA stacked vertically, and a GAA for writing control to the FeFET 63 is stacked on top of that. 63, 65, and 67 form a single stacked type GAA, but the only FeFET used in the stacking type GAA is the memory FeFET 65.

[0025] The circuit operates as follows. At the first precharge, 61 and 62 are set to a read voltage of 1V, and 66 is set to ground potential. Output 64 is precharged to 1V. At that time, 0V is applied to write word line 66. At the next read, precharge signal 62 is set to ground voltage, 66 is set to 2V, and the evaluation result of logic circuit 67 is output to output 64. At the next program, 61 and 62 are boosted to an intermediate voltage, and 64 is boosted to write voltage VP, and the evaluation result is written to FeFET 68.

[0026] When the output 64 is 1V during reading, the FeFET 68 is not programmed since the output 64 is charged to the intermediate potential during programming. On the other hand, when the output 64 is 0V during reading, the FeFET 68 is programmed since the output 64 is 0V during programming.

[0027] This invention makes it possible to realize non-volatile characteristics in vertically stacked GAA, such as MBCFET, which has high speed and low cost characteristics. As a result, it is possible to realize various memories and logic circuits using non-volatile elements, such as non-volatile memories with small pattern area at low cost, non-volatile logic circuits that store output information of logic circuits at the top, and product-sum operation circuits using non-volatile elements with improved processing capabilities at low cost.

[0028] When FeFETs are used as non-volatile elements, if 1K FeFETs are connected to one bit line, the area of ​​the memory cell array can be reduced to 1 / 1K by stacking FeFETs in the same position on a 1K layer in a stacked GAA. Since most of the area of ​​FeRAM is taken up by the memory cell array, this invention has the effect of reducing the area of ​​FeRAM to 1 / 1K of the conventional area. As a result, cost reduction can be expected.

[0029] When applied to a product-sum operation circuit using the nonvolatile element of the present invention, in the case where 1K FeFETs are connected to one bit line, the area of ​​the product-sum operation circuit can be reduced to 1 / 1K by using a stacked GAA in which the FeFETs are stacked at the same position in 1K layers. As a result, the area of ​​the product-sum operation circuit can be reduced to 1 / 1K without changing the processing capacity, which leads to cost reduction. Alternatively, in the case where the pattern area of ​​the product-sum operation circuit is not changed, the present invention can handle 1K times the input of the conventional circuit, and has the effect of realizing a product-sum operation circuit with higher performance than the conventional circuit. Other Examples Industrial Applicability

[0030] The present invention is not limited to this embodiment. Spin transistors, PCMs, etc. can also be used as non-volatile elements. It can also be applied to AI-related core circuits involved in the generation of activation functions other than product-sum operations, and the generation of protocols such as CNN and RNN. As a result, it can be applied to all currently commercialized integrated circuits such as system LSIs, logic LSIs, AI-specific LSIs, and FPGAs. [Brief description of the drawings]

[0031] [Figure 1] 1 is a circuit diagram seen from a cross-sectional direction of a first embodiment of a stacked GAA in which an insulating film capable of storing information non-volatilely is used as a gate insulating film of an integrated circuit according to the present invention. [Diagram 2] FIG. 11 is a circuit diagram seen from a cross-sectional direction of a second embodiment of a stacked GAA in which an insulating film capable of storing information non-volatilely is used as the gate insulating film of an integrated circuit according to the present invention. [Diagram 3]FIG. 1 is a circuit diagram seen from a cross-sectional direction of a first modified example of a first embodiment of a stacked GAA in which an insulating film capable of storing information non-volatilely is used as a gate insulating film of an integrated circuit according to the present invention. [Figure 4] FIG. 11 is a circuit diagram seen from the cross-sectional direction of a second modified example of the first embodiment of the stacked GAA in which an insulating film capable of storing information non-volatilely is used as the gate insulating film of an integrated circuit according to the present invention. [Diagram 5] FIG. 11 is a circuit diagram seen from the cross-sectional direction of a fourth modified example of the first embodiment of the stacked GAA in which an insulating film capable of storing information non-volatilely is used as the gate insulating film of the integrated circuit according to the present invention. [Figure 6] FIG. 11 is a circuit diagram seen from a cross-sectional direction of a first modified example of a second embodiment of a stacked GAA in which an insulating film capable of storing information non-volatilely is used as a gate insulating film of an integrated circuit according to the present invention. [Explanation of symbols]

[0031] 10-12 show three-layer stacked FeFETs, 20 shows a FeFET in a stacked GAA, and 21 and 22 show GAA using a normal gate oxide film. Reference numerals 30-39 denote symbols of a first modified example of embodiment 1. Reference numerals 30-33 denote FeFETs, 34 and 35 denote gate input signals, 36 and 37 denote source lines, and 38 and 38 denote bit lines. 40-45, 461, 462, 471, 472, 48, and 49 denote symbols of the second modified example of the embodiment 1. 40-43 denote FeFETs, 44 and 45 denote gate input signals, 461, 462, 471, and 472 denote source lines, and 48 and 48 denote bit lines. 30-39, 51, 52, and 53 are symbols of the fourth modified example of the first embodiment. 30-33 are FeFETs, 34 and 35 are gate input signals, 36 and 37 are source lines, and 38 and 38 are bit lines. 51 is a reference FeFET array, 52 is a threshold detection circuit for the FeFET, and 53 is a circuit for converting threshold voltages into gate signals. Reference numerals 61-68 denote symbols of a first modified example of embodiment 2. Reference numeral 68 denotes a memory FeFET, 63 denotes a precharge GAA, 61 denotes a write power supply, 62 denotes a write signal, 64 denotes an output, 66 denotes a gate signal of the FeFET, and 67 denotes a logic circuit.

Claims

1. An integrated circuit that realizes a nonvolatile function by using an insulating film that can store information in a nonvolatile manner as the gate insulating film of at least one element of a plurality of lateral FETs having the same conductivity type in their channel portions that are vertically stacked at the same position on the same plane.

2. 2. The integrated circuit according to claim 1, wherein the lateral FET is a gate-around type FET using four sides as a channel.

3. 3. The integrated circuit according to claim 1, wherein the nonvolatile function is realized as a nonvolatile memory.

4. 3. The integrated circuit according to claim 1, wherein the non-volatile function is a product-sum operation circuit.

5. 3. An integrated circuit according to claim 1, further comprising, as said non-volatile function, a function for storing the result of operation of any logic circuit.

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