Node and reservoir element

Abstract

To provide a node and a reservoir element excellent in short-term storage performance.SOLUTION: The node comprises a first input terminal, a second input terminal, a first signal holding circuit, and a first output terminal. The first input terminal is configured to be connectable to an input source transmitting an input signal to a reservoir element. The second input terminal is configured to be connectable to at least one or more other nodes. A first terminal of the first signal holding circuit is connected to the first input terminal and the second input terminal. A second terminal of the first signal holding circuit is connected to the first output terminal. The first output terminal is configured to be connectable to the at least one or more other nodes. The first signal holding circuit holds and converts a confluent signal obtained by joining the input signal and a propagation signal from the second input terminal.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to node and reservoir elements. [Background technology]

[0002] A neuromorphic device is an element that mimics the human brain using a neural network. A neuromorphic device artificially mimics the relationship between neurons and synapses in the human brain.

[0003] A neuromorphic device, for example, has chips (neurons in the brain) arranged in a hierarchy and a means of communication (synapses in the brain) that connects them. Neuromorphic devices increase the rate of correct answers to questions by having the means of communication (synapses) learn. Learning is the process of finding knowledge that can be used in the future from information, and neuromorphic devices weight the input data.

[0004] Recurrent neural networks are known as one type of neural network. Recurrent neural networks can handle nonlinear time series data. Nonlinear time series data is data whose values ​​change over time, such as stock prices. Recurrent neural networks can process time series data by feeding the results of processing in neurons in later layers back to neurons in earlier layers.

[0005] Reservoir computing is one of the means to realize a recurrent neural network. Reservoir computing performs recursive processing by interacting signals based on internal connections. In recent years, for example, as described in Non-Patent Document 1, attempts have been made to realize the concept of reservoir computing with actual elements. An element to which the concept of reservoir computing is applied is called a physical reservoir element or a reservoir element. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] K. Toprasertpong, E. Nako, Z. Wang, R. Nakane, M. Takenaka, and S. Takagi, “Reservoir computing on a silicon platform with a ferroelectric field-effect transistor”, Communications Engineering, 1, 21, August 2022. (DOI: 10.1038 / s44172-022-00021-8). Summary of the Invention [Problem to be solved by the invention]

[0007] One of the performance requirements for a reservoir element is short-term memory performance. Short-term memory performance is a measure of how much past information can be remembered and forgotten. In general, a reservoir element with optimal short-term memory performance for a given task outputs an estimated solution by taking into account the necessary data from the time series data up to the present, while ignoring past data that is older than necessary. However, when trying to realize a reservoir element using electronic circuits or physical elements, it is difficult to ensure sufficient short-term memory performance. As a result, a reservoir element with poor short-term memory performance outputs an estimated solution using only the data immediately preceding the time series data, resulting in insufficient performance.

[0008] The present invention has been made in consideration of the above circumstances, and provides a node and reservoir element having excellent short-term memory performance. [Means for solving the problem]

[0009] (1) A node according to a first aspect includes a first input terminal, a second input terminal, a first signal holding circuit, and a first output terminal. The first input terminal is configured to be connectable to an input source that transmits an input signal to a reservoir element. The second input terminal is configured to be connectable to at least one other node. A first terminal of the first signal holding circuit is connected to the first input terminal and the second input terminal. A second terminal of the first signal holding circuit is connected to the first output terminal. The first output terminal is configured to be connectable to at least one other node. The first signal holding circuit holds and converts a combined signal obtained by combining the input signal and a propagation signal from the second input terminal.

[0010] (2) In the node according to the above aspect, the first signal holding circuit may include a first switch, a second switch, a first capacitor, a second capacitor, and an amplifier circuit. The first switch is between the first terminal and the first capacitor. The first capacitor is between the first switch and the second switch. The second switch is between the first capacitor and the second capacitor. The second capacitor is between the second switch and the second terminal. The amplifier circuit is connected to the first capacitor and amplifies the potential of the first capacitor.

[0011] (3) In the node according to the above aspect, the first capacitor may be a variable capacitor whose capacitance is variable.

[0012] (4) In the node according to the above aspect, when the first switch is ON, the second switch is OFF, and when the second switch is ON, the first switch is OFF.

[0013] (5) In the node according to the above aspect, a first clock signal that controls ON and OFF of the first switch or a second clock signal that controls ON and OFF of the second switch may be variable.

[0014] (6) The node according to the above aspect may further include a second output terminal connected to the second terminal, the second output terminal being configured to be connectable to a leadout that outputs a signal to the outside of the reservoir element.

[0015] (7) The node according to the above aspect may further include a third switch between the second output terminal and the second terminal.

[0016] (8) The node according to the above aspect may further include a nonlinear circuit connected to the second terminal and the first output terminal.

[0017] (9) In the node according to the above aspect, the nonlinear circuit nonlinearly converts an input first signal into a second signal. The second signal and the first signal may satisfy a relational expression y≠ax+b, where y is the second signal, x is the first signal, and a and b are arbitrary values.

[0018] (10) In the node according to the above aspect, the second input terminal may be configured so as to be connectable to a plurality of nodes.

[0019] (11) In the node according to the above aspect, the first input terminal may be configured so as to be connectable to a plurality of nodes.

[0020] (12) A reservoir element according to a second aspect includes a plurality of nodes, at least one of which is the node according to the above aspect.

[0021] (13) In the reservoir element according to the above aspect, at least some of the plurality of nodes may be connected in a ring shape.

[0022] (14) In the reservoir element according to the above aspect, at least one of the plurality of nodes may include a third input terminal, a second signal holding circuit, and a third output terminal. The third input terminal is configured to be connectable to at least one other node. A first terminal of the second signal holding circuit is connected to the third input terminal. A second terminal of the second signal holding circuit is connected to the third output terminal. The third output terminal is configured to be connectable to at least one other node. The second signal holding circuit holds and converts a propagation signal from the third input terminal. Effect of the Invention

[0023] The node and reservoir elements according to the above aspects have excellent short-term memory performance. [Brief description of the drawings]

[0024] [Figure 1] FIG. 2 is a conceptual diagram of a neural network simulated by a reservoir element according to the first embodiment. [Diagram 2] 1 is a configuration diagram of an information processing device according to a first embodiment. [Diagram 3] FIG. 2 is a configuration diagram of another example of the information processing device according to the first embodiment. [Figure 4] FIG. 2 is a configuration diagram of a reservoir element according to the first embodiment. [Diagram 5] FIG. 2 is a circuit diagram of a node according to the first embodiment. [Figure 6] 5A and 5B are diagrams for explaining the operation of the signal holding circuit according to the first embodiment. [Figure 7] FIG. 4 is a diagram illustrating nonlinear characteristics of a node according to the first embodiment. [Figure 8] FIG. 11 is a plan view of a capacitor according to a first modified example. [Figure 9] FIG. 4 is a cross-sectional view of a capacitor according to a first modified example. [Figure 10] FIG. 13 is a circuit diagram of a signal holding circuit according to a second modified example. [Figure 11] FIG. 13 is a circuit diagram of a signal holding circuit according to a third modified example. [Figure 12] FIG. 13 is a circuit diagram of a signal holding circuit according to a fourth modified example. [Figure 13] FIG. 11 is a configuration diagram of a reservoir element according to a second embodiment. [Figure 14] FIG. 11 is a circuit diagram of a node according to a second embodiment. [Figure 15] FIG. 11 is a configuration diagram of a reservoir element according to a third embodiment. [Figure 16] FIG. 11 is a circuit diagram of a node according to a third embodiment. [Figure 17] FIG. 13 is a configuration diagram of a reservoir element according to a fourth embodiment. [Figure 18] FIG. 13 is a circuit diagram of a node according to a fourth embodiment. [Figure 19] FIG. 13 is a configuration diagram of a reservoir element according to a fifth embodiment. [Figure 20] FIG. 13 is a configuration diagram of a reservoir element according to a sixth embodiment. [Figure 21] FIG. 13 is a configuration diagram of a reservoir element according to a seventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] The present embodiment will be described in detail below with reference to the drawings as appropriate. The drawings used in the following description may show characteristic parts in an enlarged scale for the sake of convenience in order to make the features of the present invention easier to understand, and the dimensional ratios of each component may differ from the actual ones. The materials, dimensions, etc. exemplified in the following description are merely examples, and the present invention is not limited thereto. They may be modified as appropriate within the scope of the effects of the present invention.

[0026] "First embodiment" The reservoir element according to this embodiment is a device that implements processing in reservoir computing, which is an example of a recurrent neural network.

[0027] FIG. 1 is a conceptual diagram of a neural network simulated by a reservoir element according to the first embodiment. The neural network NN shown in FIG. 1 is a conceptual schematic diagram of reservoir computing. The neural network NN shown in FIG. 1 has an input layer L in and the reservoir layer R and the output layer L out The input layer L in and the output layer L out is connected to the reservoir layer R.

[0028] input layer L in is the input signal S in is input to the reservoir layer R. The input signal S in is, for example, a signal detected by a sensor. in The input signal S may be an analog or digital signal. in may be composed of a plurality of signals. Also, resistors or the like may be connected in series to each input signal as different weights.

[0029] The reservoir layer R is a in The reservoir layer R stores the input signal input from the node n and converts it into another signal. In the reservoir layer R, the connection weight between each node n takes a fixed value set by random numbers, etc., and generally the connection weight between each node n is not subject to learning. The reservoir layer R causes the input signal to change nonlinearly. The input signals change over time by interacting with each other in the reservoir layer R. The reservoir layer R has multiple nodes n. The nodes n correspond to neurons in a neural circuit, and the connections between the nodes n correspond to synapses. The multiple nodes n are connected randomly. For example, a signal output from one node n at time t may return to the node n that output the signal at time t+1. The node n performs processing based on the signals at time t and time t+1, and information is processed recursively.

[0030] Output layer L out is an output signal S based on a signal input from the reservoir layer R. out The output layer L outperforms the learning process and the inference process. In the learning process, the output layer L out The output from the reservoir layer R is compared with the training data D by the comparator C, and the node n of the reservoir layer R and the output layer L are compared. out The weight w applied between node n of the output layer L is adjusted. The weight w is determined during the learning process. out is the input signal S in The inference based on and weight w is output as the output signal S out The output is as follows:

[0031] 2 is a configuration diagram of an information processing device 200 according to the first embodiment. The information processing device 200 is hardware for operating a neural network NN.

[0032] The information processing device 200 includes, for example, a physical reservoir 201, a processor 202, a memory 203, and a communication device 204. The physical reservoir 201, the processor 202, the memory 203, and the communication device 204 are connected to each other via a bus 205.

[0033] The physical reservoir 201 is a physical element that performs the processing of the above-mentioned neural network NN. The processor 202 executes a program stored in the memory 203. The memory 203 has a program storage area for storing the program and an information storage area for storing information from the physical reservoir 201. The memory 203 is, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a hard disk drive (HDD), or a solid state drive (SSD). The physical reservoir 201 performs learning processing or inference processing based on an instruction from the processor 202. The communication device 204 outputs a signal to the outside of the information processing device 200. The communication device 204 may be wired or wireless.

[0034] The information processing device 200 is an example of the information processing device according to the first embodiment, and the information processing device is not limited to this example. For example, Fig. 3 is a configuration diagram of another example of the information processing device according to the first embodiment. As in the information processing device 200A shown in Fig. 3, the physical reservoir 201, the processor 202, the memory 203, and the communication device 204 may be connected to each other without the bus 205.

[0035] 4 is a configuration diagram of the reservoir element 100 according to the first embodiment. The reservoir element 100 is an example of a physical reservoir 201, and a circuit thereof performs processing of a neural network NN.

[0036] The reservoir element 100 includes a reservoir 1, an input section 2, and a readout 3. The input section 2 is shown in FIG. in Reservoir 1 corresponds to reservoir layer R in FIG. 1. Readout 3 corresponds to output layer L in FIG. out The input unit 2 includes, for example, a plurality of sensors and an analog-to-digital converter. The readout 3 includes, for example, a product-sum circuit, a comparison circuit, and an output circuit.

[0037] The reservoir 1 has a plurality of nodes 10. At least one of the nodes included in the reservoir 1 is a node 10 described later. The number of nodes 10 included in the reservoir 1 is not limited. Each of the nodes 10 has, for example, a first input terminal 11, a second input terminal 12, a first output terminal 13, and a second output terminal 14. Different nodes 10 are connected to each other by wiring that connects the second input terminal 12 and the first output terminal 13. In the example shown in FIG. 4, the plurality of nodes 10 are connected in a ring shape by wiring that connects the second input terminal 12 and the first output terminal 13. The connection between the nodes 10 shown in FIG. 4 is an example, and the connection between the nodes 10 and the arrangement of the nodes 10 are not limited to this.

[0038] 5 is a circuit diagram of a node 10 according to the first embodiment. The node 10 has, for example, a first input terminal 11, a second input terminal 12, a first output terminal 13, a second output terminal 14, a signal holding circuit 20, an output circuit 40, and a nonlinear circuit 50. The node 10 may also have resistors, amplifiers, etc. The signal holding circuit 20 is an example of a first signal holding circuit in the claims.

[0039] The first input terminal 11 is connected to, for example, the input section 2. The input section 2 receives an input signal S in The first input terminal 11 is connected to an input source that transmits an input signal S to the reservoir element 100 via the input section 2. The input source is, for example, a sensor. in The first input terminal 11 is configured to be connected to an input source that transmits an input signal S in is entered.

[0040] The second input terminal 12 is configured to be connectable to at least one other node 10. The second input terminal 12 is connected to, for example, a first output terminal 13 of the other node 10. The second input terminal 12 receives a propagation signal P in is entered.

[0041] The signal hold circuit 20 has a first terminal 21, a second terminal 22, a first switch 23, a second switch 24, a first capacitor 25, a second capacitor 26, an amplifier 27, and an inverter 28.

[0042] The first terminal 21 is a signal input terminal of the signal hold circuit 20. The first terminal 21 is connected to the first input terminal 11 and the second input terminal 12. The first terminal 21 receives an input signal S in and the propagating signal P in A combined signal of the above is input.

[0043] The second terminal 22 is a signal output terminal of the signal holding circuit 20. The second terminal 22 is connected to the first output terminal 13. An element (e.g., a resistor) or a circuit (e.g., a nonlinear circuit 50) may be present between the second terminal 22 and the first output terminal 13, as shown in Fig. 5. The second terminal 22 outputs a signal converted by the signal holding circuit 20.

[0044] The first switch 23 is between the first terminal 21 and the first capacitor 25. The second switch 24 is between the second terminal 22 and the first capacitor 25. The second switch 24 is, for example, between the first capacitor 25 and the second capacitor 26. A known switch may be used for the first switch 23 and the second switch 24, for example, a MOSFET. The first switch 23 operates with a first clock signal CLK1, and the second switch 24 operates with a second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 are input from the processor 202.

[0045] 5, the second clock signal CLK2 is the first clock signal CLK1 inverted by the inverter 28. Therefore, when the first switch 23 is ON, the second switch 24 is OFF, and when the second switch 24 is ON, the first switch 23 is OFF.

[0046] The first capacitor 25 is located between the first switch 23 and the second switch 24. One electrode of the first capacitor 25 is connected to a wiring that connects the first switch 23 and the amplifier 27, and the other electrode of the first capacitor 25 is grounded. The first capacitor 25 accumulates electric charge when the first switch 23 is ON and the second switch 24 is OFF, and discharges electric charge when the first switch 23 is OFF and the second switch 24 is ON. The amplifier 27 is connected to the first capacitor 25. The amplifier 27 amplifies the potential of the first capacitor 25.

[0047] The signal holding circuit 20 receives the input signal S in and the propagating signal P in A merging signal S m6 is a diagram for explaining the operation of the signal holding circuit 20 according to the first embodiment. When the first switch 23 is ON and the second switch 24 is OFF, the merged signal S m The first capacitor 25 receives the combined signal S m That is, the merged signal is held for a certain period of time in the first capacitor 25. Next, when the first switch 23 is turned OFF and the second switch 24 is turned ON, the charge stored in the first capacitor 25 is discharged. At this time, the merged signal S m is nonlinearly transformed to the transformed signal S c The converted signal S c is amplified by the amplifier 27 and output from the second terminal 22. The signal holding circuit 20 holds the combined signal S m Since the first capacitor 25 holds the combined signal S for a certain period of time, the short-term memory performance of the reservoir element 100 is improved. m Convert the signal S c 6, the first clock signal CLK1 and the second clock signal CLK2 are illustrated as having different duty ratios, but the duty ratio between the first clock signal CLK1 and the second clock signal CLK2 may be 50:50.

[0048] The second capacitor 26 is disposed in front of the second terminal 22. The second capacitor 26 is connected to, for example, the second switch 24 and the second terminal 22. One electrode of the second capacitor 26 is connected to a wiring leading to the second terminal 22, and the other electrode of the second capacitor 26 is grounded. A nonlinear circuit 50 may be provided between the second terminal 22 and the first output terminal 13. The second capacitor 26 accumulates a part of the signal output from the second terminal 22, thereby contributing to improving short-term memory performance. The second capacitor 26 is not essential and may be removed.

[0049] The output circuit 40 is connected to the second terminal 22 and the second output terminal 14. The second output terminal 14 is configured to be connectable to, for example, the lead-out 3. In the reservoir element 100, the second output terminal 14 is connected to the lead-out 3. The lead-out 3 outputs a signal to the outside of the reservoir element 100. The second output terminal 14 outputs an output signal S out will be output.

[0050] The output circuit 40 includes, for example, a third switch 41 and an amplifier 42. The amplifier 42 amplifies the signal input to the output circuit 40. The third switch 41 switches the connection between the second terminal 22 and the second output terminal 14. When the third switch 41 is ON, the output signal S out When the third switch 41 is OFF, the output signal S is output from the second output terminal 14 to the readout 3. out In this case, the node 10 is responsible for signal interaction between the node 10 connected to the second input terminal 12 and the node 10 connected to the first output terminal 13.

[0051] The nonlinear circuit 50 is connected to the second terminal 22 and the first output terminal 13. The nonlinear circuit 50 is, for example, a horizontal resistor circuit. The nonlinear circuit 50 nonlinearly converts the first signal S1 into a second signal S2 and outputs the second signal S2. The second signal S2 and the first signal S1 satisfy, for example, a relational expression y≠ax+b. In this relational expression, y is the second signal S2, x is the first signal S1, and a and b are arbitrary values. The first signal S1 is a signal input from the signal holding circuit 20.

[0052] The nonlinear circuit 50 enhances the nonlinear characteristics of the reservoir element 100. The reservoir 1 receives an input signal S in into a nonlinear space, and the higher the nonlinearity of the signal transformation of the reservoir 1, the higher the expressiveness of the reservoir element 100. Even if the node 10 does not have the nonlinear circuit 50, the nonlinear transformation occurs in the signal holding circuit 20, so the nonlinear circuit 50 is not essential in the node 10. However, if the node 10 has the nonlinear circuit 50, the reservoir element 100 can process more complex signals.

[0053] The first output terminal 13 is configured to be connectable to at least one other node 10. The first output terminal 13 is connected to, for example, the second input terminal 12 of the other node 10. A propagation signal P out The input signal S inputted from the first input terminal 11 is outputted. in and a propagation signal P input from the second input terminal 12. in is transformed while propagating through node 10, resulting in a propagating signal P out become.

[0054] In the reservoir element 100 according to the first embodiment, a plurality of nodes 10 are connected to each other, and signals between the nodes 10 are nonlinearly converted and interact with each other. FIG. 7 is a graph showing the measurement of the nonlinear conversion characteristic of the reservoir element 100 according to the first embodiment. The horizontal axis of FIG. 7 represents the propagation signal P in The voltage V in The vertical axis of FIG. 7 represents the propagation signal P out The voltage V out The change in the propagation signal P in The voltage V in is divided by the change in width per unit time, and the propagation signal P out The voltage V out As shown in FIG. 7, the propagation signal P out is the propagating signal P in It was confirmed that the reservoir element 100 performs nonlinear transformation of the neural network NN. The reservoir element 100 implements the mechanism of the neural network NN as a physical circuit (hardware) rather than as software.

[0055] In addition, the reservoir element 100 according to the first embodiment receives an input signal S from the input section 2 at each of the multiple nodes 10. in is input, and this input signal S in This input signal S is held for a certain period of time in the signal holding circuit 20. inThe fact that the signal holding circuit 20 is held for a certain period of time leads to the holding of past information in the reservoir element 100. In other words, the reservoir element 100 according to the first embodiment has excellent short-term memory performance. The short-term memory performance of the reservoir element 100 using the node 10 shown in FIG. 5 was 60. In contrast, the short-term memory performance of the reservoir element using the node 10 shown in FIG. 5 without the signal holding circuit 20 was 15. It can be confirmed that the short-term memory performance of the reservoir element 100 is improved by the node 10 having the signal holding circuit 20.

[0056] Although an example of the reservoir element 100 according to the first embodiment has been described in detail so far, the reservoir element according to the first embodiment can be modified and changed in various ways within the scope of the gist of the present invention.

[0057] For example, the first capacitor 25 shown in Fig. 5 is a capacitor having a fixed capacitance, but the first capacitor 25 may be a variable capacitor whose capacitance is variable. The second capacitor 26 may also be a variable capacitor whose capacitance is variable. The first capacitor 25 will be exemplified below.

[0058] Fig. 8 is a plan view of the first capacitor according to the first modification. Fig. 9 is a cross-sectional view of the first capacitor according to the first modification. The first capacitor 25 has a first conductive layer 25A, a second conductive layer 25B, a capacitance layer 25C, a first electrode 25D, a second electrode 25E, and a third electrode 25F. The conductance of the first capacitor 25 changes with a change in magnetization of the first conductive layer 25A and the second conductive layer 25B that sandwich the capacitance layer 25C. The periphery of the first capacitor 25 is covered with, for example, an insulating layer 25G.

[0059] The first conductive layer 25A is a ferromagnetic layer including a ferromagnetic material. The first conductive layer 25A may be a ferromagnetic layer made of a ferromagnetic material.

[0060] The ferromagnetic material may be, for example, a metal selected from the group consisting of Cr, Mn, Co, Fe, and Ni, an alloy containing one or more of these metals, or an alloy containing these metals and at least one of the elements B, C, and N. The ferromagnetic material may include, for example, any one selected from the group consisting of a CoPt alloy, a CoNi alloy, a TbFeCo alloy, a CoFe alloy, and alloys in which a part of these alloys is substituted. For example, the ferromagnetic material is Co-Fe, Co-Fe-B, or Ni-Fe.

[0061] The ferromagnetic material may be, for example, a Heusler alloy. Heusler alloys are half-metallic and have high spin polarizability. Heusler alloys are intermetallic compounds having a chemical composition of XYZ or X2YZ, where X is a transition metal element or a noble metal element of the Co, Fe, Ni, or Cu group on the periodic table, Y is a transition metal element or an element type of X of the Mn, V, Cr, or Ti group, and Z is a typical element of groups III to V. Examples of Heusler alloys include Co2FeSi, Co2FeGe, Co2FeGa, Co2MnSi, and Co2Mn 1-a Fe a Al b S 1-b , Co2FeGe 1-c Ga c etc.

[0062] The first conductive layer 25A has a first magnetic domain A1 and a second magnetic domain A2. A domain wall DW exists at the boundary between the first magnetic domain A1 and the second magnetic domain A2.

[0063] The domain wall DW is configured so as to be able to move in a first direction within the plane of the first conductive layer 25A at least in the region of the first conductive layer 25A that overlaps with the capacitance layer 25C in the stacking direction. For example, the domain wall DW is configured so as to be able to move in the x direction within the first conductive layer 25A. The x direction is one direction within the plane in which each layer extends. The y direction is a direction perpendicular to the x direction within the plane in which each layer extends. The z direction is a direction perpendicular to the x and y directions.

[0064] The domain wall DW moves in the x direction by changing the potential difference between the first electrode 25D and the second electrode 25E. The domain wall DW moves, for example, by applying a write current (for example, a current pulse) in the x direction of the first conductive layer 25A, applying an external magnetic field to the first conductive layer 25A, or the like. For example, when a write pulse is applied between the first electrode 25D and the second electrode 25E, the domain wall DW moves.

[0065] The first magnetic domain A1 has a first region A11 and a second region A12. The magnetizations in the first magnetic domain A1 are oriented in the same direction. The magnetization M of the first region A11 A11 and the magnetization M of the second region A12 A12 are oriented in the same direction.

[0066] The first region A11 is a region that overlaps with the first electrode 25D when viewed from the z direction, and has a magnetization M A11 The first region A11 is a region in which the magnetization is fixed. The magnetization being fixed means that the magnetization does not reverse during normal operation of the first capacitor 25 (when no external force exceeding the expected value is applied). The first region A11 is called a first magnetization fixed region.

[0067] The second region A12 is a region other than the first region A11 in the first magnetic domain A1. The volume of the second region A12 changes as the domain wall DW moves.

[0068] The second magnetic domain A2 has a third region A21 and a fourth region A22. The magnetizations in the second magnetic domain A2 are oriented in the same direction. The magnetizations in the second magnetic domain A2 are oriented in a different direction from the magnetizations in the first magnetic domain A1. The magnetization M of the third region A21 A21 and the magnetization M of the fourth region A22 A22 are oriented in the same direction.

[0069] The third region A21 is a region that overlaps with the second electrode 25E when viewed from the z direction, and has a magnetization M A21 The third region A21 is called a second magnetization fixed region.

[0070] The fourth region A22 is a region other than the third region A21 in the second magnetic domain A2. The volume of the fourth region A22 changes as the domain wall DW moves.

[0071] The second region A12 and the fourth region A22 are collectively referred to as a domain wall motion region. The domain wall motion region is sandwiched between the first magnetization fixed region and the second magnetization fixed region.

[0072] The second conductive layer 25B is in contact with the capacitance layer 25C. The first conductive layer 25A and the second conductive layer 25B sandwich the capacitance layer 25C.

[0073] The second conductive layer 25B is a ferromagnetic layer including a ferromagnetic material. The second conductive layer 25B may be a ferromagnetic layer made of a ferromagnetic material. The second conductive layer 25B may be made of the same material as the material constituting the first conductive layer 25A. The material constituting the second conductive layer 25B and the material constituting the first conductive layer 25A may be the same or different. The magnetization M of the second conductive layer 25B 25B The magnetization of the first conductive layer 25A is more difficult to reverse than that of the second conductive layer 25B.

[0074] The capacitance layer 25C is sandwiched between the first conductive layer 25A and the second conductive layer 25B. The capacitance layer 25C is a dielectric layer. The capacitance layer 25C has insulating properties, and electric charges are stored in the first conductive layer 25A and the second conductive layer 25B that sandwich the capacitance layer 25C.

[0075] The capacitance layer 25C includes, for example, any one selected from the group consisting of magnesium oxide (MgO), aluminum oxide (Al2O3), titanium oxide (TiO2), barium titanate (BaTiO3), magnesium aluminate (MgAl2O4), silicon oxide (SiO2), magnesium titanate (MgTiO3), and hafnium oxide (HfO2). The composition ratio of each element in these oxides is not limited to the stoichiometric composition. When the capacitance layer 25C includes these materials, the change range of the capacitance of the first capacitor 25 becomes large.

[0076] The capacitance layer 25C may contain, for example, aluminum nitride (AlN) or aluminum nitride to which one selected from the group consisting of calcium, strontium, titanium, and potassium is added. When the capacitance layer 25C contains these materials, it has the effect of increasing the capacitance. Furthermore, when the capacitance layer 25C contains these materials, the electrical conductivity of the capacitance layer 25C is improved, and heat generation due to current flow can be suppressed. As a result, it is possible to suppress a large change in the temperature of the first capacitor 25 during use.

[0077] The capacitance layer 25C may include any one selected from the group consisting of lead titanate (PbTiO3), strontium titanate (SrTiO3), lead zirconate (PbZrO3), lead hafnate (PbHfO3), and relaxor ferroelectrics. When the capacitance layer 25C includes any one of these materials, the dielectric constant of the capacitance layer 25C increases, and the capacitance of the first capacitor 25 increases.

[0078] The first electrode 25D and the second electrode 25E are, for example, ferromagnetic layers. For example, the same material as the first conductive layer 25A and the second conductive layer 25B can be used for the first electrode 25D and the second electrode 25E. The third electrode 25F is in contact with the second conductive layer 25B. The third electrode 25F is a conductor.

[0079] The capacitance of first capacitor 25 changes by applying a potential difference between first electrode 25D and second electrode 25E and applying a write current (write pulse) to first conductive layer 25A. The capacitance of first capacitor 25 changes in an analog manner by applying an electric signal in one direction within the plane of first conductive layer 25A.

[0080] The write current (write pulse) moves the domain wall DW in the first conductive layer 25 A. The position of the domain wall DW changes depending on the magnitude of the write current (write pulse).

[0081] The capacitance of the first capacitor 25 is determined by the second conductive layer 25B and the magnetization M 25BThe larger the region in which the magnetization of the second conductive layer 25B and the magnetization M are antiparallel, the larger the magnetization of the second conductive layer 25B and the magnetization M 25B The capacitance of the first capacitor 25 decreases as the area in which the magnetization of the first conductive layer 25A and the magnetization of the first magnetic domain A1 are parallel expands. The capacitance of the first capacitor 25 increases as the first magnetic domain A1 expands, and the capacitance of the first capacitor 25 decreases as the second magnetic domain A2 expands. For example, the capacitance of the first capacitor 25 varies between 1 μF and 1 pF.

[0082] If the capacitance of the first capacitor 25 is variable, the short-term memory performance can be changed according to the task given to the reservoir element 100. For example, if taking into account older data in the time series data improves estimation accuracy, the capacitance of the first capacitor 25 can be increased to improve the short-term memory performance. The second capacitor 26 can also be selected to have the same configuration as the first capacitor 25.

[0083] Furthermore, the configuration of the signal hold circuit 20 is not limited to that shown in FIG.

[0084] 10 is a circuit diagram of a signal holding circuit 20A of a reservoir element according to a second modified example. The signal holding circuit 20A differs from the signal holding circuit 20 shown in FIG.

[0085] In the signal hold circuit 20A, a first clock signal CLK1 that controls ON / OFF of the first switch 23 and a second clock signal CLK2 that controls ON / OFF of the second switch 24 are input separately. The first clock signal CLK1 and the second clock signal CLK2 are each independently variable.

[0086] When the second clock signal CLK2 and the first clock signal CLK1 are controlled separately, the duty ratio of the first clock signal CLK1 and the second clock signal CLK2, the frequency of the first clock signal CLK1 and the second clock signal CLK2, etc. become variable. in and the propagating signal P in A merging signal S mThe retention time in the signal retention circuit 20A varies depending on the ON / OFF timing of the first switch 23 and the second switch 24. By adjusting the retention time and the timing of signal retention, the short-term memory performance of the reservoir element can be adjusted.

[0087] 11 is a circuit diagram of a signal holding circuit 20B of a reservoir element according to a third modified example. The signal holding circuit 20B differs from the signal holding circuit 20 shown in FIG. 5 in that it has an amplifier 29 between the first terminal 21 and the first switch 23.

[0088] The signal holding circuit 20B amplifies the combined signal input from the first terminal 21 using the amplifier 29. By amplifying the combined signal, the signal holding circuit 20B is able to perform signal analysis with higher accuracy.

[0089] 12 is a circuit diagram of a signal holding circuit 20C of a reservoir element according to a fourth modification. The signal holding circuit 20C differs from the signal holding circuit 20 shown in FIG. 5 in that a switch 30 is provided between the first switch 23 and the first capacitor 25. The switch 30 may be a known switch, for example, a MOSFET. When the switch 30 is turned ON, the charge stored in the first capacitor 25 is completely discharged. The signal holding circuit 20C can control the amount of charge remaining in the first capacitor 25 by turning the switch 30 ON and OFF.

[0090] The characteristic configurations of the first to fourth modified examples may be combined. For example, the first capacitor 25 according to the second to fourth modified examples may be a variable capacitor. For example, the signal holding circuit 20A of the first modified example may be provided with an amplifier 29 or a switch 30. For example, the signal holding circuit 20B of the second modified example may be provided with a switch 30.

[0091] "Second embodiment" 13 is a configuration diagram of a reservoir element 101 according to the second embodiment. The reservoir element 101 has a reservoir 4, an input section 2, and a readout 3. The reservoir 4 differs from the reservoir 1 according to the first embodiment in that some of the multiple nodes are nodes 10A. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals.

[0092] The reservoir 4 has a plurality of nodes 10 and at least one node 10A. Any node among the nodes constituting the reservoir 4 may be set as the node 10A. The number of nodes 10A may be one or more.

[0093] 14 is a circuit diagram of a node 10A according to the second embodiment. The node 10A has, for example, a first input terminal 11, a second input terminal 12, a first output terminal 13, a signal holding circuit 20, and a nonlinear circuit 50. The node 10A is different from the node 10 in that it does not have a second output terminal 14 and an output circuit 40. The node 10A is in the same state as when the third switch 41 of the output circuit 40 of the node 10 is turned off. The node 10A is responsible for signal interaction between the node 10 or the node 10A connected to the second input terminal 12 and the node 10 or the node 10A connected to the first output terminal 13.

[0094] The reservoir element 101 according to the second embodiment realizes a neural network using a physical circuit, similar to the reservoir element 100 according to the first embodiment. Each of the nodes 10 and 10A has a signal retention circuit 20, and therefore has excellent short-term memory performance. The reservoir element 101 according to the second embodiment can also be modified in the same manner as the first embodiment.

[0095] "Third embodiment" 15 is a configuration diagram of a reservoir element 102 according to the third embodiment. The reservoir element 102 has a reservoir 5, an input section 2, and a readout 3. The reservoir 5 differs from the reservoir 1 according to the first embodiment in that some of the multiple nodes are nodes 10B. In the third embodiment, the same components as those in the first embodiment are denoted by the same reference numerals.

[0096] The reservoir 5 has a plurality of nodes 10 and at least one node 10B. Any node among the nodes constituting the reservoir 5 may be set as the node 10B. The number of the nodes 10B may be one or more.

[0097] Fig. 16 is a circuit diagram of a node 10B according to the third embodiment. The node 10B has, for example, a second input terminal 12, a first output terminal 13, a second output terminal 14, an output circuit 40, a signal holding circuit 60, and a nonlinear circuit 50. The node 10B differs from the node 10 in that it does not have a first input terminal 11. The second input terminal 12 in Fig. 16 is an example of a third input terminal in the claims, the first output terminal 13 in Fig. 16 is an example of a third output terminal in the claims, and the signal holding circuit 60 is an example of a second signal holding circuit in the claims.

[0098] The signal holding circuit 60 has a similar configuration to the signal holding circuit 20. The signal holding circuit 60 has a first terminal 21, a second terminal 22, a first switch 23, a second switch 24, a first capacitor 25, a second capacitor 26, an amplifier 27, and an inverter 28. The signal holding circuit 60 can be modified in the same manner as the signal holding circuit 20. The first terminal 21 of the signal holding circuit 60 is connected to the second input terminal 12. The first terminal 21 is connected to the second input terminal 12. in is entered.

[0099] The signal holding circuit 60 holds the propagating signal P in When the first switch 23 is ON and the second switch 24 is OFF, the propagation signal P in is held for a certain period of time in the first capacitor 25. Next, when the first switch 23 is turned OFF and the second switch 24 is turned ON, the charge stored in the first capacitor 25 is discharged. At this time, the propagation signal P in The converted signal is amplified by the amplifier 27 and output from the second terminal 22.

[0100] The reservoir element 102 according to the third embodiment realizes a neural network using a physical circuit, similar to the reservoir element 100 according to the first embodiment. Each of the nodes 10 and 10B has a signal holding circuit 20 or a signal holding circuit 60, and therefore has excellent short-term memory performance. The reservoir element 102 according to the third embodiment can be modified in the same manner as the first embodiment.

[0101] "Fourth embodiment" 17 is a configuration diagram of a reservoir element 103 according to the fourth embodiment. The reservoir element 103 has a reservoir 6, an input section 2, and a readout 3. The reservoir 6 differs from the reservoir 1 according to the first embodiment in that some of the multiple nodes are node 10A, node 10B, and node 10C. In the fourth embodiment, the same components as those in the first embodiment are denoted by the same reference numerals.

[0102] The reservoir 4 has a plurality of nodes 10, including at least one node 10A, at least one node 10B, and at least one node 10C. It is arbitrary which of the nodes constituting the reservoir 6 is the node 10A, the node 10B, or the node 10C. The number of each of the nodes 10A, 10B, and 10C may be one or more.

[0103] FIG. 18 is a circuit diagram of a node 10C according to the fourth embodiment. The node 10C has, for example, a second input terminal 12, a first output terminal 13, a signal holding circuit 60, and a nonlinear circuit 50. The node 10C is different from the node 10 in that it does not have a first input terminal 11, a second output terminal 14, or an output circuit 40. The signal holding circuit 60 is the same as that of the third embodiment. The node 10C is responsible for signal interaction between any one of the nodes 10, 10A, 10B, and 10C connected to the second input terminal 12 and any one of the nodes 10, 10B, and 10C connected to the first output terminal 13.

[0104] The reservoir element 103 according to the fourth embodiment realizes a neural network by a physical circuit, similar to the reservoir element 100 according to the first embodiment. Each of the nodes 10, 10A, 10B, and 10C has a signal holding circuit 20 or a signal holding circuit 60, and therefore has excellent short-term memory performance. The reservoir element 103 according to the fourth embodiment can be modified in the same manner as the first embodiment.

[0105] "Fifth embodiment" 19 is a configuration diagram of a reservoir element 104 according to the fifth embodiment. The reservoir element 104 has a reservoir 7, an input section 2, and a readout 3. The reservoir 7 differs from the reservoir 1 according to the first embodiment in that a plurality of nodes 10 form a plurality of rings. In the fifth embodiment, the same components as those in the first embodiment are denoted by the same reference numerals.

[0106] The reservoir 7 has a first ring unit R1 and a second ring unit R2. In the first ring unit R1, the multiple nodes 10 are connected in a ring shape by wiring connecting the second input terminal 12 and the first output terminal 13. Similarly, in the second ring unit R2, the multiple nodes 10 are connected in a ring shape by wiring connecting the second input terminal 12 and the first output terminal 13. The number of nodes 10 constituting each of the first ring unit R1 and the second ring unit R2 is not important.

[0107] The input signal input to each node 10 of the first ring unit R1 and the input signal input to each node 10 of the second ring unit R2 may be the same or different. For example, when there are two types of input signals, the input signal S in and inputs a first input signal as an input signal S to the node 10 of the second ring unit R2. in Alternatively, the input signal S may be input to the nodes 10 of the first ring unit R1 and the second ring unit. in The first input signal and the second input signal may be input as the first input signal and the second input signal.

[0108] Furthermore, the configuration of each node 10 in the first ring unit R1 and the configuration of each node 10 in the second ring unit R2 may be the same or different. The configuration of the node 10 is, for example, the capacitance of a capacitor, the first clock signal CLK1 input to the first switch 23, the second clock signal CLK2 input to the second switch 24, etc. By changing the configuration of the node 10 between the first ring unit R1 and the second ring unit R2, features of different dimensions can be extracted from the same input signal.

[0109] The reservoir element 104 according to the fifth embodiment realizes a neural network using a physical circuit, similar to the reservoir element 100 according to the first embodiment, and has excellent short-term memory performance. In addition, the reservoir element 104 according to the fifth embodiment has a plurality of units in the reservoir 7, so that various feature quantities can be extracted.

[0110] In the reservoir element 104 according to the fifth embodiment, a part of the node 10 may be replaced with any one of the node 10A, the node 10B, and the node 10C. Moreover, the reservoir element 104 according to the fifth embodiment can be modified in the same manner as the first embodiment.

[0111] Sixth embodiment 20 is a configuration diagram of a reservoir element 105 according to the sixth embodiment. The reservoir element 105 has a reservoir 8, an input section 2, and a readout 3. The reservoir 8 differs from the reservoir 1 according to the first embodiment in that a plurality of nodes 10 form a plurality of rings. In the sixth embodiment, the same components as those in the first embodiment are denoted by the same reference numerals.

[0112] The reservoir 8 has a first ring unit R1' and a second ring unit R2'. In the first ring unit R1', the plurality of nodes 10 or the plurality of nodes 10D are connected in a ring shape by wiring connecting the second input terminal 12 and the first output terminal 13. Similarly, in the second ring unit R2', the plurality of nodes 10 or the plurality of nodes 10E are connected in a ring shape by wiring connecting the second input terminal 12 and the first output terminal 13. The number of the nodes 10, the nodes 10D, and the nodes 10E constituting each of the first ring unit R1' and the second ring unit R2' is not limited.

[0113] The node 10D has a similar configuration to the node 10. The node 10D differs from the node 10 in that the second output terminal 14 of the node 10D is configured so as to be connectable to the first input terminal 11 of another node 10E.

[0114] The node 10E has a similar configuration to the node 10. The node 10E differs from the node 10 in that the first input terminal 11 of the node 10E is configured so as to be connectable to a second output terminal 14 of another node 10D.

[0115] The first ring unit R1' and the second ring unit R2' are arranged in a hierarchical structure, with the first ring unit R1' handling the first half of the reservoir 8 and the second ring unit R2' handling the second half of the reservoir 8.

[0116] Furthermore, the configuration of each node 10 or node 10D in the first ring unit R1' may be the same as or different from the configuration of each node 10 or node 10E in the second ring unit R2'. By changing the node configuration between the first ring unit R1' and the second ring unit R2', the expressiveness of the reservoir 8 is increased, enabling more complex processing to be performed. The reservoir 8 can generate a feature space with higher expressiveness that is more suited to the target task.

[0117] The reservoir element 105 according to the sixth embodiment realizes a neural network using a physical circuit, similar to the reservoir element 100 according to the first embodiment, and has excellent short-term memory performance. In addition, the reservoir element 105 according to the sixth embodiment has a plurality of units in the reservoir 8, thereby enhancing the expressiveness of the reservoir 8.

[0118] In the reservoir element 105 according to the sixth embodiment, a part of the node 10, the node 10D, or the node 10E may be replaced with any of the node 10A, the node 10B, and the node 10C. The reservoir element 105 according to the sixth embodiment may have a plurality of ring units in parallel, similar to the fifth embodiment. The reservoir element 105 according to the sixth embodiment may be modified in the same manner as the first embodiment.

[0119] Seventh embodiment 21 is a configuration diagram of a reservoir element 106 according to the seventh embodiment. The reservoir element 106 has a reservoir 9, an input section 2, and a readout 3. The reservoir 9 differs from the reservoir 1 according to the first embodiment in that some of the multiple nodes 10 are connected to multiple other nodes 10. In the seventh embodiment, the same components as those in the first embodiment are denoted by the same reference numerals.

[0120] The reservoir 9 includes a plurality of nodes 10, at least one node 10F, and at least one node 10G. A first output terminal 13 of the node 10F is configured to be connectable to a plurality of the nodes 10. A second input terminal 12 of the node 10G is configured to be connectable to a plurality of the nodes 10. The configurations of the nodes 10F and 10G are similar to that of the node 10.

[0121] The reservoir element 106 according to the seventh embodiment realizes a neural network using physical circuits, and has excellent short-term memory performance, similar to the reservoir element 100 according to the first embodiment. Furthermore, the reservoir element 106 according to the seventh embodiment has more complex connections between the nodes 10, 10F, and 10G in the reservoir 9, and can further enhance the expressiveness of the reservoir 9.

[0122] In the reservoir element 106 according to the seventh embodiment, a part of the node 10 may be replaced with any one of the node 10A, the node 10B, and the node 10C. The reservoir element 106 according to the seventh embodiment may be modified in the same manner as the first embodiment. The reservoir element 106 according to the seventh embodiment may have a plurality of ring units in the reservoir 9. [Explanation of symbols]

[0123] 1,4,5,6,7,8,9…Reservoir 2. Input section 3...Lead out 10, 10A, 10B, 10C, 10D, 10E, 10F, 10G...node 11...First input terminal 12...Second input terminal 13…First output terminal 14…Second output terminal 20,20A,20B,20C,60…Signal holding circuit 21…1st terminal 22…Second terminal 23…First switch 24…Second switch 25…First capacitor 25A…first conductive layer 25B…Second conductive layer 25C…Capacitance layer 25D…1st electrode 25E…Second electrode 25F…3rd electrode 25G…insulating layer 26…Second capacitor 27, 29…Amplifier 28…Inverter 30…Switch 40...Output circuit 100, 101, 102, 103, 104, 105, 106...Reservoir elements 200...Information processing device 201…Physical Reservoir 202…Processor 203…Memory 204...Communication equipment 205…Bus CLK1: First clock signal CLK2: Second clock signal P in , P out … Propagation signal S in …Input signal S out …Output signal S1…1st signal S2…Second signal

Claims

1. a first input terminal, a second input terminal, a first signal holding circuit, and a first output terminal; the first input terminal is adapted to be connected to an input source for providing an input signal to the reservoir element; the second input terminal is configured to be connectable to at least one other node; a first terminal of the first signal holding circuit is connected to the first input terminal and the second input terminal; a second terminal of the first signal holding circuit is connected to the first output terminal; the first output terminal is configured to be connectable to at least one other node; The first signal holding circuit holds and converts a combined signal obtained by combining the input signal and a propagation signal from the second input terminal.

2. the first signal holding circuit includes a first switch, a second switch, a first capacitor, a second capacitor, and an amplifier circuit; the first switch is between the first terminal and the first capacitor; the first capacitor is between the first switch and the second switch; the second switch is between the first capacitor and the second capacitor; the second capacitor is between the second switch and the second terminal; The node according to claim 1 , wherein the amplifier circuit is connected to the first capacitor and amplifies a potential of the first capacitor.

3. The node according to claim 2 , wherein the first capacitor is a variable capacitor having a variable capacitance.

4. When the first switch is ON, the second switch is OFF; 3. The node of claim 2, wherein the first switch is OFF when the second switch is ON.

5. 3. The node according to claim 2, wherein a first clock signal that controls ON and OFF of the first switch or a second clock signal that controls ON and OFF of the second switch is variable.

6. a second output terminal connected to the second terminal; 2. The node of claim 1, wherein the second output terminal is adapted to be connected to a lead-out for outputting a signal external to the reservoir element.

7. The node of claim 6 , further comprising a third switch between the second output terminal and the second terminal.

8. Further comprising a nonlinear circuit, The node of claim 1 , wherein the nonlinear circuit is connected to the second terminal and to the first output terminal.

9. The nonlinear circuit performs nonlinear conversion of an input first signal into a second signal, the second signal and the first signal satisfy a relational expression of y≠ax+b, 9. The node of claim 8, wherein in the relation, y is the second signal, x is the first signal, and a and b are arbitrary values.

10. The node of claim 1 , wherein the second input terminal is configured to be connectable to a plurality of nodes.

11. The node of claim 1 , wherein the first output terminal is configured to be connectable to a plurality of nodes.

12. A plurality of nodes are provided. A reservoir element, wherein at least one of the plurality of nodes is a node according to claim 1.

13. The reservoir element of claim 12 , wherein at least a portion of the plurality of nodes are connected in a ring shape.

14. At least one of the plurality of nodes is a third input terminal, a second signal holding circuit, and a third output terminal; the third input terminal is configured to be connectable to at least one other node; a first terminal of the second signal holding circuit is connected to the third input terminal; a second terminal of the second signal holding circuit is connected to the third output terminal; the third output terminal is configured to be connectable to at least one other node; The reservoir element of claim 12 , wherein the second signal holding circuit holds and converts a propagating signal from the third input terminal.

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