Storage device

Abstract

To provide a storage device having a novel configuration.SOLUTION: A first transistor has a first oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, and a second insulating layer. A second transistor has a second oxide semiconductor layer, a first conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, a third insulating layer, and a fourth insulating layer. In plain view, the first oxide semiconductor layer has a region facing the first conductive layer with the first insulating layer interposed therebetween and a region facing the second conductive layer with the second insulating layer interposed therebetween. In plain view, the second oxide semiconductor layer has a region facing the fifth conductive layer with the third insulating layer interposed therebetween and a region facing the sixth conductive layer with the fourth insulating layer interposed therebetween. The first oxide semiconductor layer is provided in contact with the third conductive layer and the fourth conductive layer. The second oxide semiconductor layer is provided in contact with the first conductive layer and the seventh conductive layer. In cross view, the third conductive layer has a region overlapping with the first conductive layer, the second conductive layer, the fourth conductive layer, the fifth conductive layer, the sixth conductive layer, and the seventh conductive layer in the cross view.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device or the like.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in the present specification relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] In this specification and the like, a semiconductor device generally refers to anything that can function by utilizing semiconductor characteristics. Thus, semiconductor elements such as transistors and diodes, circuits including semiconductor elements, and the like are semiconductor devices. In addition, display devices, light-emitting devices, lighting devices, electro-optical devices, storage devices, imaging devices, communication devices, electronic devices, and the like may include semiconductor elements and / or semiconductor circuits. In addition, display devices, light-emitting devices, lighting devices, electro-optical devices, storage devices, imaging devices, communication devices, and electronic devices may also be called semiconductor devices. [Background technology]

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors have also attracted attention as other materials. Transistors using oxide semiconductors are known to have extremely small current flow in a non-conducting state (off state).

[0005] For example, Patent Document 1 discloses a memory device that can retain stored data for a long period of time by utilizing the property that a transistor including an oxide semiconductor has a low leakage current.

[0006] In addition, in recent years, along with the trend toward smaller and lighter electronic devices, there is an increasing demand for higher density memory cells in memory devices. For example, Patent Document 2 discloses a technique for increasing the density of memory cells by stacking a plurality of element layers each having a vertical transistor using an oxide semiconductor film. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2012-256831 A [Patent Document 2] International Publication No. 2022 / 160885 Summary of the Invention [Problem to be solved by the invention]

[0008] In the case of a configuration in which multiple element layers each having a memory cell are stacked as in Patent Document 1 and Patent Document 2, the density of the memory cells can be increased. However, as the density of the memory cells increases, the spacing between wirings connected to transistors becomes narrower, which may increase the effect of parasitic capacitance. This makes it difficult to control the conductive state (also called the on state or on) or non-conductive state (off state or off) of the transistor, which may make it difficult to retain stored contents in the memory cells for a long period of time.

[0009] An object of one embodiment of the present invention is to provide a storage device having a novel structure. Another object of one embodiment of the present invention is to provide a storage device which is excellent in terms of reduced power consumption, improved operation speed, miniaturization, or improved storage capacity.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not need to solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention includes a memory cell including a first transistor and a second transistor. The first transistor includes a first oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, and a second insulating layer. The second transistor includes a second oxide semiconductor layer, the first conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, a third insulating layer, and a fourth insulating layer. The first oxide semiconductor layer has, in a plan view, a region that faces the first conductive layer with the first insulating layer interposed therebetween and a region that faces the second conductive layer with the second insulating layer interposed therebetween. The second oxide semiconductor layer has, in a plan view, a region that faces the fifth conductive layer with the third insulating layer interposed therebetween and a region that faces the sixth conductive layer with the fourth insulating layer interposed therebetween. a conductor layer is provided in contact with the third conductive layer and the fourth conductive layer, a second oxide semiconductor layer is provided in contact with the first conductive layer and the seventh conductive layer, the third conductive layer has an area overlapping with the first conductive layer, the second conductive layer, the fourth conductive layer, the fifth conductive layer, the sixth conductive layer, and the seventh conductive layer in a cross-sectional view, a first potential applied to the second conductive layer during a period when data is written to the memory cell is higher than a second potential applied to the second conductive layer during a period when data is held in the memory cell, a third potential applied to the sixth conductive layer during a period when data is read from the memory cell is higher than a fourth potential applied to the sixth conductive layer during a period when data is held in the memory cell, the third potential is lower than the first potential, and the fourth potential is lower than the second potential.

[0012] In one aspect of the present invention, the memory cell preferably has a capacitor, one electrode of which is electrically connected to the first conductive layer.

[0013] In one embodiment of the present invention, the other electrode of the capacitor is preferably electrically connected to the sixth conductive layer.

[0014] In one embodiment of the present invention, the first insulating layer or the second insulating layer preferably contains hafnium, zirconium, and oxygen.

[0015] In one embodiment of the present invention, in the memory device, each of the first oxide semiconductor layer and the second oxide semiconductor layer preferably contains at least indium.

[0016] Other aspects of the present invention will be described in the following embodiment and in the drawings. Effect of the Invention

[0017] According to one embodiment of the present invention, a storage device having a novel structure can be provided. In addition, according to one embodiment of the present invention, a storage device excellent in terms of reduced power consumption, improved operation speed, miniaturization, or improved storage capacity can be provided.

[0018] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0019] [Figure 1] Fig. 1A is a circuit diagram of a memory cell, and Fig. 1B is a timing chart of the memory cell. [Diagram 2] Fig. 2(A) is a schematic diagram for explaining the voltage in a memory cell, and Fig. 2(B) and Fig. 2(C) are circuit diagrams of the memory cell. [Diagram 3] 3A is a cross-sectional view of a transistor, and FIG 3B is a plan view of the transistor. [Figure 4] 4A is a cross-sectional view of a transistor, and FIG 4B is a circuit diagram of the transistor. [Diagram 5] 5A to 5C are circuit diagrams of a memory cell. [Figure 6] 6A to 6C are circuit diagrams of a memory cell. [Figure 7] FIG. 7 is a timing chart of the memory cell. [Figure 8] 8(A) and 8(B) are circuit diagrams of a memory cell. [Figure 9] 9A is a schematic diagram of a memory array, and FIG 9B is a schematic diagram of a memory cell. [Figure 10] 10(A) and 10(B) are plan views of a transistor, and Fig. 10(C) and 10(D) are cross-sectional views of the transistor. [Figure 11] 11A to 11D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. [Figure 12] 12A to 12D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. [Figure 13] Fig. 13A is a block diagram illustrating a configuration example of a semiconductor device, and Fig. 13B and Fig. 13C are perspective views illustrating a configuration example of a semiconductor device. [Figure 14] Fig. 14A is a block diagram illustrating an example of the configuration of a cell array, and Fig. 14B is a circuit diagram of a memory cell. [Figure 15] Fig. 15A is a block diagram illustrating an example of the configuration of a cell array, and Fig. 15B is a circuit diagram of a memory cell. [Figure 16] FIG. 16 is a diagram showing various storage devices by hierarchy. [Figure 17] 17A to 17E are diagrams for explaining application examples of the storage device. [Figure 18] 18(A) to 18(H) are diagrams showing electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated description will be omitted.

[0021] In this specification, the high power supply potential VDD (hereinafter simply referred to as "VDD", "H potential", or "H") refers to a power supply potential that is higher than the low power supply potential VSS (hereinafter simply referred to as "VSS", "L potential", or "L"). VSS refers to a power supply potential that is lower than VDD.

[0022] In addition, unless otherwise specified, the transistors described in this specification and the like are enhancement-type (normally-off) n-channel field effect transistors. Therefore, the threshold voltage (also referred to as "Vth") is assumed to be higher than 0 V. In addition, unless otherwise specified, "supplying an H potential to the gate of a transistor" may be synonymous with "turning the transistor on." In addition, unless otherwise specified, "supplying an L potential to the gate of a transistor" may be synonymous with "turning the transistor off."

[0023] In addition, in drawings, etc., to make the potential of wiring and electrodes easier to understand, "H" indicating H potential or "L" indicating L potential may be written next to the wiring and electrode. Wiring and electrodes where a potential change has occurred may be written with "H" or "L" enclosed in a box. When a transistor is in the off state, an "x" symbol may be written over the transistor.

[0024] In addition, in this specification and the like, when the same reference numeral is used for multiple elements, and when it is particularly necessary to distinguish between them, the reference numeral may be accompanied by an identifying reference numeral such as "_1", "_2", "[n]", "[m,n]", etc. For example, the second wiring GL may be described as wiring GL[2].

[0025] (Embodiment 1) In this embodiment, a configuration example of a memory cell included in a memory device according to one embodiment of the present invention will be described with reference to drawings.

[0026] 1A is an example of a circuit diagram of a memory cell of a memory device of one embodiment of the present invention. In FIG. 1A, memory cells 10_1 to 10_3 are illustrated as examples of memory cells. Each of the memory cells 10_1 to 10_3 includes transistors VT1 and VT2.

[0027] The memory cells 10_1 to 10_3 are connected to the wirings WBL, SL, and RBL, respectively. The memory cell 10_1 is connected to the wirings WWL1, BGL1, and RWL1. The memory cell 10_2 is connected to the wirings WWL2, BGL2, and RWL2. The memory cell 10_3 is connected to the wirings WWL3, BGL3, and RWL3.

[0028] Data can be written to the memory cells 10_1 to 10_3 by controlling the on or off state of the transistor VT2 to provide charges corresponding to the data to the nodes FN1 to FN3. The wiring WBL is a wiring for transmitting data (write data) to be written to the memory cells 10_1 to 10_3. The wirings WWL1 to WWL3 function as wirings for transmitting word signals (write word signals) for controlling the timing of writing data held in the memory cells 10_1 to 10_3. Specifically, data to be held in the memory cells 10_1 to 10_3 can be written by turning on the transistor VT2. Charges corresponding to the data written to the memory cells 10_1 to 10_3 can be held in the nodes FN1 to FN3 by turning off the transistor VT2. The wirings BGL1 to BGL3 function as wirings for transmitting control signals for controlling the electrical characteristics of the transistor VT2, for example, the threshold voltage. The transistor VT2 functions as a transistor for writing and holding data.

[0029] Data can be read from the memory cells 10_1 to 10_3 based on the difference in the amount of current flowing through the transistor VT1, which changes depending on the potentials of the nodes FN1 to FN3. The wiring RBL is a wiring for transmitting data (read data) read from the memory cells 10_1 to 10_3. The wiring SL is a wiring for passing a current corresponding to the charge written between the source and drain of the transistor VT1 between the wiring RBL and the wiring SL. The wirings RWL1 to RWL3 function as wirings for transmitting a word signal (read word signal) for controlling the timing of reading data held in the memory cells 10_1 to 10_3. Specifically, by setting the potential of the wiring RWL to an L level and shifting the threshold voltage of the transistor VT1 to the positive side, a state in which no current flows through the transistor VT1 regardless of the potentials of the nodes FN1 to FN3 is achieved. In addition, by shifting the threshold voltage of the transistor VT1 to near 0, a state in which the amount of current flowing through the transistor VT1 changes depending on the potentials of the nodes FN1 to FN3 is achieved. The transistor VT1 functions as a transistor for reading data.

[0030] The wiring WWL may be called a write word line, the wiring RWL may be called a read word line, the wiring WBL may be called a write bit line, the wiring RBL may be called a read bit line, and the wiring SL may be called a source line.

[0031] The transistors VT1 and VT2 are transistors having an oxide semiconductor in a channel formation region (OS transistors). A memory having memory cells each having an OS transistor may be referred to as an "OS memory". Examples of oxide semiconductors used for the OS transistor include indium oxide (In oxide), gallium oxide (Ga oxide), and zinc oxide (Zn oxide). An element layer having an OS transistor can be stacked on an element layer having a Si transistor. This can increase the transistor density per unit area.

[0032] In addition, the off-state current of the OS transistor is extremely low. Therefore, charge corresponding to data written to the memory cell 10 can be held for a long time. In the case of the memory cell 10_1 shown in FIG. 1A, charge corresponding to data written through the transistor VT2 can be held for a long time in the node FN1 to which the gate of the transistor VT1 is connected by turning off the transistor VT2. In the memory cell 10_2 or 10_3 shown in FIG. 1A, charge corresponding to data written through the transistor VT2 can be held for a long time in the node FN2 or FN3. Therefore, the frequency of data refresh can be reduced, and the power consumption of the memory device of one embodiment of the present invention can be reduced.

[0033] That is, the memory device provided with the memory cells 10_1 to 10_3 having OS transistors can be a nonvolatile oxide semiconductor random access memory (NOSRAM). For example, the memory cells 10_1 to 10_3 in FIG. 1A are two-transistor (2T) NOSRAMs. Since NOSRAMs rewrite data by charging and discharging electric charge, there is no restriction on the number of rewrites in principle, and they are low energy. Furthermore, since NOSRAMs have transistors for reading data, they have a high signal supply capability for data that can be read out via the wiring RBL, and therefore can operate at high speed, have low power consumption, and are highly durable. Furthermore, NOSRAMs are suitable for long-term data retention because written data can be read out nondestructively.

[0034] Moreover, OS transistors have better electrical characteristics than Si transistors in high-temperature environments. Specifically, OS transistors have a large ratio of on-current to off-current even at high temperatures of 125° C. to 150° C., and therefore can perform good switching operations. Furthermore, OS transistors operate well within a temperature range of −40° C. to 190° C. In other words, OS transistors have very good heat resistance. This is better heat resistance than the heat resistance of a phase change memory (PCM) (−40° C. to 150° C.), a resistance random access memory (ReRAM) (−40° C. to 125° C.), a magnetoresistive random access memory (MRAM) (−40° C. to 105° C.), and the like.

[0035] The transistors VT1 and VT2 of the memory cells 10_1 to 10_3, which can be 2T-type NOSRAM shown in FIG. 1A, are vertical transistors in which the source electrode and the drain electrode are located at different heights relative to the surface on which they are formed, such as a substrate. In the vertical transistor, a current flows in the height direction (Z direction) in the channel formation region of the semiconductor layer. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the above-mentioned vertical transistor can also be called a VFET (Vertical Field Effect Transistor), a vertical channel transistor, a vertical channel transistor, or a vertical transistor.

[0036] In a vertical transistor, the source region, the channel formation region, and the drain region can be at least partially overlapped in a top view, so that the occupied area (also called a footprint) can be made smaller than that of a horizontal transistor (also called a planar structure or a planar type) in which the source electrode and the drain electrode are located at the same height. In addition, since the vertical transistor has a structure that can reduce the channel length and increase the channel width, the on-resistance can be made smaller (the on-current can be increased).

[0037] Next, the operation of the memory device according to one embodiment of the present invention will be described with reference to Fig. 1B, taking the memory cells 10_1 to 10_3 shown in Fig. 1A as an example. Fig. 1B is a timing chart showing changes over time in the potential of signals (data, control signals, word signals, etc.) input to each wiring (WWL_1 to WWL_3, BGL_1 to BGL_3, WBL, RWL_1 to RWL_3, RBL, and SL). Fig. 1B illustrates operations during data writing (period T10), data retention (period T20), and data reading (period T30).

[0038] The period T10 includes a period T11 for writing data to the memory cell 10_1, a period T12 for writing data to the memory cell 10_2, and a period T13 for writing data to the memory cell 10_3. The period T30 includes a period T31 for reading data from the memory cell 10_1, a period T32 for reading data from the memory cell 10_2, and a period T33 for reading data from the memory cell 10_3.

[0039] In the memory cell 10_1 shown in FIG. 1A, data can be written to the memory cell 10_1 by supplying a control signal to the wiring BGL1, data to the wiring WBL, and a word signal to the wiring WWL1. Data held in the memory cell 10_1 can be read by supplying a word signal to the wiring RWL1 and a precharge potential for reading data to the wiring RBL. Data can be read from and written to any of the memory cells 10_1 to 10_3 by controlling the signals supplied to the respective wirings. Thus, a memory device having the memory cells 10_1 to 10_3 can function as a NOR type memory device.

[0040] In a period T11 of the period T10, data D1 is written to the memory cell 10_1. The wiring WWL1 is set to the H level, and the wiring BGL1 is set to the H level. In the memory cell 10_1, the transistor VT2 can be turned on with the threshold voltage of the transistor VT2 shifted in the negative direction. Therefore, the amount of current flowing through the transistor VT2 in the memory cell 10_1 can be increased. As a result, the change in the potential of the node FN1 of the memory cell 10_1 can be made steep, and data can be written at high speed.

[0041] Similarly, data D2 and D3 are written to memory cells 10_2 and 10_3 during periods T12 and T13 of period T10. In memory cells 10_2 and 10_3, the threshold voltage of transistor VT2 can be shifted in the negative direction and transistor VT2 can be turned on. This allows the amount of current flowing through transistor VT2 to be increased in memory cells 10_2 and 10_3. As a result, the potential of node FN2 of memory cell 10_2 and node FN3 of memory cell 10_3 can change sharply.

[0042] In the period T20, data D1 to D3 are held in the memory cells 10_1 to 10_3. The wirings WWL1 to WWL3 are set to the L level, and the wirings BGL1 to BGL3 are set to the L level. In the memory cells 10_1 to 10_3, the threshold voltage of the transistor VT2 is shifted in the positive direction, and the transistor VT2 can be turned off. Therefore, the amount of current flowing through the transistor VT2 in the memory cells 10_1 to 10_3 can be made extremely small. As a result, the fluctuation in the potential of the nodes FN1 to FN3 in the memory cells 10_1 to 10_3 can be made extremely small for a long period of time.

[0043] Note that the wirings RWL1 to RWL3 are set to the L level throughout the periods T10 and T20. In the memory cells 10_1 to 10_3, the threshold voltage of the transistor VT2 is shifted significantly in the positive direction. In this state, the amount of current flowing between the source and drain of the transistor VT1 can be reduced regardless of the potentials of the nodes FN1 to FN3. As a result, even when data is written to the memory cells 10_1 to 10_3, that is, when the potentials of the nodes FN1 to FN3 are high, the transistor VT can be maintained in the off state.

[0044] In a period T31 of the period T30, data D1 is read from the memory cell 10_1. The line RWL1 is set to the H level, and the line RBL is set to the potential V PREIn the memory cell 10_1, the threshold voltage of the transistor VT1 can be shifted to approximately 0 V. A current can flow between the source and drain of the transistor VT1 according to the potential held at the node FN1. Therefore, the memory cell 10_1 can change the potential of the wiring RBL according to the amount of current flowing through the transistor VT1, and thus data D1 can be read out.

[0045] Similarly, in periods T32 and T33 of the period T30, data D2 and D3 are read from memory cells 10_2 and 10_3. In memory cells 10_2 and 10_3, wirings RWL2 and RWL3 are set to H level in that order. The threshold voltage of transistor VT1 can be shifted to near 0V. A current can flow between the source and drain of transistor VT1 according to the potentials held at nodes FN2 and FN3. Therefore, the memory cells 10_2 and 10_3 can change the potential of the wiring RBL according to the amount of current flowing through transistor VT1, and therefore data D2 and D3 can be read out.

[0046] 1B, the H-level potential of the signals of the wirings BGL_1 to BGL_3 is illustrated as V1 and the L-level potential is illustrated as V2. Also, in FIG. 1B, the H-level potential of the signals of the wirings RWL_1 to RWL_3 is illustrated as V3 and the L-level potential is illustrated as V4. Also, the potential of the wiring SL is illustrated as V5, which is the same level as the potential V3. Note that by setting the potential V5 to be equal to or higher than the potential V4 and equal to or lower than the potential V3, a current can be passed through the transistor VT2 at a predetermined timing.

[0047] 2A is a schematic diagram illustrating the voltage relationship of the above-mentioned potentials V1 to V5 in the memory cells 10_1 to 10_3. As shown in FIG. 2A, the potential V1 applied to the wiring BGL (wirings BGL_1 to BGL_3) is higher than the potential V2. That is, in the memory cells 10_1 to 10_3, the potential V1 applied to the wiring BGL during the data writing period is higher than the potential V2 applied to the wiring BGL during the data retention period.

[0048] 2A, the potential V3 applied to the wirings RWL (wirings RWL_1 to RWL_3) is higher than the potential V4. That is, in the memory cells 10_1 to 10_3, the potential V3 applied to the wirings RWL during the data read period is higher than the potential V4 applied to the wirings RWL during the data retention period.

[0049] 2A, the potential V3 is lower than the potential V1, and the potential V4 is lower than the potential V2. In other words, the potential V3 applied to the wiring RWL during the data read period is lower than the potential V1 applied to the wiring BGL during the data write period. The potential V4 applied to the wiring RWL during the data retention period is lower than the potential V2 applied to the wiring BGL during the data retention period.

[0050] As shown in Figure 2(A), by making the potentials of a control signal that controls the electrical characteristics of transistor VT1, a control signal that controls the electrical characteristics of transistor VT2, and a word signal that controls the timing of reading data given to transistor VT2 different, the electrical characteristics of transistor VT1 and transistor VT2 can be controlled according to the data write period, data retention period, and data read period.

[0051] Specifically, for example, during a data write period, the potentials of the wirings are as shown in FIG. 2B. In FIG. 2B, the potential V DWrepresents a data potential to be written to the memory cell 10. A potential V1 is applied to the transistor VT2 as a control signal. When the wiring WWL is set to the H level, the transistor VT2 is supplied with a potential V DW Current I according to VT2 flows.

[0052] On the other hand, in the data write period shown in FIG. 2B, the potential V4 is applied to the transistor VT1 as a word signal. Therefore, the threshold voltage of the transistor VT1 can be shifted significantly in the positive direction. D Regardless of this, the transistor VT1 can be turned off (marked with an x ​​in the figure), and as a result, the amount of current flowing through the memory cell 10 can be made extremely small during the data write period and data retention period.

[0053] During the data read period, the potentials of the wirings are as shown in FIG. 2C. In FIG. 2C, the potential V PRE represents a precharge potential for reading data from the memory cell 10. A potential V3 is applied to the transistor VT1 as a word signal. The data potential V D The current I flows through the transistor VT1 depending on VT1 A current I VT1 The amount of current is the data potential V D is large when the potential is H, and the data potential V D is small when the potential is L. Current I VT1 Depending on the amount of current, the potential V of the wiring RBL PRE fluctuates, and the data potential V DR can be read out.

[0054] On the other hand, in the data read period shown in FIG. 2C, a potential V2 is applied to the transistor VT2 as a control signal. The potential V2 is lower than the potential V1. Therefore, the threshold voltage of the transistor VT1 can be shifted in the negative direction. Even if the potential of the wiring WWL, which is at an L level, fluctuates, the transistor VT2 can be turned off (indicated by an x ​​in the figure). As a result, the amount of fluctuation in the potential of the node FN can be made extremely small during the data retention period and the data read period.

[0055] 2A to 2C are particularly effective in a configuration in which the transistors VT1 and VT2 are vertical transistors and are stacked. When the transistors VT1 and VT2 are stacked as vertical transistors, the spacing between wirings connected to the transistors is narrowed as the memory cells are densely packed, and the effect of parasitic capacitance is increased. This makes it difficult to control the on / off state of the transistor, and it may be difficult to hold the stored contents in the memory cell for a long period of time, or a current may flow to the memory cell during a period other than the read period due to the held data potential, resulting in increased power consumption.

[0056] One embodiment of the present invention is a structure in which a conductive layer functioning as a first gate electrode or a second gate electrode of a vertical transistor is given a potential that controls the electrical characteristics of the transistor, specifically, the threshold voltage. With this structure, different potentials can be given to each transistor depending on a write operation, a holding operation, or a read operation, so that the electrical characteristics of the transistor can be controlled. With this structure, a memory device excellent in reducing power consumption, improving the operating speed, miniaturization, or improving the storage capacity can be obtained.

[0057] The first gate electrode of the vertical transistor is an electrode to which a signal that controls the on or off state of the transistor is applied. The second gate electrode of the vertical transistor is an electrode that applies a potential that controls the threshold voltage of the transistor. By applying a negative potential to the second gate electrode, the threshold voltage of the transistor can be controlled to shift to the positive side, thereby reducing the off-current. By applying a positive potential to the second gate electrode, the threshold voltage of the transistor can be controlled to shift to the negative side, thereby increasing the on-current.

[0058] For example, in the case of the transistor VT2 in FIG. 1A, the electrode connected to the wiring WWL can be the first gate electrode, and the electrode connected to the wiring BGL can be the second gate electrode. In the above example, the electrode functioning as the first gate electrode and the electrode functioning as the second gate electrode can be replaced by switching the connection between the wiring WWL and the wiring BGL. The first gate electrode may be called a gate electrode. The second gate electrode may be called a backgate electrode.

[0059] Next, a configuration example of a vertical transistor applicable to the transistors VT1 and VT2 shown in Fig. 1A will be described. Fig. 3A shows a cross-sectional view of a transistor VT applicable to the transistors VT1 and VT2, and Fig. 3B shows a plan view along the dashed line X1-X2 in Fig. 3A.

[0060] In the drawings described below, arrows indicating the X, Y, and Z directions may be attached. The X, Y, and Z directions are mutually orthogonal. In this specification, one of the X, Y, and Z directions may be called the "first direction" or "first direction". One of the other two may be called the "second direction" or "second direction". The remaining one may be called the "third direction". The direction parallel to the XY plane is called the horizontal direction, and the direction perpendicular to the XY plane is called the vertical direction.

[0061] FIG. 4(A) shows a cross-sectional view in which terminals corresponding to the circuit symbols of the transistors VT1 and VT2 shown in FIG. 4(B) are added to the cross-sectional view shown in FIG. 3(A). As shown in FIGS. 4(A) and 4(B), the conductive layer 110 functions as one of the source and drain (lower electrode BSD). The conductive layer 120 functions as one of the first gate electrode and the second gate electrode (second gate electrode BGE). The conductive layer 130 functions as the other of the source and drain (upper electrode TSD). The conductive layer 140 functions as the other of the first gate electrode and the second gate electrode (first gate electrode TGE). The first gate electrode is an electrode to which a signal is applied to control the on or off state of the transistor.

[0062] In FIG. 3A, a conductive layer 110 is provided over a substrate (not shown). An insulating layer 181 is provided over the conductive layer 110. A conductive layer 120 is provided on the insulating layer 181. A conductive layer 130 is provided over the insulating layer 181. An opening 182 is provided in a region of the insulating layer 181 overlapping with the conductive layer 110. An insulating layer 170 is provided so as to be in contact with a side surface of the opening 182. The oxide semiconductor layer 150 is in contact with a recess of the conductive layer 110, a side surface of the insulating layer 170, and an upper surface of the conductive layer 130. The insulating layer 160 is located inside the oxide semiconductor layer 150 in the opening 182. The conductive layer 140 is located inside the insulating layer 160 in the opening 182. An insulating layer 183 is provided over the conductive layer 140 and the insulating layer 160.

[0063] The surface on which the conductive layer 110 is formed, such as an insulating layer, corresponds to the XY plane described above. The horizontal direction described above corresponds to the direction parallel to the surface on which the conductive layer 110 is formed. The Z direction described above corresponds to the direction perpendicular to the surface on which the conductive layer 110 is formed.

[0064] The channel length of the transistor VT is the distance between the source region and the drain region, specifically, the distance from the conductive layer 110 in contact with the oxide semiconductor layer 150 to the conductive layer 130 in contact with the oxide semiconductor layer 150. In other words, the channel length of the transistor VT can be set by the thickness of the insulating layer 181 on the conductive layer 110.

[0065] In a lateral transistor, the channel length is limited by the exposure limit of photolithography, but in the configuration of FIG. 3A, the channel length can be set by the film thickness of the insulating layer 181. Therefore, the channel length of the transistor VT can be made to be an extremely fine structure below the exposure limit of photolithography. This increases the on-current of the transistor VT, and improves the frequency characteristics. Therefore, a memory device with high operating speed can be provided.

[0066] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 182. This allows the area occupied by the transistor VT to be reduced compared to a lateral transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows the memory device to be highly integrated, thereby increasing the memory capacity per unit area.

[0067] 3A has a recessed portion at a position overlapping with the opening 182. The recessed portion in the conductive layer 110 can increase the area where the oxide semiconductor layer 150 is in contact with the conductive layer 110. Thus, the contact resistance between the oxide semiconductor layer 150 and the conductive layer 110 can be reduced.

[0068] In addition, in the plan view illustrated in FIG. 3B corresponding to the XY plane including the channel formation region of the oxide semiconductor layer 150, the conductive layer 140, the insulating layer 160, the oxide semiconductor layer 150, and the insulating layer 170 are provided concentrically. Therefore, the side surface of the conductive layer 140 provided at the center faces the side surface of the oxide semiconductor layer 150 through the insulating layer 160, and the side surface of the conductive layer 120 faces the side surface of the oxide semiconductor layer 150 through the insulating layer 170. That is, the entire periphery of the oxide semiconductor layer 150 can be surrounded by the conductive layer through the insulating layer in a plan view. Therefore, by increasing the diameter of the opening 182, the region that becomes the channel formation region can be increased. As a result, by increasing the diameter of the opening 182, the channel width per unit area can be increased, and the on-current can be increased.

[0069] In the structure of FIG. 3B, the insulating layer 170 is in contact with the outer surface of the oxide semiconductor layer 150. The conductive layer 120 surrounds the entire outer periphery of the oxide semiconductor layer 150 with the insulating layer 170 interposed therebetween. The insulating layer 160 is in contact with the inner surface of the oxide semiconductor layer 150. The oxide semiconductor layer 150 surrounds the entire outer periphery of the conductive layer 140 with the insulating layer 160 interposed therebetween. Thus, the channel formation region of the transistor VT can be formed over the entire surface of the oxide semiconductor layer 150 in the opening 182 (the entire region in contact with the insulating layers 160 and 170). As a result, the transistor VT of one embodiment of the present invention can have both a large on-state current and normally-off characteristics.

[0070] The channel formation region of a transistor having an oxide semiconductor layer has more oxygen vacancies (V O It is preferable that the concentration of impurities such as hydrogen, nitrogen, and metal elements is low. In addition, hydrogen near the oxygen vacancy is replaced by a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V O H) and generate electrons that become carriers. Therefore, in the channel formation region, V OIt is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0071] In addition, the source and drain regions of a transistor that uses an oxide semiconductor for the semiconductor layer have more oxygen vacancies than the channel formation region. O This is a region with a high carrier concentration and low resistance due to a high concentration of H or a high concentration of impurities such as hydrogen, nitrogen, and metal elements. In other words, the source and drain regions of a transistor are n-type regions with a high carrier concentration and low resistance compared to the channel formation region.

[0072] The band gap of the oxide semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using an oxide semiconductor with a wide band gap for the semiconductor layer, the off-state current of a transistor can be reduced. By using a transistor with a small off-state current for a memory cell, stored data can be retained for a long period of time. In other words, a refresh operation is not required or is performed very rarely, and therefore the power consumption of the memory device can be sufficiently reduced.

[0073] Fig. 5A is a diagram showing a configuration example of a memory cell 10 applicable to the memory cells 10_1 to 10_3 described in Fig. 1A. In Fig. 5A, in addition to the symbols of each wiring, information on the terminals of the transistors shown in Figs. 4A and 4B (the lower electrode BSD, the second gate electrode BGE, the upper electrode TSD, and the first gate electrode TGE) is added.

[0074] As shown in FIG. 5(A), the wiring WWL is connected to the first gate electrode TGE of the transistor VT2. As shown in FIG. 5(A), the wiring WBL is connected to the upper electrode TSD of the transistor VT2. As shown in FIG. 5(A), the wiring BGL is connected to the second gate electrode BGE of the transistor VT2. As shown in FIG. 5(A), the node FN is connected to the first gate electrode TGE of the transistor VT1. The first gate electrode TGE of the transistor VT1 also functions as the lower electrode BSD. As shown in FIG. 5(A), the wiring RWL is connected to the second gate electrode BGE of the transistor VT1. As shown in FIG. 5(A), the wiring SL is connected to the upper electrode TSD of the transistor VT1. As shown in FIG. 5(A), the wiring RBL is connected to the lower electrode BSD of the transistor VT1.

[0075] Note that in the transistor of one embodiment of the present invention, in particular, there is a case where a structure in which the conductive layer 140 is used as a first gate electrode TGE and the conductive layer 120 is used as a second gate electrode BGE is preferable. When the conductive layer 140, which has a larger region facing the oxide semiconductor layer 150 than the conductive layer 120, is used as the first gate electrode TGE, a gate electric field can be applied to the oxide semiconductor layer 150 more efficiently, so that the electrical characteristics of the transistor can be improved in some cases.

[0076] 5A, by configuring each wiring to be connected to each terminal of the transistor VT1, it is possible to provide an overlapping region in the vertical direction of the conductive layer 110 that is a part of the wiring RBL, among the conductive layer 120 that is a part of the wiring RWL, the conductive layer 130 that is a part of the wiring SL, and the conductive layer 140 that is a node FN. Similarly, by configuring each wiring to be connected to each terminal of the transistor VT2, it is possible to provide an overlapping region in the vertical direction of the conductive layer 140 that is the node FN, among the conductive layer 120 that is a part of the wiring BGL, the conductive layer 130 that is a part of the wiring WBL, and the conductive layer 140 that is a part of the wiring WWL.

[0077] The configuration of the memory cell applicable to the memory cells 10_1 to 10_3 described in FIG. 1(A) is not limited to the configuration of FIG. 5(A). For example, the configuration of FIG. 5(B) or FIG. 5(C) may be used. The memory cell 10A shown in FIG. 5(B) has a configuration in which the wiring WWL is connected to the second gate electrode BGE of the transistor VT2 and the wiring BGL is connected to the first gate electrode TGE of the transistor VT2 in the configuration of FIG. 5(A). The memory cell 10B shown in FIG. 5(C) has a configuration in which the wiring SL is connected to the lower electrode BSD of the transistor VT1 and the wiring RBL is connected to the upper electrode TSD of the transistor VT1 in the configuration of FIG. 5(A).

[0078] One embodiment of the present invention is a structure in which a conductive layer functioning as a first gate electrode or a second gate electrode of a vertical transistor is given a potential for controlling the electrical characteristics of the transistor, specifically, the threshold voltage. With this structure, different potentials can be given to each transistor depending on a write operation, a holding operation, or a read operation, thereby controlling the electrical characteristics of the transistor. In addition, the structures shown in Figures 5(A) to 5(C) can make the parasitic capacitance of each wiring different.

[0079] For example, in the vertical transistor shown in Fig. 4A, the parasitic capacitance between the first gate electrode TGE and the upper electrode TSD is larger than the parasitic capacitance between the first gate electrode TGE and the lower electrode BSD. Therefore, by placing the data read wiring RBL on the lower electrode BSD side as shown in Fig. 5A, the power consumption required for charging and discharging the wiring can be reduced.

[0080] For example, in the vertical transistor shown in Fig. 4A, the parasitic capacitance of the first gate electrode TGE is larger than that of the second gate electrode BGE. Therefore, as shown in Fig. 5B, the wiring WWL that controls the on / off state of the transistor VT2 is located on the second gate electrode BGE side, thereby reducing the power consumption required for charging and discharging the wiring.

[0081] For example, in the vertical transistor shown in FIG. 4A, the wiring SL for applying a constant potential is located on the lower electrode BSD side, so that the influence of noise from the wiring in the lower layer of the vertical transistor can be reduced.

[0082] By using the structures shown in FIGS. 5A to 5C, a storage device excellent in terms of reduced power consumption, improved operation speed, miniaturization, or improved storage capacity can be provided.

[0083] In the memory cell 10 described in Fig. 5A, a capacitor for holding a data potential is preferably connected to the node FN. Fig. 6A is a diagram showing a configuration example of a memory cell 10C having a capacitor, which can be applied to the memory cells 10_1 to 10_3 described in Fig. 1A.

[0084] A memory cell 10C shown in Fig. 6A includes a capacitor CS in addition to the configuration shown in Fig. 5A. One terminal of the capacitor CS is connected to a node FN. The other terminal of the capacitor CS is connected to a wiring CSL. The wiring CSL is a wiring to which a constant potential is applied to maintain the potential of the node FN.

[0085] The configuration of the memory cell having the capacitor described in FIG. 6(A) is not limited to the configuration in FIG. 6(A). For example, the configuration in FIG. 6(B) or FIG. 6(C) may be used. The memory cell 10D shown in FIG. 6(B) has a configuration in which the other terminal of the capacitor CS in the configuration in FIG. 6(A) is connected to the second gate electrode BGE of the transistor VT2, that is, the wiring BGL. Since the wiring BGL is a wiring to which a constant potential is applied during the retention period and the data read period, the capacitor CS can hold the data potential of the node FN. The memory cell 10E shown in FIG. 6(C) has a configuration in which the other terminal of the capacitor CS in the configuration in FIG. 6(A) is connected to the upper electrode TSD of the transistor VT1, that is, the wiring SL. Since the wiring SL is a wiring to which a constant potential is applied, the capacitor CS can hold the data potential of the node FN.

[0086] One embodiment of the present invention is a structure in which a conductive layer functioning as a first gate electrode or a second gate electrode of a vertical transistor is given a potential that controls the electrical characteristics of the transistor, specifically, the threshold voltage. With this structure, different potentials can be given to each transistor depending on a write operation, a holding operation, or a read operation to control the electrical characteristics of the transistor. In addition, the structure shown in FIG. 6A to FIG. 6C can improve the charge holding characteristics at the node FN by including a capacitor CS. For example, the influence of a potential fluctuation caused by a word signal given to the wiring WWL fluctuating between an H level and an L level and a potential fluctuation caused by noise or the like can be reduced. With this structure, a memory device excellent in reducing power consumption, improving the operating speed, reducing size, or improving the storage capacity can be obtained.

[0087] Fig. 7 is a diagram showing a modified example of the timing chart illustrating the operation of the memory cells 10_1 to 10_3 described in Fig. 1B. Fig. 7 is different from the timing chart shown in Fig. 1B in that the control signals for the wirings BGL_1 to BGL_3 are set to the H level in the period before data is written and are set to the L level in the period after data is written.

[0088] One embodiment of the present invention is a configuration in which a conductive layer functioning as a first gate electrode or a second gate electrode of a vertical transistor is given a potential that controls the electrical characteristics of the transistor, specifically, the threshold voltage. With this configuration, different potentials can be given to each transistor depending on a write operation, a holding operation, or a read operation, thereby controlling the electrical characteristics of the transistor. In addition, the configuration shown in FIG. 7 can control writing of data without switching a control signal for the wiring BGL in accordance with the timing at which a word signal given to the wiring WWL is raised (timing at which the signal is changed from an L level to an H level). With this configuration, a memory device excellent in reducing power consumption, improving operation speed, miniaturization, or improving storage capacity can be obtained.

[0089] In a transistor in a memory device of one embodiment of the present invention, a ferroelectric material can be used for, for example, the insulating layer (e.g., the insulating layers 160 and 170) shown in FIG. 3A or the insulating layer included in the capacitor CS shown in FIG. 6A.

[0090] A memory cell 10F shown in FIG. 8(A) is an example of a circuit diagram in which a material exhibiting ferroelectricity is applied to the insulating layer 160 of the insulating layers shown in FIG. 3(A).

[0091] Examples of materials that exhibit ferroelectricity include oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. It is also preferable to use a material in which a Group 3 element is added to the oxide. For example, the oxide preferably contains one or more of scandium, yttrium, and elements belonging to the lanthanoids. In particular, yttrium, lanthanum, and scandium are preferable because they are relatively easy to handle and have high affinity with semiconductor manufacturing processes. By adding such elements, not only can ferroelectricity be stably expressed, but also deterioration of characteristics during repeated rewriting can be suppressed, and reliability can be improved. For example, it is preferable to add these elements at a ratio of 0.5 at% or more and 10 at% or less. Other additive elements include silicon, aluminum, gadolinium, and scandium.

[0092] Oxides containing either or both of hafnium and zirconium easily exhibit ferroelectricity even in extremely thin films prepared using thin-film deposition methods such as sputtering and atomic layer deposition (ALD). This makes them highly compatible with semiconductor manufacturing processes and allows for reduced production costs.

[0093] The memory cell 10G shown in Fig. 8B is an example of a circuit diagram in which a ferroelectric material is applied to the insulating layer of the capacitor CS shown in Fig. 6A. The capacitor CS having a ferroelectric material is sometimes called a ferroelectric capacitor.

[0094] With the configuration shown in FIGS. 8A and 8B, the memory device of one embodiment of the present invention can perform nondestructive readout and low voltage operation (writing and reading), and can have extremely high rewrite resistance.

[0095] 9A and 9B show an example of the configuration of a memory cell 10 of a two-transistor type NOSRAM and an example of the configuration of a memory array 400 having the memory cell. FIG. 9A is an example of a perspective view of a memory array 400 in which a plurality of memory cells 10 having a transistor VT1 and a transistor VT2 stacked are arranged side by side. The transistors VT1 and VT2 are vertical transistors. The memory cell 10 is connected to the conductive layer 110a, the conductive layer 120a, the conductive layer 130a, the conductive layer 140a, the conductive layer 120b, the conductive layer 130b, the conductive layer 140b, and the conductive layer 190. Note that, in FIG. 9A, for clarity, insulating layers such as an interlayer film are not shown, and the conductive layer 190 located at the top is indicated by a dashed line.

[0096] The conductive layer 110a shown in FIG. 9A functions as the wiring RBL (representatively, wirings RBL_1 to RBL_3) shown in FIG. 1A and the like. The conductive layer 120a shown in FIG. 9A functions as the wiring RWL (representatively, wirings RWL_1 to RWL_3) shown in FIG. 1A and the like. The conductive layer 130a shown in FIG. 9A functions as the wiring SL (representatively, wirings SL_1 to SL_3) shown in FIG. 1A and the like. The conductive layer 120b shown in FIG. 9A functions as the wiring BGL (representatively, wirings BGL_1 to BGL_3) shown in FIG. 1A and the like. The conductive layer 130b shown in FIG. 9A functions as the wiring WBL (representatively, wirings WBL_1 to WBL_3) shown in FIG. 1A and the like. The conductive layer 190 shown in FIG. 9A and the conductive layer 140b connected to the conductive layer 190 function as the wiring WWL (representatively, wirings WWL_1 to WWL_3 are illustrated) shown in FIG. 1A and the like.

[0097] 9A shows an example in which the memory cells 10 are arranged at equal intervals in the X and Y directions, but the memory cells 10 may be arranged in a staggered manner in which they are shifted alternately one by one. Also, while FIG. 9A shows an example in which the wirings are arranged so as to intersect at right angles in the X and Y directions, the wirings may be arranged so as not to intersect at right angles.

[0098] Next, a configuration example of the memory cell 10 will be described. FIG. 9B is a perspective view illustrating the configuration example of the memory cell 10. As illustrated in FIG. 9B, the transistor VT1 has, as components, a conductive layer 110a, a conductive layer 120a, a conductive layer 130a, a conductive layer 140a, and an oxide semiconductor layer 150a. The transistor VT2 has a conductive layer 140a, a conductive layer 120b, a conductive layer 130b, a conductive layer 140b, and an oxide semiconductor layer 150a. The transistor VT2 may include a conductive layer 190.

[0099] For clarity, in Figure 9(B), insulating layers such as interlayer films are not shown, and conductive layer 110a, conductive layer 120a, conductive layer 130a, conductive layer 120b, part of conductive layer 130b, and conductive layer 190 are shown with dashed lines.

[0100] 9B, the conductive layer 110a has an area overlapping with the conductive layer 120a, the conductive layer 130a, the conductive layer 140a, the conductive layer 120b, the conductive layer 130b, and the conductive layer 140b in the vertical direction (Z direction). Note that a cross-sectional view is a view from a normal direction to the vertical direction, and corresponds to a cross-sectional view cut along a plane parallel to the vertical direction.

[0101] 9A and 9B, the memory cell 10 has an overlapping region among the conductive layers 110a, 120a, 130a, 140a, 120b, 130b, and 140b. This may cause unstable operation due to electrical interference between the transistors or between the conductive layers. However, one embodiment of the present invention is a structure in which a potential for controlling the electrical characteristics of the transistor, specifically, the threshold voltage, is applied to a conductive layer that functions as a first gate electrode or a second gate electrode of a vertical transistor. With this structure, different potentials can be applied to each transistor depending on a write operation, a holding operation, or a read operation, thereby controlling the electrical characteristics of the transistor. With this structure, a memory device excellent in reducing power consumption, improving the operating speed, reducing size, or improving the storage capacity can be obtained.

[0102] A configuration example of the transistors VT1 and VT2 included in the memory cell 10 shown in Fig. 9B will be described with reference to Fig. 10(A) to Fig. 10(D). Fig. 10(A) is a plan view illustrating the transistor VT1, and Fig. 10(B) is a plan view illustrating the transistor VT2. Note that in the plan views, some elements are omitted for clarity.

[0103] Fig. 10(C) is a diagram corresponding to a cross section taken along line segment A1-A2 in Fig. 10(A) and (B), and Fig. 10(D) is a diagram corresponding to a cross section taken along line segment B1-B2 in Fig. 10(A) and (B).

[0104] The memory cell 10 includes an insulating layer 199 on a substrate (not shown), a transistor VT1 provided on the insulating layer 199, and a transistor VT2 provided on the transistor VT1. Note that insulating layers 181a, 181b, 183, and the like that function as interlayer films can be provided between the transistors and between various wirings.

[0105] The transistor VT1 includes a conductive layer 110a, a conductive layer 120a, a conductive layer 130a, a conductive layer 140a, an oxide semiconductor layer 150a, an insulating layer 160a, and an insulating layer 170a. In the transistor VT1, the oxide semiconductor layer 150a functions as a semiconductor layer. The conductive layer 140a functions as a first gate electrode. The insulating layer 160a functions as a first gate insulating film. The conductive layer 120a functions as a second gate electrode. The insulating layer 170a functions as a second gate insulating film. The conductive layer 110a and the conductive layer 130a each function as a source electrode or a drain electrode.

[0106] The transistor VT2 includes a conductive layer 140a, a conductive layer 120b, a conductive layer 130b, a conductive layer 140b, an oxide semiconductor layer 150b, an insulating layer 160b, and an insulating layer 170b. In the transistor VT2, the oxide semiconductor layer 150b functions as a semiconductor layer. The conductive layer 140b functions as a first gate electrode. The insulating layer 160b functions as a first gate insulating film. The conductive layer 120b functions as a second gate electrode. The insulating layer 170b functions as a second gate insulating film. The conductive layer 140a and the conductive layer 130b each function as a source electrode or a drain electrode.

[0107] That is, the transistors VT1 and VT2 have a structure corresponding to that of the transistor VT shown in Fig. 3(A). Therefore, in the figure, the corresponding configurations in the transistor VT and the transistors VT1 and VT2 are basically given the same three-digit numbers as symbols. In the following, unless otherwise specified, the description of the transistor VT can be referred to for the transistors VT1 and VT2.

[0108] The conductive layer 140a in the transistor VT2 corresponds to the conductive layer 110a in the transistor VT1. In other words, the conductive layer 140a has a region that shares the first gate electrode of the transistor VT1 and one of the source electrode and drain electrode of the transistor VT2.

[0109] In the transistor VT1, an oxide semiconductor layer 150a is provided in an opening 182a provided in the conductive layer 130a and the conductive layer 120a. In the opening 182a, the oxide semiconductor layer 150a has a region overlapping with the conductive layer 140a with the insulating layer 160a sandwiched therebetween and a region overlapping with the conductive layer 120a with the insulating layer 170a sandwiched therebetween in the horizontal direction (direction parallel to the XY plane). The oxide semiconductor layer 150a is in contact with the upper surface of the conductive layer 130a and the upper surface of the conductive layer 110a. Note that a plan view is a view from a normal direction to the horizontal direction, and corresponds to a cross-sectional view cut along a plane parallel to the horizontal direction.

[0110] In the transistor VT2, an oxide semiconductor layer 150b is provided in an opening 182b provided in the conductive layer 130b and the conductive layer 120b. In the opening 182b, the oxide semiconductor layer 150b has a region overlapping with the conductive layer 140b with the insulating layer 160b sandwiched therebetween and a region overlapping with the conductive layer 120b with the insulating layer 170b sandwiched therebetween in the horizontal direction (direction parallel to the XY plane). The oxide semiconductor layer 150b is in contact with an upper surface of the conductive layer 130b and an upper surface of the conductive layer 140a.

[0111] 10C and 10D, the oxide semiconductor layer 150a can be surrounded by the conductive layer 120a and the conductive layer 140a with the insulating layers 160a and 170a sandwiched therebetween, and the oxide semiconductor layer 150b can be surrounded by the conductive layer 120b and the conductive layer 140b with the insulating layers 160b and 170b sandwiched therebetween in the horizontal direction. Therefore, one embodiment of the present invention is a structure in which a potential for controlling the electrical characteristics of a transistor, specifically, a threshold voltage, is applied to a conductive layer functioning as a first gate electrode or a second gate electrode of a vertical transistor. With this structure, different potentials can be applied to each transistor depending on a write operation, a holding operation, or a read operation to control the electrical characteristics of the transistor. With this structure, a memory device excellent in reducing power consumption, improving the operating speed, miniaturization, or improving the storage capacity can be obtained.

[0112] The conductive layer 140b is connected to a conductive layer 190 formed on the conductive layer 140b. The conductive layer 140b and the conductive layer 190 may be formed as a single element.

[0113] The conductive layers 140a and 140b preferably have a generally circular top surface shape, which allows the degree of integration of the memory cells 10 to be increased.

[0114] In order to increase the overlapping area of ​​the transistors VT2 and VT1, it is preferable that the top surface shape of the opening 182b and the top surface shape of the opening 182a in which the transistor VT1 is formed be the same or similar.

[0115] The following describes materials that can be used in memory devices.

[0116] Substrates that can be used in memory devices include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include, for example, semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include the above-mentioned semiconductor substrates having an insulator region inside, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having metal nitrides and substrates having metal oxides. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0117] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.

[0118] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, the capacitance value of the parasitic capacitance that occurs between wiring can be reduced. Therefore, it is advisable to select materials according to the function of the insulator. Note that materials with a low dielectric constant also have high dielectric strength.

[0119] Examples of materials with a high dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0120] Examples of materials with low relative dielectric constants include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. Examples of other inorganic insulating materials with low relative dielectric constants include silicon oxide with fluorine added, silicon oxide with carbon added, and silicon oxide with carbon and nitrogen added. Another example is silicon oxide with vacancies. These silicon oxides may contain nitrogen.

[0121] In addition, the transistor using an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing the transmission of impurities and oxygen. As the insulator having a function of suppressing the transmission of impurities and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or a stacked layer. Specifically, as the insulator having a function of suppressing the transmission of impurities and oxygen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride can be used.

[0122] In addition, an insulating layer such as a gate insulating film that is in contact with a semiconductor layer or that is provided near the semiconductor layer preferably has a region containing excess oxygen. For example, an insulating layer having a region containing excess oxygen is provided in contact with a semiconductor layer or near the semiconductor layer, whereby oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0123] Examples of insulators having a barrier property against oxygen include oxides containing either or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, silicon nitride oxide, etc. Examples of oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0124] Examples of insulators having a barrier property against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.

[0125] An insulator having a barrier property against oxygen and an insulator having a barrier property against hydrogen can be referred to as an insulator having a barrier property against one or both of oxygen and hydrogen.

[0126] In addition, examples of insulators having the function of capturing or fixing hydrogen include oxides containing magnesium, and oxides containing one or both of aluminum and hafnium. It is more preferable that these oxides have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. It is preferable that these metal oxides have an amorphous structure, but a crystalline region may be formed in a part of the oxide.

[0127] In this specification and the like, a barrier insulating film refers to an insulating film having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that has low permeability of a corresponding substance, or a function of suppressing the diffusion of a corresponding substance). The function of capturing or fixing a corresponding substance (also referred to as gettering) can be rephrased as barrier properties. Note that hydrogen when described as a corresponding substance can refer to, for example, a hydrogen atom, a hydrogen molecule, and a water molecule and OH. -The term "impurity" refers to at least one of substances bonded to hydrogen such as hydrogen, hydrogen ions, and the like. Furthermore, unless otherwise specified, impurities described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and refer to at least one of, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Furthermore, oxygen described as corresponding substances refers to at least one of, for example, oxygen atoms, oxygen molecules, etc. Specifically, the term "barrier property against oxygen" refers to a property that makes it difficult for at least one of oxygen atoms, oxygen molecules, etc. to diffuse.

[0128] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. In addition, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0129] In addition, conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing oxygen diffusion, or materials that maintain conductivity even when oxygen is absorbed. Note that examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.

[0130] Moreover, conductive materials containing tungsten, copper, or aluminum as a main component are preferable because they have high conductivity.

[0131] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0132] In the case where an oxide semiconductor is used for the channel formation region of a transistor, a conductor functioning as a gate electrode (first gate electrode or second gate electrode) preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0133] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in an oxide semiconductor in which a channel is formed. The conductive material containing the metal element and nitrogen described above may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may also be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide containing silicon may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in an oxide semiconductor in which a channel is formed can be captured in some cases. Alternatively, hydrogen mixed in from an external insulator or the like can be captured in some cases.

[0134] The semiconductor material that can be used for the semiconductor layer is not limited to an oxide semiconductor. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the semiconductor layer. For example, it is preferable to use a semiconductor of a single element, a compound semiconductor, or a layered material (also called an atomic layer material, a two-dimensional material, or the like) as the semiconductor material.

[0135] Here, in this specification and the like, the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0136] Examples of semiconductors that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor layers include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0137] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. The boron nitride that can be used for the semiconductor layer preferably includes an amorphous structure. The boron arsenide that can be used for the semiconductor layer preferably includes a crystal with a cubic crystal structure.

[0138] Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides. In the layered material boron carbonitride, carbon, nitrogen, and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements in group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0139] As the semiconductor layer, for example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor. Specific examples of transition metal chalcogenides that can be used as the semiconductor layer include molybdenum sulfide (representatively MoS2), molybdenum selenide (representatively MoSe2), molybdenum tellurium (representatively MoTe2), tungsten sulfide (representatively WS2), tungsten selenide (representatively WSe2), tungsten tellurium (representatively WTe2), hafnium sulfide (representatively HfS2), hafnium selenide (representatively HfSe2), zirconium sulfide (representatively ZrS2), and zirconium selenide (representatively ZrSe2). By applying the above-mentioned transition metal chalcogenide to the semiconductor layer, a memory device with a large on-current can be provided.

[0140] One embodiment of the present invention is a structure in which a conductive layer functioning as a first gate electrode or a second gate electrode of a vertical transistor is given a potential that controls the electrical characteristics of the transistor, specifically, the threshold voltage. With this structure, different potentials can be given to each transistor depending on a write operation, a holding operation, or a read operation, so that the electrical characteristics of the transistor can be controlled. With this structure, a memory device excellent in reducing power consumption, improving the operating speed, miniaturization, or improving the storage capacity can be obtained.

[0141] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments.

[0142] (Embodiment 2) In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described.

[0143] [Oxide semiconductor layer] The oxide semiconductor layer of one embodiment of the present invention preferably contains a metal oxide having crystallinity. Examples of the structure of a metal oxide having crystallinity include a c-axis aligned crystal (CAAC) structure, a polycrystalline (polycrystal) structure, and a nanocrystalline (nc) structure. By using a metal oxide having crystallinity for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Thus, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a memory device including the transistor can be improved.

[0144] The oxide semiconductor layer of one embodiment of the present invention particularly preferably contains a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected without being oriented in the ab-plane. When a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Thus, the oxide semiconductor layer having a CAAC structure can be said to have a structure having layered crystal parts.

[0145] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED), or the analysis may be performed by combining a plurality of these techniques.

[0146] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics may be suppressed.

[0147] Examples of the metal oxide contained in the oxide semiconductor layer of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. Note that the element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a higher bond energy with oxygen than indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M of the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably has one or more selected from indium, gallium, and zinc. In this specification, etc., metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification, etc. may include metalloid elements.

[0148] Examples of metal oxides according to an embodiment of the present invention include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium Indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide containing silicon (also called ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0149] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-current and high frequency characteristics.

[0150] The metal oxide may have one or more kinds of metal elements having a large period number in the periodic table instead of indium. Alternatively, the metal oxide may have one or more kinds of metal elements having a large period number in the periodic table in addition to indium. The greater the overlap of the orbits of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a large period number in the periodic table, the field effect mobility of a transistor may be increased. Examples of metal elements having a large period number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0151] The metal oxide may contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the field-effect mobility of the transistor may be increased. Examples of the nonmetallic element include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0152] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing the fluctuation of the electrical characteristics of the transistor and improving its reliability.

[0153] In addition, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0154] In the present embodiment, an In-Ga-Zn oxide may be taken as an example of the metal oxide.

[0155] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0156] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by using at least two kinds of film formation methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by using a first film formation method and a second film formation method. Note that an oxide semiconductor layer formed by using at least two kinds of film formation methods may be referred to as a hybrid OS.

[0157] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by using a first film formation method, and then forming a metal oxide as a second layer over the first layer by using a second film formation method. In this case, it is preferable to use a film formation method that causes less damage to a surface to be formed as compared with the second film formation method as the first film formation method. By using a film formation method that causes less damage to a surface to be formed as the first film formation method, formation of a mixed layer at the interface between the oxide semiconductor layer and a layer that is a surface to be formed of the oxide semiconductor layer can be suppressed. Furthermore, impurities such as silicon can be suppressed from being mixed into the second layer, and thus the crystallinity of the oxide semiconductor layer can be increased.

[0158] Examples of the first film formation method include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and wet methods. Examples of the CVD method include plasma enhanced CVD (PECVD), thermal CVD, photo CVD, and metal organic CVD (MOCVD). Examples of the wet method include spray coating. Compared with the sputtering method described later, the ALD and CVD methods are suitable as the first film formation method because they can suppress damage to the surface to be formed.

[0159] Examples of the ALD method include a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0160] The ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios or surfaces with large steps; films can be formed with few defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. The PEALD method may be preferable because it uses plasma, which allows films to be formed at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. For this reason, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In one embodiment of the present invention, a metal oxide film formation method uses an ALD method. However, since the method employs a high substrate temperature condition during film formation and / or an impurity removal treatment, the amount of carbon and chlorine contained in the film may be smaller than that in the case of using an ALD method without employing these conditions.

[0161] The ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece, unlike a film formation method in which particles emitted from a target or the like are deposited. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0162] The plasma CVD method can produce high-quality films at relatively low temperatures. Thermal CVD is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. In addition, thermal CVD does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0163] Examples of the second film formation method include a sputtering method, a pulsed laser deposition (PLD) method, etc. The metal oxide formed by using the second film formation method is likely to have a CAAC structure.

[0164] The first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased with the second layer as a nucleus. This can increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0165] In addition, a third layer can be further formed on the second layer. Since the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that is likely to give crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0166] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by using a first film formation method, forming a metal oxide as a second layer by using a second film formation method, and forming a metal oxide as a third layer by using the first film formation method. Specifically, an ALD method can be used as the first film formation method, and a sputtering method can be used as the second film formation method. The ALD method has better coverage than the sputtering method, and the use of the ALD method as the film formation method for the first layer and the third layer can improve the coverage of the oxide semiconductor layer. Thus, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0167] [Method for producing oxide semiconductor layer] The oxide semiconductor 230 which is an oxide semiconductor layer can be manufactured, for example, by forming an oxide semiconductor 230a on the layer 229 which is a surface to be formed by an ALD method, forming an oxide semiconductor 230b on the oxide semiconductor 230a by a sputtering method, and forming an oxide semiconductor 230c on the oxide semiconductor 230b by an ALD method. After the oxide semiconductor 230 is formed, it is preferable to perform heat treatment. The heat treatment can improve the crystallinity of the oxide semiconductor 230. The heat treatment here is not limited to heating treatment. For example, it may be heat applied during a manufacturing process.

[0168] The oxide semiconductor 230 can be used for the oxide semiconductor layer 150 or the like. The layer 229 corresponds to the insulating layer 160, the insulating layer 170, or the like described in the above embodiment.

[0169] The layer 229 does not have to be crystalline. When the layer 229 has crystallinity, the layer 229 may have a crystal structure with low lattice matching with a metal oxide contained in the oxide semiconductor 230.

[0170] An example of a method for manufacturing the oxide semiconductor 230 will be described with reference to FIGS.

[0171] When a metal oxide film is formed by a sputtering method, the components contained in the metal oxide film may be alloyed with the components contained in the layer on which the film is formed due to damage caused by sputtering particles on the surface on which the film is formed or by energy given to the substrate by the sputtering particles or the like. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when a heat treatment described later is performed. In addition, there is a concern that the use of an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress alloying between the components contained in the metal oxide film and the components contained in the layer on which the film is formed.

[0172] For this purpose, first, an oxide semiconductor 230a is formed on the layer 229 by an ALD method (FIG. 11A). Then, an oxide semiconductor 230b is formed on the oxide semiconductor 230a by a sputtering method (FIG. 11B).

[0173] In the method for forming the oxide semiconductor layer of one embodiment of the present invention, the oxide semiconductor 230a is formed between the oxide semiconductor 230b and the layer 229 by a deposition method that causes little damage to a surface on which the oxide semiconductor 230a is formed. This suppresses alloying of components contained in the oxide semiconductor 230 and components contained in the layer 229, and thus the crystallinity of the oxide semiconductor 230 can be further improved.

[0174] With the above structure, the thickness of the alloyed region can be made thin, or can be made thin enough that the alloyed region cannot be observed. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm. Note that FIGS. 11A and 11B show an example in which no alloyed region is formed between the layer 229 and the oxide semiconductor 230a.

[0175] In addition, the thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0176] For example, an EDX line analysis is performed on the above region and its periphery with the direction perpendicular to the surface of the oxide semiconductor 230a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by the analysis, the depth at which the quantitative value of a metal (In when the oxide semiconductor 230a contains In) that is the main component of the oxide semiconductor 230a and is not the main component of the layer (here, layer 229) that will be the surface to be formed becomes half-value is defined as the depth (position) of the interface between the above region and the oxide semiconductor 230a. Also, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will be the surface to be formed and is not the main component of the oxide semiconductor 230a becomes half-value is defined as the depth (position) of the interface between the above region and the layer that will be the surface to be formed. From the above, the thickness of the alloyed region can be calculated.

[0177] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and even more preferably 0 nm to less than 0.3 nm.

[0178] For example, when a silicon oxide layer is used as the layer 229 and a SIMS analysis is performed on the oxide semiconductor 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 21 atoms / cm 3 , preferably 5.0 x 10 20 atoms / cm 3 , more preferably 1.0×10 20 atoms / cm 3 The distance between the depth at which the thickness decreases to the interface and the depth is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0179] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0180] By reducing the thickness of the alloyed region, the CAAC structure can be formed near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region that is more than 0 nm and not more than 3 nm, preferably more than 0 nm and not more than 2 nm, more preferably 1 nm or more and not more than 2 nm, approximately perpendicularly from the formation surface of the oxide semiconductor 230.

[0181] The CAAC structure near the formation surface may be observed by TEM observation. For example, in a cross-sectional observation of the oxide semiconductor 230 by a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed near the formation surface.

[0182] When the oxide semiconductor 230a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure with lower crystallinity than that of a CAAC structure may be formed. That is, at the manufacturing stage shown in FIG. 11A, the oxide semiconductor 230a may have a region with lower crystallinity than the oxide semiconductor 230b.

[0183] The oxide semiconductor 230b preferably has a composition suitable for forming a CAAC structure.

[0184] When the oxide semiconductor 230b is formed by sputtering, the mixed layer 231 is formed on or near the surface of the oxide semiconductor 230a. In addition, when the oxide semiconductor 230b is formed, a minute crystal region may be formed in the mixed layer 231 due to sputtering particles or energy given to the substrate side by the sputtering particles or the like. In a subsequent heat treatment process, the mixed layer 231 or the minute crystal region formed in the mixed layer 231 may become a nucleus, and at least a part of the oxide semiconductor 230a may be crystallized.

[0185] In the formation of the oxide semiconductor 230b by a sputtering method, it is preferable to heat the substrate. In the formation of the metal oxide, by increasing the substrate temperature (stage temperature) during the formation of the metal oxide, a metal oxide with high crystallinity can be formed in some cases.

[0186] Next, the oxide semiconductor 230c is formed on the oxide semiconductor 230b by the ALD method (FIG. 11C). For the formation of the oxide semiconductor 230c by the ALD method, the method for forming the oxide semiconductor 230a can be referred to.

[0187] When the oxide semiconductor 230c is formed on the oxide semiconductor 230b having the CAAC structure by the ALD method, the oxide semiconductor 230c may grow epitaxially with the oxide semiconductor 230b as a nucleus. Therefore, when the oxide semiconductor 230c is formed, the oxide semiconductor 230c may have a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed over the entire oxide semiconductor 230c.

[0188] Next, a heat treatment step may be performed. The heat treatment step may increase the crystallinity of the region having the CAAC structure in the oxide semiconductor 230c. When the region is formed only below the oxide semiconductor 230c after the film formation by the ALD method, the region may expand upward by the heat treatment step ( FIG. 11D ). That is, the heat treatment may form a region having the CAAC structure throughout the entire layer in the oxide semiconductor 230c.

[0189] It is also preferable that at least a part of the oxide semiconductor 230a is converted into CAAC by the heat treatment process (FIG. 11(D)). It is expected that the CAAC is easily generated because the mixed layer 231 formed in the oxide semiconductor 230a during the deposition of the oxide semiconductor 230b serves as a nucleus or seed. It is preferable that the region in the oxide semiconductor 230a that is converted into CAAC is large, and it is preferable that the CAAC is converted to CAAC up to the vicinity of the layer 229.

[0190] Furthermore, because the CAAC process occurs from the top to the bottom of the oxide semiconductor 230a, the CAAC process can be performed up to the vicinity of the layer 229 without being limited to the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the oxide semiconductor 230a can have high crystallinity. Thus, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is to be formed has an amorphous structure.

[0191] 11A to 11D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIGS. 11A to 11D can also be regarded as conceptual diagrams illustrating a model for forming a metal oxide film according to one embodiment of the present invention. As illustrated in FIGS. 11A to 11D, the oxide semiconductors 230a and 230c each have high crystallinity using the oxide semiconductor 230b having high crystallinity as a nucleus or seed. Specifically, the crystallinity of the oxide semiconductor 230a may be increased by heat treatment during the formation of the oxide semiconductor 230b or after the formation of the oxide semiconductor 230c. The crystallinity of the oxide semiconductor 230c may be increased by heat treatment during the formation of the oxide semiconductor 230c or after the formation of the oxide semiconductor 230c. Note that the heat treatment has an assisting effect of increasing the crystallinity.

[0192] In this manner, in the method for forming a metal oxide film according to one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (the oxide semiconductor 230a and the oxide semiconductor 230c here) can be increased by using the oxide semiconductor 230b with high crystallinity (i.e., CAAC) as a nucleus or seed. This can increase the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be grown in a solid phase using the oxide semiconductor 230b as a nucleus or seed to form an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method, that is, a CAAC film here, can be referred to as an axial growth CAAC (AG CAAC). Note that although the structures including the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are illustrated in FIGS. 12A to 12D, the present invention is not limited thereto. For example, the structure including the oxide semiconductor 230a and the oxide semiconductor 230b can also be an AG CAAC.

[0193] In the oxide semiconductor 230, a region having a CAAC structure is preferably present widely throughout the layer. FIG. 12A shows the oxide semiconductors 230a, 230b, and 230c each being crystallized. At this time, the boundary between the oxide semiconductors 230a and 230b may not be observed. Also, the boundary between the oxide semiconductors 230b and 230c may not be observed. The oxide semiconductor 230 may be expressed as a single layer whose interface is not clearly observed. The oxide semiconductor 230 may be expressed as a single layer.

[0194] In addition, a part of the oxide semiconductor 230a or the oxide semiconductor 230c may not be crystallized. In addition, a part of the oxide semiconductor 230a or the oxide semiconductor 230c may have a region with lower crystallinity than the CAAC structure remaining. The example shown in FIG. 12B illustrates a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor 230a is not crystallized, or a region with lower crystallinity than the CAAC structure remains near the interface. FIG. 12C illustrates a state in which the vicinity of the surface of the oxide semiconductor 230c is not crystallized, or a region with lower crystallinity than the CAAC structure remains near the surface. FIG. 12D illustrates a state in which the vicinity of the interface of the oxide semiconductor 230a with the layer 229 and the vicinity of the surface of the oxide semiconductor 230c are not crystallized, or a region with lower crystallinity than the CAAC structure remains near the interface of the oxide semiconductor 230a with the layer 229 and near the surface of the oxide semiconductor 230c.

[0195] By increasing the crystallinity of the oxide semiconductor layer, an increase in the electrical resistance of a transistor using the oxide semiconductor layer can be suppressed or initial characteristics (particularly, on-state current) of the transistor can be improved, which is expected to make the transistor suitable for high-speed operation. In addition, the reliability of the transistor can be increased, and the on-state current can be increased.

[0196] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor 230, the boundaries between the stacked films of the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c may not be visible. In particular, it may be difficult to confirm the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed by, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0197] As described above, by using a metal oxide with a high In content for a transistor, the field effect mobility of the transistor can be increased. On the other hand, an oxide semiconductor with a high In content tends to be polycrystallized. Using a metal oxide with a polycrystalline structure for a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content for one or both of the oxide semiconductors 230a and 230c, crystals that reflect the crystal orientation of the oxide semiconductor 230b are formed, and polycrystallization can be suppressed.

[0198] In addition, it is preferable that the degree of lattice mismatch between the crystals of the oxide semiconductor 230b and the crystals of the oxide semiconductor 230a or the oxide semiconductor 230c is small. This allows the oxide semiconductor 230a or the oxide semiconductor 230c to form crystals that reflect the orientation of the crystals of the oxide semiconductor 230b. In this case, for example, in a cross-sectional observation of the oxide semiconductor 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the oxide semiconductor 230a or the oxide semiconductor 230c.

[0199] As long as the degree of lattice mismatch between the crystals of the oxide semiconductor 230b and the crystals of the oxide semiconductor 230a or the oxide semiconductor 230c is small, the crystal structure of the oxide semiconductor 230a or the oxide semiconductor 230c is not particularly limited. The crystal structure of the oxide semiconductor 230a or the oxide semiconductor 230c may be any of a cubic system, a tetragonal system, an orthorhombic system, a hexagonal system, a monoclinic system, and a trigonal system.

[0200] [Composition of oxide semiconductor layer] As described above, the oxide semiconductor 230b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 230b can be formed by, for example, a sputtering method. The oxide semiconductor 230b preferably contains, for example, zinc. By containing zinc, the oxide semiconductor 230b becomes a metal oxide with high crystallinity. Furthermore, the oxide semiconductor 230b preferably contains the element M in addition to zinc. By containing the element M in the oxide semiconductor 230b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Therefore, the reliability of a transistor to which the oxide semiconductor layer is applied can be improved. Specifically, the oxide semiconductor 230b may be a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, or In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto. The composition close thereto includes a range of ±30% of the desired atomic ratio. It is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0201] The oxide semiconductor 230b may be configured not to include the element M. For example, it may be an In-Zn oxide. Specifically, it may be configured to have a composition of In:Zn=1:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn=2:1 [atomic ratio] or a composition in the vicinity thereof, or In:Zn=4:1 [atomic ratio] or a composition in the vicinity thereof. Alternatively, an indium oxide may be used. It may also be configured to include a trace amount of the element M. For example, it may be configured to have a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof. Also, it may be configured to have a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof.

[0202] The oxide semiconductor 230a and the oxide semiconductor 230c can be a metal oxide having a high proportion of In. The oxide semiconductor 230a and the oxide semiconductor 230c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, when the oxide semiconductor layer is used in a transistor, the on-current can be increased and the frequency characteristics can be improved.

[0203] Alternatively, the oxide semiconductor 230a and the oxide semiconductor 230c may be configured to not include the element M. For example, they may be In-Zn oxide. Specifically, they may have a composition of In:Zn=1:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn=2:1 [atomic ratio] or a composition in the vicinity thereof, or In:Zn=4:1 [atomic ratio] or a composition in the vicinity thereof. Alternatively, indium oxide may be used. Also, the oxide semiconductor 230a and the oxide semiconductor 230c may be configured to include a trace amount of the element M. Specifically, they may have a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof, In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof.

[0204] In addition, by increasing the composition of zinc in the oxide semiconductor, the crystallinity of the oxide semiconductor can be improved. In particular, it is preferable that the oxide semiconductor 230a contains zinc. For example, when the oxide semiconductor 230a is formed by the ALD method and the oxide semiconductor 230b is formed by the sputtering method, the zinc contained in the oxide semiconductor 230a may diffuse into the oxide semiconductor 230b. The diffusion may occur during sputtering or during a heat treatment thereafter. The diffusion of zinc from the oxide semiconductor 230a to the oxide semiconductor 230b is expected to improve the crystallinity. Alternatively, the diffusion of zinc from the oxide semiconductor 230a to the oxide semiconductor 230b is expected to promote the formation of CAAC by lateral growth of a crystal part having c-axis orientation.

[0205] The oxide semiconductor 230a and the oxide semiconductor 230c can be metal oxides containing a higher proportion of In than the oxide semiconductor 230b.

[0206] For example, the oxide semiconductor 230a and the oxide semiconductor 230c may be made of a metal oxide having a higher Ga ratio than the oxide semiconductor 230b. For example, the oxide semiconductor 230a and the oxide semiconductor 230c may be made of a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition close thereto, or a metal oxide having a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto. By increasing the ratio of Ga, for example, the band gaps of the oxide semiconductor 230a and the oxide semiconductor 230c may be made larger than that of the oxide semiconductor 230b. As a result, the oxide semiconductor 230b is sandwiched between the oxide semiconductor 230a and the oxide semiconductor 230c having a larger band gap, and the oxide semiconductor 230b mainly functions as a current path (channel). By sandwiching the oxide semiconductor 230b between the oxide semiconductor 230a and the oxide semiconductor 230c, the trap levels at the interface of the oxide semiconductor 230b and in the vicinity thereof can be reduced, thereby realizing a buried channel transistor in which the channel is separated from the insulating layer interface, and thus increasing the field effect mobility.

[0207] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductors 230a and 230c are formed using compositions that make it difficult to form a CAAC structure when they are formed into a single layer, crystal growth occurs with the oxide semiconductor 230b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductors 230a and 230c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductors 230a and 230c and the oxide semiconductor 230b.

[0208] In particular, even when the oxide semiconductor 230a and the oxide semiconductor 230c have a high In content, the oxide semiconductor layer can have suitable crystallinity for use as a semiconductor layer of a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the high In content can improve the on-state characteristics of the transistor, and the highly crystalline CAAC structure can improve reliability.

[0209] The oxide semiconductor 230a and the oxide semiconductor 230c may have different compositions.

[0210] The oxide semiconductor 230a and the oxide semiconductor 230c may be made of a metal oxide having the same composition as the oxide semiconductor 230b.

[0211] By using an oxide semiconductor layer having a CAAC structure formed by using the above-described two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a transistor with high reliability, etc.) can be realized.

[0212] The composition of the metal oxide used in the oxide semiconductor 230 can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0213] [c-axis orientation rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using crystal orientation, for example.

[0214] The crystal orientation can be obtained from the Fast Fourier Transform (FFT) pattern obtained by FFT processing of the TEM image. Specifically, the direction of the crystal axis can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice space information similar to that of the electron diffraction pattern.

[0215] By performing FFT processing for each region in the TEM image of the oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having a layered crystal part. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0216] The c-axis orientation rate can be calculated by calculating the ratio of c-axis oriented regions in a map showing crystal orientation. Note that the c-axis oriented regions are defined here as regions whose orientation coincides with the c-axis and regions whose orientation differs from the c-axis by 20° or less.

[0217] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by TEM observation of a cross section or a plan view of the oxide semiconductor layer. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0218] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0219] The c-axis orientation rates of the region formed as the oxide semiconductor 230a, the region formed as the oxide semiconductor 230b, and the region formed as the oxide semiconductor 230c are Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are each 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0220] Note that after the oxide semiconductor 230 is formed, the boundaries between the oxide semiconductors 230a, 230b, and 230c may not be clearly observed.

[0221] The oxide semiconductor 230 of one embodiment of the present invention can be divided into three regions, a first region, a second region, and a third region, starting from the top of the layer 229. Each region has a layer shape.

[0222] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rate of each of the second region and the third region is 80% or more, more preferably 90% or more, and even more preferably 95% or more.

[0223] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the oxide semiconductor 230 .

[0224] Or, the layer thickness in each region may be, for example, approximately the same.

[0225] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in the case where a plurality of configuration examples are shown in one embodiment mode in this specification, the configuration examples can be combined as appropriate.

[0226] (Embodiment 3) In this embodiment, a configuration example of a semiconductor device 1000 including a memory cell 10 (also called a "memory element") will be described.

[0227] 13A is a block diagram illustrating a configuration example of a semiconductor device 1000 according to one embodiment of the present invention. The semiconductor device 1000 illustrated in FIG 13A includes a driver circuit 300 and a memory array 400. The memory array 400 includes a plurality of memory cells 10. FIG 13A illustrates an example in which the memory array 400 includes a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers equal to or greater than 2).

[0228] The rows and columns extend in directions perpendicular to each other. In this embodiment, the X direction is defined as the "rows" and the Y direction is defined as the "columns", but the X direction may be defined as the "columns" and the Y direction as the "rows".

[0229] 13A, the memory cell 10 in the first row and first column is indicated as memory cell 10[1,1], the memory cell 10 in the mth row and nth column is indicated as memory cell 10[m,n], and the memory cell 10 in the ith row and jth column (i is an integer between 1 and m, and j is an integer between 1 and n) is indicated as memory cell 10[i,j].

[0230] The drive circuit 300 includes a PSW 341 (power switch), a PSW 342, and a peripheral circuit 315. The peripheral circuit 315 includes a peripheral circuit 311, a control circuit 312, and a voltage generating circuit 328.

[0231] In the semiconductor device 1000, each circuit, each signal, and each voltage can be appropriately selected or omitted as necessary. Alternatively, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0232] Moreover, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 312.

[0233] The control circuit 312 is a logic circuit having a function of controlling the overall operation of the semiconductor device 1000. For example, the control circuit 312 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 1000. Alternatively, the control circuit 312 generates a control signal for the peripheral circuit 311 so that this operation mode is executed.

[0234] The voltage generating circuit 328 has a function of generating a voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 328. For example, when an H-level signal is provided to the signal WAKE, the signal CLK is input to the voltage generating circuit 328, and the voltage generating circuit 328 generates a voltage.

[0235] The peripheral circuit 311 is a circuit for writing and reading data to and from the memory cells 10. The peripheral circuit 311 includes a row decoder 321, a column decoder 322, a row driver 323, a column driver 324, an input circuit 325, an output circuit 326, and a sense amplifier 327.

[0236] The row decoder 321 and the column decoder 322 have a function of decoding the signal ADDR. The row decoder 321 is a circuit for specifying a row to be accessed, and the column decoder 322 is a circuit for specifying a column to be accessed. The row driver 323 has a function of selecting a wiring specified by the row decoder 321. The column driver 324 has a function of writing data to the memory cell 10, a function of reading data from the memory cell 10, a function of holding the read data, and the like.

[0237] The input circuit 325 has a function of holding a signal WDA. The data held by the input circuit 325 is output to the column driver 324. The output data of the input circuit 325 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 324 is output to the output circuit 326. The output circuit 326 has a function of holding Dout. In addition, the output circuit 326 has a function of outputting Dout to the outside of the semiconductor device 1000. The data output from the output circuit 326 is a signal RDA.

[0238] PSW341 is the V to the peripheral circuit 315 DD The PSW 342 has the function of controlling the supply of V HM In this embodiment, the high power supply voltage of the semiconductor device 1000 is V DD and the low power supply voltage is GND (ground potential). Also, V HM is the high power supply voltage used to drive the word line high, and V DD 13A, in the peripheral circuit 315, V DD Although the number of power domains to which the power is supplied is set to one, it is also possible to set it to multiple. In this case, a power switch may be provided for each power domain.

[0239] The driving circuit 300 and the memory array 400 may be provided on the same plane. Also, as shown in FIG. 13B, the driving circuit 300 and the memory array 400 may be provided so as to overlap each other. By providing the driving circuit 300 and the memory array 400 so as to overlap each other, the signal propagation distance can be shortened. Also, the semiconductor device 1000 can be made smaller.

[0240] 13C, a plurality of memory arrays 400 may be stacked on the driver circuit 300. By stacking a plurality of memory arrays 400 on the driver circuit 300, the storage capacity per unit area can be increased.

[0241] 14A is a block diagram illustrating an example of the arrangement of memory cells 10 in a memory array 400. The memory array 400 includes m wirings WBL and m wirings RBL extending in the row direction, and n wirings WWL, n wirings SL, n wirings BGL, and n wirings RWL extending in the column direction (not shown).

[0242] 14B is a circuit diagram of the memory cell 10[i,j]. The memory cell 10[i,j] includes a transistor VT2[i,j] and a transistor VT1[i,j]. The gate of the transistor VT2[i,j] is connected to the wiring WWL[j], which is the wiring WWL in the jth column, and the back gate is connected to the wiring BGL[j], which is the wiring BGL in the jth column. In addition, one of the source or drain of the transistor VT2[i,j] is connected to the wiring WBL[i], which is the wiring WBL in the ith row, and the other is connected to the gate of the transistor VT1[i,j].

[0243] The back gate of the transistor VT1[i,j] is connected to the wiring RWL[j], which is the wiring RWL in the jth column. One of the source or drain of the transistor VT1[i,j] is connected to the wiring RBL[i], which is the wiring RBL in the ith row, and the other is connected to the wiring SL[j], which is the wiring SL in the jth column.

[0244] The memory cell 10[i,j] also includes a node FN[i,j], which is a node where the other of the source or drain of the transistor VT2[i,j] and the gate of the transistor VT1[i,j] are connected.

[0245] By supplying signals to the wiring WBL[i] and the wiring WWL[j], information can be written to the memory cell 10[i,j]. In addition, by supplying signals to the wiring RBL[i] and the wiring RWL[j], information stored in the memory cell 10[i,j] can be read. By controlling the signals supplied to each wiring, information can be read from and written to any memory cell 10. Thus, the semiconductor device 1000 can function as a NOR type memory device.

[0246] FIG. 15A is a block diagram illustrating an example of an arrangement of memory cells 10 in a memory array 400 that is different from that shown in FIG.

[0247] In the memory array 400 shown in FIG. 15(A), the memory cells 10 in the odd columns and the memory cells 10 in the even columns are arranged symmetrically. FIG. 15(B) shows a circuit diagram of the memory cells 10[i,j] and the memory cells 10[i,j+1] when j is an odd number. Either the source or the drain of the transistor VT2[i,j] and either the source or the drain of the transistor VT2[i,j+1] are both connected to the wiring WBL[i]. By arranging the memory cells 10 in the odd columns and the memory cells 10 in the even columns symmetrically, both the transistor VT2[i,j] and the transistor VT2[i,j+1] can be connected to the wiring WBL[i] via a common connection path.

[0248] Similarly, both the transistor VT1[i,j] and the transistor VT1[i,j+1] can be connected to the wiring RBL[i] via a common connection path. This further reduces the area occupied by the memory array 400. In addition, the recording density per unit area can be further increased.

[0249] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0250] (Embodiment 4) In this embodiment, application examples of a storage device according to one embodiment of the present invention will be described.

[0251] Generally, various memory devices are used in semiconductor devices such as computers depending on the application. Figure 16 shows various memory devices by hierarchy. The higher the layer, the faster the access speed is required for the memory device, and the lower the layer, the larger the memory capacity and the higher the recording density are required for the memory device. Figure 16 shows, from the top layer, memory integrated as a register in a processor such as a CPU, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0252] The memory embedded as a register in a processor such as a CPU is used for temporary storage of calculation results, and is accessed frequently by the processor. Therefore, a faster operating speed is required rather than a larger memory capacity. The register also has the function of storing setting information for the processor.

[0253] SRAM is used, for example, in caches. A cache has the function of storing a copy of some of the information stored in the main memory. By storing a copy of frequently used data in the cache, the speed of accessing the data can be increased.

[0254] DRAM is used, for example, as a main memory. The main memory has a function of holding programs or data read from a storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 It is.

[0255] 3D NAND memory is used, for example, in storage. Storage has the function of holding data that needs to be stored for a long time, various programs used in processing units, etc. Therefore, storage requires a larger memory capacity and a higher recording density than the operating speed. The recording density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm 2 It is.

[0256] The storage device according to one embodiment of the present invention is excellent in that it has a high operating speed, is capable of retaining data for a long period of time, has high rewrite endurance, and can be driven at a low voltage. The storage device according to one embodiment of the present invention can be suitably used as a storage device located in a boundary area 901 that includes both a hierarchical level where the main memory is located and a hierarchical level where the storage is located.

[0257] A storage device according to one embodiment of the present invention can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book terminals, digital still cameras, video cameras, recording / playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, IoT (Internet of Things), healthcare-related devices, etc. Note that the term "computer" as used herein includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0258] Moreover, the storage device according to one embodiment of the present invention is applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives). Figures 17(A) to 17(E) are schematic diagrams showing some configuration examples of removable storage devices. For example, the storage device according to one embodiment of the present invention is processed into a packaged memory chip and used in various storage devices and removable memories.

[0259] 17A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1105 of the board 1104.

[0260] FIG. 17B is a schematic diagram of the appearance of an SD card, and FIG. 17C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113 as well. In addition, a wireless chip having a wireless communication function may be provided on the substrate 1113. This enables data to be read from and written to the memory chip 1114 by wireless communication between a host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1114 of the substrate 1113 or the like.

[0261] FIG. 17(D) is a schematic diagram of the appearance of the SSD, and FIG. 17(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a board 1153. The board 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the board 1153. The memory chip 1155 is a work memory for the controller chip 1156, and may be, for example, a DOSRAM chip. The capacity of the SSD 1150 can be increased by providing a memory chip 1154 on the back side of the board 1153. The semiconductor device shown in the above embodiment can be incorporated into the memory chip 1154 of the board 1153.

[0262] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0263] (Embodiment 5) FIG. 18 illustrates a specific example of an electronic device including a semiconductor device according to one embodiment of the present invention.

[0264] <Electronic equipment and systems> The semiconductor device according to one embodiment of the present invention can be mounted on various electronic devices. Examples of the electronic devices include electronic devices with relatively large screens, such as television devices, monitors for desktop or notebook information terminals, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, portable information terminals, and audio playback devices. The semiconductor device according to one embodiment of the present invention can be used as a component of artificial intelligence. Artificial intelligence can be mounted on electronic devices using the semiconductor device according to one embodiment of the present invention.

[0265] An electronic device according to one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, an image or information can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0266] An electronic device according to one embodiment of the present invention may have a sensor (including a function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0267] An electronic device according to an embodiment of the present invention can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out a program or data recorded on a recording medium, etc.

[0268] [Information terminal] 18A illustrates a mobile phone (smartphone), which is one type of information terminal. The information terminal 5100 includes a housing 5101 and a display unit 5102. As an input interface, a touch panel is provided on the display unit 5102, and buttons are provided on the housing 5101.

[0269] The information terminal 5100 can execute applications using artificial intelligence using the semiconductor device according to one embodiment of the present invention. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display portion 5102, an application that recognizes characters, figures, or the like input by a user to a touch panel included in the display portion 5102 and displays them on the display portion 5102, and an application that performs biometric authentication such as a fingerprint or voiceprint.

[0270] 18B illustrates a notebook type information terminal 5200. The notebook type information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0271] The notebook information terminal 5200 can execute an application using artificial intelligence using a semiconductor device according to one embodiment of the present invention, similarly to the above-described information terminal 5100. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. In addition, new artificial intelligence can be developed by using the notebook information terminal 5200.

[0272] In the above description, a smartphone and a notebook type information terminal are shown as examples of electronic devices in Fig. 18(A) and Fig. 18(B), respectively, but information terminals other than smartphones and notebook type information terminals can also be applied. Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.

[0273] [Game consoles] FIG. 18C illustrates a portable game machine 5300, which is an example of a game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, an operation key 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. By attaching the connection portion 5305 of the housing 5301 to another housing (not shown), a video output to the display portion 5304 can be output to another video device (not shown). In this case, the housing 5302 and the housing 5303 can each function as an operation portion. This allows a plurality of players to play a game at the same time. A semiconductor device according to one embodiment of the present invention can be incorporated into chips provided on substrates of the housing 5301, the housing 5302, and the housing 5303.

[0274] 18D shows a stationary game machine 5400, which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.

[0275] A game machine with low power consumption can be realized by applying a GPU or a chip of one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Furthermore, low power consumption can reduce heat generation from a circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

[0276] Furthermore, the portable game console 5300 can have artificial intelligence by using a semiconductor device according to one embodiment of the present invention.

[0277] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game device 5300, it becomes possible to express things that are not limited to the program of the game. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0278] In addition, when playing a game on the portable game console 5300 that requires multiple players, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent a game player based on artificial intelligence.

[0279] 18C and 18D show a portable game machine and a stationary game machine as examples of game machines, but the game machines to which the semiconductor device according to one embodiment of the present invention can be applied are not limited to these. Examples of game machines to which the semiconductor device according to one embodiment of the present invention can be applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0280] [Mainframe computers] A semiconductor device according to one embodiment of the present invention can be applied to a large-scale computer.

[0281] 18(E) is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 18(F) is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0282] A supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. Note that the plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and a semiconductor device according to one embodiment of the present invention can be mounted on the board.

[0283] The supercomputer 5500 is a large-scale computer mainly used for scientific and technological calculations. In scientific and technological calculations, huge amounts of calculations need to be processed at high speed, and therefore power consumption is high and chips generate a lot of heat. By applying a semiconductor device according to one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. Furthermore, low power consumption can reduce heat generation from a circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

[0284] 18(E) and 18(F) illustrate a supercomputer as an example of a large computer, but the large computer to which the semiconductor device according to one embodiment of the present invention is applied is not limited to this. Examples of large computers to which the semiconductor device according to one embodiment of the present invention is applied include computers (servers) that provide services and large general-purpose computers (mainframes).

[0285] [Mobile object] A semiconductor device according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the vicinity of a driver's seat of an automobile.

[0286] Fig. 18(G) is a diagram showing the periphery of a windshield in the interior of an automobile 5600, which is an example of a moving body. Fig. 18(G) shows a display panel 5601, a display panel 5602, and a display panel 5603 attached to the dashboard, as well as a display panel 5604 attached to a pillar.

[0287] The display panels 5601 to 5603 can provide various information by displaying a speedometer or tachometer, mileage, fuel gauge, gear status, air conditioner settings, etc. In addition, the display items or layouts displayed on the display panels can be changed as appropriate according to the user's preferences, and the design can be improved. The display panels 5601 to 5603 can also be used as lighting devices.

[0288] The display panel 5604 can complement the field of view (blind spot) blocked by the pillar by displaying an image from an imaging device (not shown) installed in the vehicle. That is, by displaying an image from an imaging device installed outside the vehicle, blind spots can be complemented and safety can be improved. In addition, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5604 can also be used as a lighting device.

[0289] Since the semiconductor device according to one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system for automobiles. The chip can also be used in a system that performs road guidance, risk prediction, etc. The display panels 5601 to 5604 may be configured to display information such as road guidance and risk prediction.

[0290] In the above description, an automobile is described as an example of a moving object, but the moving object is not limited to an automobile. For example, the moving object may be a train, a monorail, a ship, or an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), and the like. A semiconductor device according to one embodiment of the present invention may be applied to these moving objects to provide them with a system using artificial intelligence.

[0291] [electric appliances] 18H shows an example of an electric appliance, an electric refrigerator-freezer 5700. The electric refrigerator-freezer 5700 includes a housing 5701, a door for a refrigerator compartment 5702, a door for a freezer compartment 5703, and the like.

[0292] An electric refrigerator-freezer 5700 having artificial intelligence can be realized by using the semiconductor device according to one embodiment of the present invention in the electric refrigerator-freezer 5700. By using artificial intelligence, the electric refrigerator-freezer 5700 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5700 and the expiration dates of the ingredients, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5700, and the like.

[0293] Although an electric refrigerator-freezer has been described as an example of an electrical appliance, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water servers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0294] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof described in this embodiment can be appropriately combined with the descriptions of other electronic devices.

[0295] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0296] <Additional notes regarding the present specification etc.> The above embodiment and each configuration in the embodiment will be described below with additional notes.

[0297] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0298] In addition, the content (or a part of the content) described in one embodiment can be applied to, combined with, or replaced by another content (or a part of the content) described in that embodiment, and / or the content (or a part of the content) described in one or more other embodiments.

[0299] The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

[0300] In addition, a figure (or a part thereof) described in one embodiment can be combined with another part of that figure, with another figure (or a part thereof) described in that embodiment, and / or with a figure (or a part thereof) described in one or more other embodiments to form even more figures.

[0301] In addition, in the present specification and the like, in the block diagrams, the components are classified by function and shown as mutually independent blocks. However, in actual circuits and the like, it is difficult to separate the components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and may be rephrased appropriately according to the situation.

[0302] In addition, in the drawings, the size, layer thickness, or region are shown at an arbitrary size for convenience of explanation. Therefore, they are not necessarily limited to the scale. Note that the drawings are shown diagrammatically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0303] In this specification, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0304] In this specification and elsewhere, "parallel" refers to, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. This therefore includes cases in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" and "orthogonal" refer to, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This therefore includes cases in which the angle is 85° or more and 95° or less.

[0305] In addition, ordinal numbers such as "first" and "second" in this specification are used to avoid confusion of components, and do not indicate any order or ranking, such as a process order or a stacking order. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion of components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0306] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0307] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed.

[0308] In addition, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage is a potential difference from a reference potential, and if the reference potential is a ground voltage (earth voltage), for example, voltage can be interchanged with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential applied to wiring, etc. may be changed depending on the reference potential.

[0309] In this specification and the like, the terms "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer".

[0310] In this specification, a switch refers to a device that has a function of controlling whether a current flows or not by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0311] In this specification, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically short-circuited (also referred to as a "conductive state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically disconnected (also referred to as a "non-conductive state").

[0312] In this specification, the term "on-state current" may refer to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" may refer to a current that flows between a source and a drain when a transistor is off.

[0313] In this specification, the channel length of a planar transistor refers to, for example, a distance between the source and drain in a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap in a top view of the transistor, or in a region where a channel is formed.

[0314] In this specification, the channel width refers to, for example, the length of the region where a semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and a gate electrode overlap, or the length of the portion where a source and a drain face each other in a region in which a channel is formed.

[0315] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit configuration, a device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0316] In this specification, A and B are connected means that A and B are electrically connected. Here, A and B are electrically connected means a connection in which an electrical signal between A and B can be transmitted when an object (an element such as a switch, a transistor element, or a diode, or a circuit including the element and wiring) exists between A and B. Note that when A and B are electrically connected, this includes a case in which A and B are directly connected. Here, A and B are directly connected means a connection in which an electrical signal between A and B can be transmitted through wiring (or electrodes) between A and B without passing through the object. In other words, a direct connection means a connection that can be regarded as the same circuit diagram when expressed as an equivalent circuit. [Explanation of symbols]

[0317] BGL wiring CS Capacitor FN Node RBL Wiring RWL wiring SL Wiring TGE First gate electrode BGE Second gate electrode TSD top electrode BSD bottom electrode VT Transistor WBL Wiring WWL Wiring 10 Memory Cells 110 Conductive layer 120 Conductive layer 130 Conductive layer 140 Conductive layer 150 Oxide semiconductor layer 160 Insulating layer 170 Insulating layer 181 Insulating Layer 182 Opening 183 Insulating Layer 400 Memory Array

Claims

1. A memory cell having a first transistor and a second transistor, the first transistor includes a first oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, and a second insulating layer; the second transistor includes a second oxide semiconductor layer, the first conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, a third insulating layer, and a fourth insulating layer; the first oxide semiconductor layer has, in a plan view, a region that faces the first conductive layer with the first insulating layer interposed therebetween and a region that faces the second conductive layer with the second insulating layer interposed therebetween; the second oxide semiconductor layer has, in a plan view, an overlapping region that faces the fifth conductive layer with the third insulating layer interposed therebetween and a region that faces the sixth conductive layer with the fourth insulating layer interposed therebetween; the first oxide semiconductor layer is provided in contact with the third conductive layer and the fourth conductive layer; the second oxide semiconductor layer is provided in contact with the first conductive layer and the seventh conductive layer; the third conductive layer has an area overlapping with the first conductive layer, the second conductive layer, the fourth conductive layer, the fifth conductive layer, the sixth conductive layer, and the seventh conductive layer in a cross-sectional view; a first potential applied to the second conductive layer during a period in which data is written to the memory cell is higher than a second potential applied to the second conductive layer during a period in which the data is held in the memory cell; a third potential applied to the sixth conductive layer during a period in which the data is read from the memory cell is higher than a fourth potential applied to the sixth conductive layer during a period in which the data is held in the memory cell; the third potential is lower than the first potential; The fourth potential is lower than the second potential. storage device.

2. In claim 1, The memory cell includes a capacitor. One electrode of the capacitor is electrically connected to the first conductive layer. storage device.

3. In claim 2, the other electrode of the capacitor is electrically connected to the sixth conductive layer; storage device.

4. In claim 1, The first insulating layer or the second insulating layer contains hafnium, zirconium, and oxygen. storage device.

5. In claim 1, each of the first oxide semiconductor layer and the second oxide semiconductor layer contains at least indium; storage device.

Images