Power amplifier circuit

Abstract

To suppress deterioration in output characteristics.SOLUTION: A power amplifier circuit includes: a first transistor formed on a semiconductor substrate; a second transistor which is formed on the semiconductor substrate, has a base to which a first current being a part of a control current is supplied, and supplies a bias current based on the first current to the first transistor; a third transistor which is formed on the semiconductor substrate, has a collector to which a second current being a part of the control current is supplied, and outputs a third current based on the second current from an emitter; a first metal member electrically connected to the emitter of the first transistor and disposed so as to overlap a first arrangement region in which the first transistor is disposed in a plan view of the semiconductor substrate; and a second metal member electrically connected to the emitter of the third transistor. The third transistor is disposed so as to overlap the first metal member in a plan view.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a power amplifier circuit. [Background technology]

[0002] Patent Document 1 describes a power amplifier circuit that can mitigate the effects of stress. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-125870 A Summary of the Invention [Problem to be solved by the invention]

[0004] Amplification transistors generate heat when a bias is applied or when high-frequency signals are amplified. When an amplification transistor generates heat, the threshold of the base-emitter voltage fluctuates, the operating point fluctuates, the gain fluctuates, and linearity is affected. As a result, the output characteristics of the power amplifier circuit deteriorates.

[0005] The power amplifier circuit described in Patent Document 1 takes into consideration that the amplifying transistor and the biasing transistor are subjected to stress, but does not take into consideration that the amplifying transistor generates heat.

[0006] The present invention has been made in view of the above, and has an object to suppress deterioration of the output characteristics of a power amplifier circuit. [Means for solving the problem]

[0007] A power amplifier circuit according to one aspect of the present disclosure includes a first transistor formed on a semiconductor substrate, a second transistor formed on the semiconductor substrate, a base of which is supplied with a first current that is a part of a control current, and a bias current based on the first current, the third transistor formed on the semiconductor substrate, a collector of which is supplied with a second current that is a part of the control current, and an emitter of which outputs a third current based on the second current, a first metal member electrically connected to the emitter of the first transistor and provided so as to overlap a first arrangement region in which the first transistor is arranged in a plan view of the semiconductor substrate, and a second metal member electrically connected to the emitter of the third transistor. The third transistor is provided so as to overlap the first metal member in a plan view. Effect of the Invention

[0008] According to the present disclosure, it is possible to suppress deterioration of the output characteristics of a power amplifier circuit. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a circuit configuration of a power amplifier circuit according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing a layout of the power amplifier circuit according to the first embodiment. [Diagram 3] FIG. 3 is a cross-sectional view of the power amplifier circuit according to the first embodiment. [Figure 4] FIG. 4 is a diagram illustrating a circuit configuration of a power amplifier circuit according to the second embodiment. [Diagram 5] FIG. 5 is a diagram showing a layout of the power amplifier circuit according to the second embodiment. [Figure 6] FIG. 6 is a diagram illustrating a circuit configuration of a power amplifier circuit according to the third embodiment. [Figure 7] FIG. 7 is a diagram showing a layout of the power amplifier circuit according to the third embodiment. [Figure 8] FIG. 8 is a diagram illustrating a circuit configuration of a power amplifier circuit according to the fourth embodiment. [Figure 9]FIG. 9 is a diagram showing a layout of the power amplifier circuit according to the fourth embodiment. [Figure 10] FIG. 10 is a cross-sectional view of a power amplifier circuit according to the fourth embodiment. [Figure 11] FIG. 11 is a diagram showing a layout of the power amplifier circuit according to the fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the present invention is not limited to these embodiments. Each embodiment is an example, and it goes without saying that partial replacement or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, a description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0011] <First embodiment> (Circuit configuration) 1 is a diagram showing a circuit configuration of a power amplifier circuit according to a first embodiment of the present invention. The power amplifier circuit 1 amplifies a high-frequency signal RFin and outputs a high-frequency signal RFout.

[0012] The power amplifier circuit 1 includes an input matching circuit 11, a first-stage (driver stage) amplifying transistor 12, a bias circuit 13, an inter-stage matching circuit 14, a final-stage (power stage) amplifying transistor 15, a bias circuit 16, and an output matching circuit 17.

[0013] Each of the amplification transistor 12 and the amplification transistor 15 corresponds to an example of a "first transistor" in the present disclosure.

[0014] Each transistor is a bipolar transistor, but the present disclosure is not limited thereto. The transistor may be, for example, a field effect transistor. An example of a bipolar transistor is a heterojunction bipolar transistor (HBT), but the present disclosure is not limited thereto. The transistor may be a multi-finger transistor in which a plurality of unit transistors are electrically connected in parallel. A unit transistor refers to the minimum configuration that constitutes a transistor.

[0015] When each transistor is a field effect transistor, the source corresponds to the emitter of the bipolar transistor, the gate corresponds to the base of the bipolar transistor, and the drain corresponds to the collector of the bipolar transistor.

[0016] In the embodiment, each of the amplifying transistor 12 and the amplifying transistor 15 is a multi-finger transistor, but the present disclosure is not limited to this. Each of the amplifying transistor 12 and the amplifying transistor 15 may be a unit transistor.

[0017] In the embodiment, the number of stages of the power amplifier circuit 1 is two, but the present disclosure is not limited to this. The number of stages of the power amplifier circuit 1 may be one, or three or more.

[0018] A radio frequency signal RFin is input to one end of the input matching circuit 11. The other end of the input matching circuit 11 is electrically connected to the base of the amplifying transistor 12. The radio frequency signal RFin that has passed through the input matching circuit 11 is input to the base of the amplifying transistor 12.

[0019] The bias circuit 13 provides a bias to the amplifier transistor 12. The bias circuit 13 includes transistors 21 to 23.

[0020] The transistor 23 corresponds to an example of a "second transistor" in the present disclosure. The transistor 22 corresponds to an example of a "third transistor" in the present disclosure. The transistor 21 corresponds to an example of a "fifth transistor" in the present disclosure.

[0021] In the embodiment, each of the transistors 21 to 23 is a unit transistor, but the present disclosure is not limited to this. Each of the transistors 21 to 23 may be a multi-finger transistor.

[0022] The collector and base of the transistor 21 are electrically connected to the node N11. That is, the transistor 21 is diode-connected. The emitter of the transistor 21 is electrically connected to the collector and base of the transistor 22. That is, the transistor 22 is diode-connected. Instead of the transistors 21 and 22, a transistor having a feedback circuit provided between the base and collector may be used. The emitter of the transistor 22 is electrically connected to a bump BMP21 (described later). The bump BMP21 is electrically connected to a reference potential. That is, the emitter of the transistor 22 is electrically connected to the reference potential via the bump BMP21. The reference potential is exemplified by a ground potential, but the present disclosure is not limited thereto.

[0023] The base of the transistor 23 is electrically connected to the node N11. The collector of the transistor 23 is electrically connected to the power supply potential Vcc1 and receives power. The emitter of the transistor 23 is electrically connected to one end of the resistor 53. That is, the transistor 23 and the resistor 53 are connected in an emitter-follower fashion. The other end of the resistor 53 is electrically connected to the base of the amplifying transistor 12.

[0024] A current I11 is input to the node N11 from a current source 51. The current I11 is divided into a current I12 and a current I13. That is, I11=I12+I13.

[0025] The current I11 corresponds to an example of a "control current" in the present disclosure. The current I13 corresponds to an example of a "first current" in the present disclosure.

[0026] A current I12 is input to the collector and base of the transistor 21. The transistor 21 outputs a current I14 from the emitter to the collector and base of the transistor 22. That is, I12=I14. The transistor 22 outputs a current I15 from the emitter to the bump BMP21. That is, I14=I15. The transistors 21 and 22 generate a voltage at the node N11.

[0027] The current I14 corresponds to an example of the "second current" in the present disclosure. The current I15 corresponds to an example of the "third current" in the present disclosure.

[0028] The transistor 23 outputs a current I16 corresponding to the current I13 to the base of the amplifying transistor 12 via the resistor 53. The base of the amplifying transistor 12 is biased by the current I16. That is, the current I16 is a base bias current of the amplifying transistor 12.

[0029] The emitter of the amplifying transistor 12 is electrically connected to a bump BMP11 (described later). The bump BMP11 is electrically connected to a reference potential. That is, the emitter of the amplifying transistor 12 is electrically connected to the reference potential via the bump BMP11. The collector of the amplifying transistor 12 is electrically connected to a power supply potential Vcc2 via a choke coil 55, and is supplied with power. In addition, the collector of the amplifying transistor 12 is electrically connected to one end of the inter-stage matching circuit 14. The amplifying transistor 12 amplifies a high-frequency signal RFin input to its base, and outputs the amplified high-frequency signal RF1 from the collector to one end of the inter-stage matching circuit 14.

[0030] The other end of the inter-stage matching circuit 14 is electrically connected to the base of the amplifying transistor 15. The radio frequency signal RF1 that has passed through the inter-stage matching circuit 14 is input to the base of the amplifying transistor 15.

[0031] The bias circuit 16 provides a bias to the amplifying transistor 15. The bias circuit 16 includes transistors 31 to 33.

[0032] The transistor 33 corresponds to an example of a "second transistor" in the present disclosure. The transistor 32 corresponds to an example of a "third transistor" in the present disclosure. The transistor 31 corresponds to an example of a "fifth transistor" in the present disclosure.

[0033] In the embodiment, each of the transistors 31 to 33 is a unit transistor, but the present disclosure is not limited to this. Each of the transistors 31 to 33 may be a multi-finger transistor.

[0034] The collector and base of the transistor 31 are electrically connected to the node N21. That is, the transistor 31 is diode-connected. The emitter of the transistor 31 is electrically connected to the collector and base of the transistor 32. That is, the transistor 32 is diode-connected. Instead of the transistors 31 and 32, a transistor having a feedback circuit provided between the base and collector may be used. The emitter of the transistor 32 is electrically connected to a bump BMP21 (described later). The bump BMP21 is electrically connected to a reference potential. That is, the emitter of the transistor 32 is electrically connected to the reference potential via the bump BMP21.

[0035] The base of the transistor 33 is electrically connected to the node N21. The collector of the transistor 33 is electrically connected to the power supply potential Vcc3 and is supplied with power. The emitter of the transistor 33 is electrically connected to one end of the resistor 54. That is, the transistor 33 and the resistor 54 are connected in an emitter-follower manner. The other end of the resistor 54 is electrically connected to the base of the amplifying transistor 15.

[0036] A current I21 is input to node N21 from a current source 52. The current I21 is divided into a current I22 and a current I23. That is, I21=I22+I23.

[0037] The current I21 corresponds to an example of a "control current" in the present disclosure. The current I23 corresponds to an example of a "first current" in the present disclosure.

[0038] A current I22 is input to the collector and base of transistor 31. Transistor 31 outputs a current I24 from the emitter to the collector and base of transistor 32. That is, I22=I24. Transistor 32 outputs a current I25 from the emitter to bump BMP21. That is, I24=I25. Transistors 31 and 32 generate a voltage at node N21.

[0039] The current I24 corresponds to an example of the "second current" in the present disclosure. The current I25 corresponds to an example of the "third current" in the present disclosure.

[0040] The transistor 33 outputs a current I26 corresponding to the current I23 to the base of the amplifying transistor 15 via the resistor 54. The base of the amplifying transistor 15 is biased by the current I26. That is, the current I26 is the base bias current of the amplifying transistor 15.

[0041] The emitter of the amplifying transistor 15 is electrically connected to a bump BMP12 (described later). The bump BMP12 is electrically connected to a reference potential. That is, the emitter of the amplifying transistor 15 is electrically connected to the reference potential via the bump BMP12. The collector of the amplifying transistor 15 is electrically connected to a power supply potential Vcc4 via a choke coil 56, and power is supplied to the collector of the amplifying transistor 15. The collector of the amplifying transistor 15 is electrically connected to one end of an output matching circuit 17. The amplifying transistor 15 amplifies a high-frequency signal RF1 input to the base, and outputs the amplified high-frequency signal RFout from the collector to one end of the output matching circuit 17. The high-frequency signal RFout is output from the other end of the output matching circuit 17.

[0042] (Layout) Fig. 2 is a diagram showing the layout of the power amplifier circuit of the first embodiment. The power amplifier circuit 1 is formed on a semiconductor substrate 71. Fig. 2 is a plan view of the semiconductor substrate 71 as viewed from a direction perpendicular to the main surface. Note that Fig. 2 omits the illustration of a region in which an output matching circuit 17 is formed.

[0043] A bias circuit region 81 is provided along the left side of the semiconductor substrate 71 in the figure (the side on the base end side of the X-axis and along the Y-axis). The bias circuit region 81 has a longitudinal direction along the Y-axis direction and a lateral direction along the X-axis direction. The bias circuit region 81 is a region in which the transistors 21 and 23 in the bias circuit 13 and the transistors 31 and 33 in the bias circuit 16 are formed.

[0044] A bump BMP21 is formed on the upper layer (the layer on the front side of the paper surface) approximately in the center of the bias circuit region 81 via an insulating layer (described later).

[0045] The bump BMP21 corresponds to an example of a "second metal member" in the present disclosure.

[0046] The bumps BMP21 may be made of, for example, copper (Cu), but may also be made of low-resistance metal materials such as aluminum (Al) and gold (Au) in addition to copper.

[0047] An under bump metal (UBM) may be formed between the insulating layer and the bump BMP 21. The under bump metal is formed of a material containing at least one of Ti, Cr, Cu, Au, Ni, and Pd, for example.

[0048] An input matching circuit region 82 is provided on the right side (X-axis direction) of the upper part of the bias circuit region 81 in the figure (the portion on the base end side of the Y-axis). The longitudinal direction of the input matching circuit region 82 is the X-axis direction, and the lateral direction is the Y-axis direction. The input matching circuit region 82 is a region in which the input matching circuit 11 is formed.

[0049] Region 83 is provided to the right (X-axis direction side) of the center (center in the Y-axis direction) of the bias circuit region 81 in the figure, and below (Y-axis direction side) the input matching circuit region 82 in the figure. The longitudinal direction of region 83 is the X-axis direction, and the lateral direction is the Y-axis direction. A transistor 22 and a plurality of unit transistors 12a are formed in region 83. The plurality of unit transistors 12a constitute the amplifying transistor 12.

[0050] Region 83 corresponds to an example of a "first placement region" in the present disclosure.

[0051] A transistor 22 is formed along the left side of region 83 in the figure (the side on the base end side along the X-axis). A plurality of unit transistors 12a are formed on the right side of transistor 22 in the figure (the side along the X-axis). The longitudinal direction of each of transistor 22 and the plurality of unit transistors 12a is the Y-axis direction, and the lateral direction is the X-axis direction. The transistor 22 and the plurality of unit transistors 12a are arranged in the longitudinal direction of region 83 (the X-axis direction).

[0052] The emitter of the transistor 22 is electrically connected to a bump BMP21 via a wiring 91 formed on the semiconductor substrate 71.

[0053] A bump BMP11 is formed on an upper layer (the layer on the front side of the paper) of region 83 via an insulating layer (described later). In plan view, bump BMP11 overlaps region 83 (transistor 22 and a plurality of unit transistors 12a). Here, plan view refers to viewing semiconductor substrate 71 in a direction perpendicular to the main surface of semiconductor substrate 71 (the direction opposite to the Z-axis direction).

[0054] The bump BMP11 corresponds to an example of a "first metal member" in the present disclosure.

[0055] The bumps BMP11 are, for example, made of copper (Cu), but may also be made of low-resistance metal materials such as aluminum (Al) and gold (Au) other than copper.

[0056] An under-bump metal may be formed between the insulating layer and the bump BMP11.

[0057] The emitters of the unit transistors 12a are electrically connected to a bump BMP11 through vias (described later).

[0058] An interstage matching circuit region 84 is provided to the right (X-axis direction side) of the lower part (Y-axis side part) of the bias circuit region 81 in the figure, and also below the region 83 in the figure (Y-axis direction side). The longer side of the interstage matching circuit region 84 is the X-axis direction, and the shorter side is the Y-axis direction. The interstage matching circuit 14 is formed in the interstage matching circuit region 84.

[0059] A region 85 is provided below the bias circuit region 81 and the inter-stage matching circuit region 84 in the figure (on the Y-axis direction). The longitudinal direction of the region 85 is the X-axis direction, and the lateral direction is the Y-axis direction. A transistor 32 and a plurality of unit transistors 15a are formed in the region 85. The plurality of unit transistors 15a constitute the amplifying transistor 15.

[0060] Region 85 corresponds to an example of a "first placement region" in the present disclosure.

[0061] A transistor 32 is formed along the left side of region 85 in the figure (the side on the base end side along the X-axis). A plurality of unit transistors 15a are formed on the right side of transistor 32 in the figure (X-axis direction). The longitudinal direction of each of transistor 32 and the plurality of unit transistors 15a is the Y-axis direction, and the lateral direction is the X-axis direction. The transistor 32 and the plurality of unit transistors 15a are arranged in the longitudinal direction of region 85 (X-axis direction).

[0062] The emitter of the transistor 32 is electrically connected to the bump BMP21 via a wiring 92 formed on the semiconductor substrate 71.

[0063] A bump BMP12 is formed on an upper layer (the layer on the front side of the paper) of region 85 via an insulating layer (described later). In plan view, bump BMP12 overlaps region 85 (transistor 32 and multiple unit transistors 15a). Here, plan view refers to viewing semiconductor substrate 71 in a direction perpendicular to the main surface of semiconductor substrate 71 (the direction opposite to the Z-axis direction).

[0064] The bump BMP12 corresponds to an example of a "first metal member" in the present disclosure.

[0065] The bump BMP 12 may be made of, for example, copper (Cu), but may also be made of low-resistance metal materials such as aluminum (Al) and gold (Au) other than copper.

[0066] An under-bump metal may be formed between the insulating layer and the bump BMP12.

[0067] The emitters of the unit transistors 15a are electrically connected to a bump BMP12 through vias (described later).

[0068] 3 is a cross-sectional view of the power amplifier circuit according to the first embodiment taken along line AB in FIG.

[0069] FIG. 3 shows cross sections of the transistor 32, the plurality of unit transistors 15a, and the bump BMP12, but the cross sections of the transistor 22, the plurality of unit transistors 12a, and the bump BMP11 are similar, so illustration and description thereof will be omitted.

[0070] A transistor 32 and a plurality of unit transistors 15a are formed on a semiconductor substrate 71. An insulating layer 72 is formed in a layer above the transistor 32 and the plurality of unit transistors 15a (layer in the Z-axis direction). Bumps BMP12 are formed in a layer above the insulating layer 72 (layer in the Z-axis direction). The emitters of the plurality of unit transistors 15a are electrically connected to the bumps BMP12 through a plurality of vias 101a.

[0071] An under-bump metal may be formed between the insulating layer 72 and the bump BMP 12. In that case, the multiple vias 101a are electrically connected to the under-bump metal.

[0072] The emitter of the transistor 32 is electrically connected to the bump BMP21 (see FIG. 2) via the wiring 92 (see FIG. 2), and is not electrically connected to the bump BMP12.

[0073] (effect) The amplifying transistor 15 (multiple unit transistors 15a) generates heat when a bias is applied or when a high-frequency signal is amplified. When the amplifying transistor 15 generates heat, the threshold value of the base-emitter voltage drops, the operating point fluctuates, the quiescent current fluctuates, the gain fluctuates, and the linearity deteriorates.

[0074] Refer to Figure 3. Heat generated from the multiple unit transistors 15a is transferred to transistor 32 via semiconductor substrate 71 and insulating layer 72. In other words, the multiple unit transistors 15a and transistor 32 are thermally coupled. When heat is transferred to transistor 32 and the temperature rises, the threshold base-emitter voltage of transistor 32 drops.

[0075] Referring to FIG. 1, when the threshold of the base-emitter voltage of the transistor 32 drops, the current I25 increases, the current I24 increases, and the current I22 increases. Thus, the current I23 decreases. When the current I23 decreases, the transistor 33 decreases the current I26. That is, the base bias current (current I26) provided to the amplifying transistor 15 decreases. Thus, the fluctuation of the threshold of the base-emitter voltage of the amplifying transistor 15 due to an increase in temperature is compensated for by the decrease in the base bias current (current I26).

[0076] As a result, the power amplifier circuit 1 can suppress deterioration of the output characteristics even if the amplifier transistor 15 generates heat.

[0077] Although the amplifying transistor 15 and the bias circuit 16 have been described above, the amplifying transistor 12 and the bias circuit 13 also operate in the same manner. As a result, the power amplifying circuit 1 can suppress deterioration of the output characteristics even if the amplifying transistor 12 generates heat.

[0078] In the first embodiment, the technology of the present disclosure is applied to both stages of the multi-stage amplifier circuit (the amplifier transistor 12 and the bias circuit 13, and the amplifier transistor 15 and the bias circuit 16), but the present disclosure is not limited to this. The technology of the present disclosure may be applied to at least one stage of the multi-stage amplifier circuit.

[0079] <Second embodiment> (Circuit configuration) FIG. 4 is a diagram illustrating a circuit configuration of a power amplifier circuit according to the second embodiment.

[0080] Compared to the power amplifier circuit 1 (see FIG. 1), the power amplifier circuit 1A includes a bias circuit 13A instead of the bias circuit 13. Moreover, the power amplifier circuit 1A includes a bias circuit 16A instead of the bias circuit 16.

[0081] Compared to the bias circuit 13, the bias circuit 13A further includes a transistor 24.

[0082] The transistor 24 corresponds to an example of a "fourth transistor" of the present disclosure.

[0083] In the embodiment, transistor 24 is a unit transistor, but the present disclosure is not limited thereto. Transistor 24 may be a multi-finger transistor.

[0084] The collector and base of the transistor 24 are electrically connected to a node N12 between the emitter of the transistor 21 and the collector of the transistor 22. In other words, the transistor 24 is diode-connected. The emitter of the transistor 24 is electrically connected to the bump BMP21.

[0085] That is, the transistor 22 and the transistor 24 are connected in parallel.

[0086] The size of transistor 22 and the size of transistor 24 may be different or the same.

[0087] The transistor 21 outputs a current I14 to the node N12. The current I14 is divided into a current I17 and a current I18. That is, I14=I17+I18.

[0088] The current I14 corresponds to an example of the "second current" of the present disclosure.

[0089] The current I17 is input to the collector and base of the transistor 22. The transistor 22 outputs a current I19 from the emitter to the bump BMP21. In other words, I17=I19.

[0090] The current I18 is input to the collector and base of the transistor 24. The transistor 24 outputs a current I20 from the emitter to the bump BMP21. In other words, I18=I20.

[0091] The current I20 corresponds to an example of the "fourth current" of the present disclosure.

[0092] Compared to the bias circuit 16, the bias circuit 16A further includes a transistor 34.

[0093] The transistor 34 corresponds to an example of a "fourth transistor" of the present disclosure.

[0094] In the embodiment, the transistor 34 is a unit transistor, but the present disclosure is not limited thereto. The transistor 34 may be a multi-finger transistor.

[0095] The collector and base of the transistor 34 are electrically connected to a node N22 between the emitter of the transistor 31 and the collector of the transistor 32. In other words, the transistor 34 is diode-connected. The emitter of the transistor 34 is electrically connected to the bump BMP21.

[0096] In other words, the transistor 32 and the transistor 34 are connected in parallel.

[0097] The size of transistor 32 and the size of transistor 34 may be different or the same.

[0098] The transistor 31 outputs a current I24 to the node N22. The current I24 is divided into a current I27 and a current I28. That is, I24=I27+I28.

[0099] The current I24 corresponds to an example of the "second current" of the present disclosure.

[0100] The current I27 is input to the collector and base of the transistor 32. The transistor 32 outputs a current I29 from the emitter to the bump BMP21. In other words, I27=I29.

[0101] The current I28 is input to the collector and base of the transistor 34. The transistor 34 outputs a current I30 from the emitter to the bump BMP21. In other words, I28=I30.

[0102] The current I30 corresponds to an example of the "fourth current" of the present disclosure.

[0103] (Layout) Fig. 5 is a diagram showing a layout of a power amplifier circuit according to the second embodiment. A power amplifier circuit 1A is formed on a semiconductor substrate 71. Fig. 5 is a plan view of the semiconductor substrate 71 as viewed from a direction perpendicular to the main surface.

[0104] In comparison with the power amplifier circuit 1 (see FIG. 2), the power amplifier circuit 1A has a transistor 24 formed in the upper part (the part on the base end side of the Y axis) of the bias circuit region 81. The emitter of the transistor 24 is electrically connected to the bump BMP21 via a wiring 93 formed on the semiconductor substrate 71.

[0105] Further, the transistor 34 is formed in the lower part (the part on the Y-axis direction side) of the bias circuit region 81 in the figure. The emitter of the transistor 34 is electrically connected to the bump BMP21 via a wiring 94 formed on the semiconductor substrate 71.

[0106] In addition, the transistor 24 and the transistor 34 may overlap the bump BMP 21 in a plan view. Here, a plan view refers to viewing the semiconductor substrate 71 in a direction perpendicular to the main surface of the semiconductor substrate 71 (the direction opposite to the Z-axis direction).

[0107] (effect) In the bias circuit 16 of the first embodiment, because the transistor 32 is thermally coupled to the multiple unit transistors 15a, there is a possibility that the bias circuit 16 may be overly sensitive in response to heat generated in the multiple unit transistors 15a. In other words, there is a possibility that the power amplifier circuit 1 may be overly sensitive in response to heat generated in the amplifying transistor 15.

[0108] On the other hand, the bias circuit 16A of the second embodiment includes, in addition to transistor 32 that is thermally coupled to the multiple unit transistors 15a, a transistor 34 that is not thermally coupled to the multiple unit transistors 15a. Transistors 32 and 34 are connected in parallel. Because transistor 34 is not subjected to heat generated by the multiple unit transistors 15a, the emitter current of transistor 34 (current I30) is not affected by the heat generated by the multiple unit transistors 15a. Therefore, fluctuations in the base bias current (current I26) of the amplifying transistor 15 are suppressed compared to the first embodiment.

[0109] This allows the bias circuit 16A to suppress the response to heat generated in the amplifying transistor 15 from becoming too sensitive. That is, the power amplifying circuit 1A can suppress the response to heat generated in the amplifying transistor 15 from becoming too sensitive.

[0110] Furthermore, if the transistors 24 and 34 overlap the bump BMP21 in a plan view, stress is also applied to the transistors 24 and 34, the effect of the stress on the amplifying transistor 15 is reduced, and deterioration of the output characteristics can be suppressed.

[0111] The bias circuit 16A can adjust the response to heat generated by the amplifying transistor 15 by adjusting the size of the transistor 32 and the size of the transistor 34. In the present disclosure, the sizes of the transistor 32 and the transistor 34 refer to the emitter areas.

[0112] Although the bias circuit 16A has been described above, the bias circuit 13A operates in the same manner. This makes it possible for the power amplifier circuit 1A to suppress over-responsiveness to heat generated in the amplifier transistor 12.

[0113] The bias circuit 13A can adjust the response to heat generated by the amplifying transistor 12 by adjusting the size of the transistor 22 and the size of the transistor 24. In the present disclosure, the sizes of the transistor 22 and the transistor 24 refer to the emitter areas.

[0114] In the second embodiment, the technology of the present disclosure is applied to both stages of the multistage amplifier circuit (the amplifier transistor 12 and the bias circuit 13, and the amplifier transistor 15 and the bias circuit 16), but the present disclosure is not limited to this. The technology of the present disclosure may be applied to at least one stage of the multistage amplifier circuit.

[0115] <Third embodiment> (Circuit configuration) FIG. 6 is a diagram illustrating a circuit configuration of a power amplifier circuit according to the third embodiment.

[0116] The power amplifier circuit 1B further includes an amplifier transistor 18 and a bias circuit 19, in comparison with the power amplifier circuit 1 (see FIG. 1).

[0117] In the embodiment, the amplifier transistor 18 is a multi-finger transistor, but the present disclosure is not limited to this. The amplifier transistor 18 may be a unit transistor.

[0118] The amplifying transistor 15 and the amplifying transistor 18 are connected in parallel. That is, the final stage (power stage) of the power amplifying circuit 1B is composed of the amplifying transistor 15 and the amplifying transistor 18 connected in parallel.

[0119] The bias circuit 19 provides a bias to the amplifying transistor 18. The bias circuit 19 includes transistors 41 to 43.

[0120] In the embodiment, each of the transistors 41 to 43 is a unit transistor, but the present disclosure is not limited to this. Each of the transistors 41 to 43 may be a multi-finger transistor.

[0121] The collector and base of the transistor 41 are electrically connected to the node N31. That is, the transistor 41 is diode-connected. The emitter of the transistor 41 is electrically connected to the collector and base of the transistor 42. That is, the transistor 42 is diode-connected. The emitter of the transistor 42 is electrically connected to the bump BMP21. That is, the emitter of the transistor 42 is electrically connected to the reference potential via the bump BMP21.

[0122] The base of the transistor 43 is electrically connected to the node N31. The collector of the transistor 43 is electrically connected to the power supply potential Vcc5 and receives power. The emitter of the transistor 43 is electrically connected to one end of the resistor 59. That is, the transistor 43 and the resistor 59 are connected in an emitter-follower fashion. The other end of the resistor 59 is electrically connected to the base of the amplifying transistor 18.

[0123] A current I31 is input to node N31 from a current source 52. The current I31 is divided into a current I32 and a current I33. That is, I31=I32+I33.

[0124] A current I32 is input to the collector and base of a transistor 41. The transistor 41 outputs a current I34 from the emitter to the collector and base of the transistor 32. That is, I32=I34. The transistor 42 outputs a current I35 from the emitter to the bump BMP21. That is, I34=I35. The transistors 41 and 42 generate a voltage at a node N31.

[0125] The transistor 43 outputs a current I36 corresponding to the current I33 to the base of the amplifying transistor 18 via the resistor 59. The base of the amplifying transistor 18 is biased by the current I36. That is, the current I36 is the base bias current of the amplifying transistor 18.

[0126] The emitter of the amplifying transistor 18 is electrically connected to a bump BMP13 (described later). The bump BMP13 is electrically connected to a reference potential. That is, the emitter of the amplifying transistor 18 is electrically connected to the reference potential via the bump BMP13. The collector of the amplifying transistor 18 is electrically connected to a power supply potential Vcc6 via a choke coil 60, and power is supplied to the collector.

[0127] A DC blocking capacitor 57 is added between the other end of the interstage matching circuit 14 and the base of the amplifying transistor 15. A DC blocking capacitor 58 is added between the other end of the interstage matching circuit 14 and the base of the amplifying transistor 18.

[0128] The collector of the amplifier transistor 15 is electrically connected to the node N1. The amplifier transistor 15 amplifies the radio frequency signal RF1 input to the base, and outputs the amplified radio frequency signal RF2 from the collector to the node N1.

[0129] The collector of the amplifier transistor 18 is electrically connected to the node N1. The amplifier transistor 18 amplifies the radio frequency signal RF1 input to the base, and outputs the amplified radio frequency signal RF3 from the collector to the node N1.

[0130] The high frequency signals RF2 and RF3 are superimposed at a node N1 to become a high frequency signal RFout.

[0131] One end of the output matching circuit 17 is electrically connected to the node N1. The other end of the output matching circuit 17 outputs a high frequency signal RFout.

[0132] (Layout) Fig. 7 is a diagram showing a layout of a power amplifier circuit according to the third embodiment. A power amplifier circuit 1B is formed on a semiconductor substrate 71. Fig. 7 is a plan view of the semiconductor substrate 71 as viewed in a direction perpendicular to the main surface.

[0133] A region 85 is provided below the bias circuit region 81 and the inter-stage matching circuit region 84 in the figure (on the Y-axis direction). The longitudinal direction of the region 85 is the X-axis direction, and the lateral direction is the Y-axis direction. A transistor 32 and a plurality of unit transistors 15a are formed in the region 85. The plurality of unit transistors 15a constitute the amplifying transistor 15.

[0134] A transistor 32 is formed along the right side of region 85 in the figure (the side on the X-axis direction side). A plurality of unit transistors 15a are formed on the left side of transistor 32 in the figure (the base end side of the X-axis). The longitudinal direction of each of transistor 32 and the plurality of unit transistors 15a is the Y-axis direction, and the lateral direction is the X-axis direction. The transistor 32 and the plurality of unit transistors 15a are arranged in the longitudinal direction of region 85 (the X-axis direction).

[0135] The emitter of the transistor 32 is electrically connected to the bump BMP21 via a wiring 92 formed on the semiconductor substrate 71.

[0136] The wiring 92 corresponds to an example of a "first wiring" in the present disclosure.

[0137] The bases of the plurality of unit transistors 15 a are electrically connected to the inter-stage matching circuit 14 in the inter-stage matching circuit region 84 via wiring 95 formed in a layer different from the wiring 92 of the semiconductor substrate 71 .

[0138] The wiring 95 corresponds to an example of a "second wiring" in the present disclosure.

[0139] The wiring 92 and the wiring 95 cross each other in a region 151. In the region 151, a parasitic capacitance may occur between the wiring 92 and the wiring 95.

[0140] Region 86 is provided to the right of region 85 in the figure (X-axis direction side) and below inter-stage matching circuit region 84 in the figure (Y-axis direction side). The longitudinal direction of region 86 is the X-axis direction, and the lateral direction is the Y-axis direction. A transistor 42 and a plurality of unit transistors 18a are formed in region 86. The plurality of unit transistors 18a constitute the amplifying transistor 18.

[0141] The transistor 42 is formed along the left side of the region 86 in the figure (the side on the base end side along the X-axis). In addition, a plurality of unit transistors 18a are formed on the right side of the transistor 42 in the figure (the side along the X-axis). The longitudinal direction of each of the transistor 42 and the plurality of unit transistors 18a is the Y-axis direction, and the lateral direction is the X-axis direction. The transistor 42 and the plurality of unit transistors 18a are arranged in the longitudinal direction of the region 86 (the X-axis direction).

[0142] The emitter of the transistor 42 is electrically connected to the bump BMP21 via a wiring 92.

[0143] The bases of the plurality of unit transistors 18 a are electrically connected to the inter-stage matching circuit 14 in the inter-stage matching circuit region 84 via wiring 96 formed on the semiconductor substrate 71 .

[0144] A bump BMP13 is formed on an insulating layer in an upper layer (the layer on the front side of the paper) of region 86. In plan view, bump BMP13 overlaps region 86 (transistor 42 and multiple unit transistors 18a). Here, plan view refers to viewing semiconductor substrate 71 in a direction perpendicular to the main surface of semiconductor substrate 71 (the direction opposite to the Z-axis direction).

[0145] The bump BMP 13 may be made of, for example, copper (Cu), but may also be made of low-resistance metal materials such as aluminum (Al) and gold (Au) other than copper.

[0146] An under-bump metal may be formed between the insulating layer and the bump BMP13.

[0147] (effect) There may be cases where the wiring 92 electrically connecting the transistor 32 and the bump BMP21 needs to intersect with other wiring. Even in such cases, the wiring 92 intersects with a wiring 95 electrically connected to the bases of the unit transistors 15a, thereby realizing an intersection with a smaller parasitic capacitance.

[0148] This allows the power amplifier circuit 1B to suppress deterioration of the output characteristics.

[0149] The third embodiment and the second embodiment may be combined. That is, the bias circuit 13 may further include a transistor 24 connected in parallel to the transistor 22. The bias circuit 16 may further include a transistor 34 connected in parallel to the transistor 32. Similarly, the bias circuit 19 may further include a transistor connected in parallel to the transistor 42.

[0150] In the third embodiment, the technology of the present disclosure is applied to both stages of the multistage amplifier circuit (the amplifier transistor 12 and the bias circuit 13, and the amplifier transistors 15 and 18 and the bias circuits 16 and 19), but the present disclosure is not limited to this. The technology of the present disclosure may be applied to at least one stage of the multistage amplifier circuit.

[0151] <Fourth embodiment> (Circuit configuration) FIG. 8 is a diagram illustrating a circuit configuration of a power amplifier circuit according to the fourth embodiment.

[0152] Compared to the power amplifier circuit 1A (see FIG. 4), the power amplifier circuit 1C includes a bias circuit 13C instead of the bias circuit 13A, and also includes a bias circuit 16C instead of the bias circuit 16A.

[0153] In the bias circuit 13C, the emitter of the transistor 22 is electrically connected to the bump BMP11.

[0154] In bias circuit 16C, the emitter of transistor 32 is electrically connected to bump BMP12.

[0155] (Layout) Fig. 9 is a diagram showing a layout of a power amplifier circuit according to the fourth embodiment. A power amplifier circuit 1C is formed on a semiconductor substrate 71. Fig. 9 is a plan view of the semiconductor substrate 71 as viewed from a direction perpendicular to the main surface.

[0156] Compared to the power amplifier circuit 1A (see FIG. 5), the power amplifier circuit 1C does not include the wiring 91 and the wiring 92. The emitter of the transistor 22 is electrically connected to the bump BMP11. The emitter of the transistor 32 is electrically connected to the bump BMP12.

[0157] 10 is a cross-sectional view of the power amplifier circuit according to the fourth embodiment, taken along line CD in FIG.

[0158] FIG. 10 shows cross sections of the transistor 32, the plurality of unit transistors 15a, and the bump BMP12, but the cross sections of the transistor 22, the plurality of unit transistors 12a, and the bump BMP11 are similar, so they will not be shown or described.

[0159] The emitter of transistor 32 is electrically connected to bump BMP12 through via 102.

[0160] (effect) See Figure 10. Heat generated from the multiple unit transistors 15a is transferred to transistor 32 via semiconductor substrate 71, insulating layer 72, bump BMP12, and via 102. In other words, the multiple unit transistors 15a and transistor 32 are thermally coupled. When heat is transferred to transistor 32 and the temperature rises, the threshold base-emitter voltage of transistor 32 rises. Therefore, the fluctuation in the threshold base-emitter voltage of amplifying transistor 15 due to the rise in temperature is compensated for by an increase in base bias current (current I26).

[0161] As a result, the power amplifier circuit 1 can suppress deterioration of the output characteristics even if the amplifier transistor 15 generates heat.

[0162] The bias circuit 16C includes, in addition to transistor 32 that is thermally coupled to the multiple unit transistors 15a, a transistor 34 that is not thermally coupled to the multiple unit transistors 15a. Transistor 32 and transistor 34 are connected in parallel. Because transistor 34 is not subjected to heat generated by the multiple unit transistors 15a, the emitter current (current I30) of transistor 34 is not affected by heat. Therefore, fluctuations in the base bias current (current I26) of the amplifying transistor 15 are suppressed compared to the first embodiment.

[0163] This allows the bias circuit 16C to suppress the response to heat generated in the amplifying transistor 15 from becoming too sensitive. That is, the power amplifying circuit 1C allows the response to heat generated in the amplifying transistor 15 to be suppressed from becoming too sensitive.

[0164] The bias circuit 16C can adjust the response to heat generated by the amplifying transistor 15 by adjusting the size of the transistor 32 and the size of the transistor .

[0165] Although the bias circuit 16C has been described above, the bias circuit 13C operates in the same manner. As a result, the power amplifier circuit 1C can suppress deterioration of the output characteristics even if the amplifier transistor 12 generates heat.

[0166] The bias circuit 13C can adjust the response to heat generated by the amplifying transistor 12 by adjusting the size of the transistor 22 and the size of the transistor 24.

[0167] Furthermore, when the amplifying transistor 15 (multiple unit transistors 15a) receives stress from the bump BMP12 through the via 101a, the threshold of the base-emitter voltage increases, the operating point changes, the quiescent current changes, the gain changes, and the linearity deteriorates.

[0168] 10, the transistor 32 is electrically connected to the bump BMP12 through the via 102. As a result, the transistor 32 receives stress from the bump BMP12 through the via 102 that is equivalent to the stress that the multiple unit transistors 15a receive from the bump BMP12 through the via 101a.

[0169] When the base-emitter threshold voltages of the multiple unit transistors 15a fluctuate due to stress, the base-emitter threshold voltage of transistor 32 also fluctuates due to stress. As a result, the stress-induced fluctuation in the threshold base-emitter voltage of the amplifying transistor 15 is compensated for by an increase in the base bias current (current I26). This suppresses fluctuations in the quiescent current of the amplifying transistor 15, suppresses fluctuations in gain, and suppresses degradation of linearity.

[0170] As a result, the power amplifier circuit 1C can suppress deterioration of the output characteristics even if the amplifier transistor 15 is subjected to stress.

[0171] The bias circuit 16C can adjust the response of the amplifying transistor 15 to the stress it receives by adjusting the size of the transistor 32 and the size of the transistor .

[0172] Although the transistor 32 and the amplifying transistor 15 have been described above, the transistor 22 and the amplifying transistor 12 also operate in the same manner. As a result, the power amplifying circuit 1C can suppress deterioration of the output characteristics even if the amplifying transistor 12 receives stress from the bump BMP11.

[0173] The bias circuit 13C can adjust the response of the amplifier transistor 12 to the stress it receives by adjusting the size of the transistor 22 and the size of the transistor 24.

[0174] <Fifth embodiment> (Circuit configuration) The circuit configuration of the fifth embodiment is similar to that of the first embodiment (see FIG. 1), and therefore illustration and description thereof will be omitted.

[0175] (Layout) Fig. 11 is a diagram showing the layout of a power amplifier circuit according to the fifth embodiment. A power amplifier circuit 1D is formed on a semiconductor substrate 71. Fig. 11 is a plan view of the semiconductor substrate 71 as viewed in a direction perpendicular to the main surface.

[0176] In the power amplifier circuit 1D, compared to the power amplifier circuit 1 (see FIG. 2), the transistor 32 and the bump BMP12 do not overlap when viewed from a direction perpendicular to the main surface of the semiconductor substrate 71.

[0177] Moreover, the transistor 31 is formed in the bias circuit region 81. A bump BMP14 is formed on an upper layer (the layer on the front side of the paper) of the transistor 31 via an insulating layer. The bump BMP14 overlaps the transistor 31 when the semiconductor substrate 71 is viewed from a direction perpendicular to the main surface of the semiconductor substrate 71.

[0178] (effect) In the power amplifier circuit 1 of the first embodiment, the transistor 32 overlaps the bump BMP12 when the semiconductor substrate 71 is viewed from a direction perpendicular to the main surface of the semiconductor substrate 71, so that the power amplifier circuit 1 may be overly sensitive in response to heat generated in the unit transistors 15a. In other words, the power amplifier circuit 1 may be overly sensitive in response to heat generated in the amplifying transistor 15.

[0179] On the other hand, in the power amplifier circuit 1D of the fifth embodiment, the transistor 32 does not overlap the bump BMP12 when the semiconductor substrate 71 is viewed from a direction perpendicular to the main surface of the semiconductor substrate 71. Therefore, in the power amplifier circuit 1D, the thermal coupling between the transistor 32 and the amplifying transistor 15 can be weakened compared to the power amplifier circuit 1.

[0180] This makes it possible to prevent the power amplifier circuit 1D from being overly responsive to heat generated in the amplifier transistor 15.

[0181] Moreover, in the power amplifier circuit 1D, when the semiconductor substrate 71 is viewed from a direction perpendicular to the main surface of the semiconductor substrate 71, the transistor 31 overlaps the bump BMP14.

[0182] As a result, in the power amplifier circuit 1D, when stress is applied to the semiconductor substrate 71, the stress is also applied to the transistor 31, the effect of the stress on the amplifier transistor 15 is reduced, and deterioration of the output characteristics can be suppressed.

[0183] Although the final stage (transistor 31 and transistor 32) of the multistage amplifier circuit has been described above, the first stage (transistor 21 and transistor 22) of the multistage amplifier circuit may be configured similarly to the final stage. That is, transistor 22 may not overlap bump BMP11 when viewing semiconductor substrate 71 from a direction perpendicular to the main surface of semiconductor substrate 71. Also, transistor 21 may overlap a bump other than bump BMP11 when viewing semiconductor substrate 71 from a direction perpendicular to the main surface of semiconductor substrate 71. The technology of the present disclosure may be applied to at least one stage of a multistage amplifier circuit.

[0184] <Configuration Example of the Present Disclosure> The present disclosure may also have the following configurations.

[0185] (1) a first transistor formed on a semiconductor substrate; a second transistor formed on the semiconductor substrate, a first current being a part of a control current being supplied to a base thereof, and a bias current based on the first current being supplied to the first transistor; a third transistor formed on the semiconductor substrate, receiving a second current that is a part of the control current at a collector, and outputting a third current based on the second current from an emitter; a first metal member electrically connected to the emitter of the first transistor and provided to overlap a first arrangement region in which the first transistor is arranged in a plan view of the semiconductor substrate; a second metal member electrically connected to the emitter of the third transistor; Equipped with the third transistor is provided so as to overlap the first metal member in the plan view; Power amplifier circuit.

[0186] (2) The power amplifier circuit according to (1), a fourth transistor formed on the semiconductor substrate, the second current being a part of the control current being supplied to a collector, and the fourth transistor being in parallel with the third transistor and outputting a fourth current based on the second current from an emitter; Further comprising: the emitter of the fourth transistor is electrically connected to the second metal member; Power amplifier circuit.

[0187] (3) The power amplifier circuit according to (2) above, the fourth transistor is provided so as to overlap the second metal member in the plan view. Power amplifier circuit.

[0188] (4) A power amplifier circuit according to any one of (1) to (3), a first wiring electrically connecting the emitter of the third transistor and the second metal member intersects with a second wiring electrically connected to the base of the first transistor; Power amplifier circuit.

[0189] (5) The power amplifier circuit according to any one of (2) to (4), the third transistor and the fourth transistor have different sizes; Power amplifier circuit.

[0190] (6) A power amplifier circuit according to any one of (1) to (5), a fifth transistor formed on the semiconductor substrate, the fifth transistor having a collector and a base electrically connected to each other, the fifth current being a part of the control current being supplied to the collector and the base, and the fifth transistor outputting the second current from the emitter; Further comprising: The collector and the base of the third transistor are electrically connected. Power amplifier circuit.

[0191] (7) a first transistor formed on a semiconductor substrate; a second transistor formed on the semiconductor substrate, a first current being a part of a control current being supplied to a base thereof, and a bias current based on the first current being supplied to the first transistor; a third transistor formed on the semiconductor substrate, receiving a second current that is a part of the control current at a collector, and outputting a third current based on the second current from an emitter; a fourth transistor formed on the semiconductor substrate, the second current being supplied to a collector thereof, and the fourth transistor being in parallel with the third transistor and outputting a fourth current based on the second current from an emitter thereof; a first metal member electrically connected to the emitter of the first transistor and provided to overlap a first arrangement region in which the first transistor is arranged in a plan view of the semiconductor substrate; Equipped with the emitter of the third transistor is electrically connected to the first metal member; Power amplifier circuit.

[0192] (8) The power amplifier circuit according to (7), a fifth transistor formed on the semiconductor substrate, the fifth transistor having a collector and a base electrically connected to each other, the fifth current being a part of the control current being supplied to the collector and the base, and the fifth transistor outputting the second current from the emitter; Further comprising: the collector and the base of the third transistor are electrically connected; The collector and the base of the fourth transistor are electrically connected. Power amplifier circuit.

[0193] The above-described embodiment is for the purpose of facilitating understanding of the present invention, and is not intended to limit the present invention. The present invention may be modified or improved without departing from the spirit of the present invention, and equivalents thereof are also included in the present invention. [Explanation of symbols]

[0194] 1, 1A, 1B, 1C, 1D Power amplifier circuit 11 Input matching circuit 12, 15, 18 Amplification transistor 12a, 15a Unit transistor 13, 16, 19 Bias circuit 14 Interstage matching circuit 17 Output matching circuit 21, 22, 23, 24, 31, 32, 33, 34, 41, 42, 43 Transistors 71 Semiconductor Substrate 72 Insulating layer BMP11, BMP12, BMP13, BMP14, BMP21 Bump

Claims

1. a first transistor formed on a semiconductor substrate; a second transistor formed on the semiconductor substrate, a first current being a part of a control current being supplied to a base thereof, and a bias current based on the first current being supplied to the first transistor; a third transistor formed on the semiconductor substrate, receiving a second current that is a part of the control current at a collector, and outputting a third current based on the second current from an emitter; a first metal member electrically connected to the emitter of the first transistor and provided to overlap a first arrangement region in which the first transistor is arranged in a plan view of the semiconductor substrate; a second metal member electrically connected to the emitter of the third transistor; Equipped with the third transistor is provided so as to overlap the first metal member in the plan view; Power amplifier circuit.

2. 2. The power amplifier circuit according to claim 1, a fourth transistor formed on the semiconductor substrate, the second current being a part of the control current being supplied to a collector, and the fourth transistor being in parallel with the third transistor and outputting a fourth current based on the second current from an emitter; Further comprising: the emitter of the fourth transistor is electrically connected to the second metal member; Power amplifier circuit.

3. 3. The power amplifier circuit according to claim 2, the fourth transistor is provided so as to overlap the second metal member in the plan view; Power amplifier circuit.

4. 4. A power amplifier circuit according to claim 1, a first wiring electrically connecting the emitter of the third transistor and the second metal member intersects with a second wiring electrically connected to the base of the first transistor; Power amplifier circuit.

5. 3. The power amplifier circuit according to claim 2, the third transistor and the fourth transistor have different sizes; Power amplifier circuit.

6. 2. The power amplifier circuit according to claim 1, a fifth transistor formed on the semiconductor substrate, the fifth transistor having a collector and a base electrically connected to each other, the fifth current being a part of the control current being supplied to the collector and the base, and the fifth transistor outputting the second current from the emitter; Further comprising: The collector and the base of the third transistor are electrically connected. Power amplifier circuit.

7. a first transistor formed on a semiconductor substrate; a second transistor formed on the semiconductor substrate, a first current being a part of a control current being supplied to a base thereof, and a bias current based on the first current being supplied to the first transistor; a third transistor formed on the semiconductor substrate, receiving a second current that is a part of the control current at a collector, and outputting a third current based on the second current from an emitter; a fourth transistor formed on the semiconductor substrate, the second current being supplied to a collector thereof, and the fourth transistor being in parallel with the third transistor and outputting a fourth current based on the second current from an emitter thereof; a first metal member electrically connected to the emitter of the first transistor and provided to overlap a first arrangement region in which the first transistor is arranged in a plan view of the semiconductor substrate; Equipped with the emitter of the third transistor is electrically connected to the first metal member; Power amplifier circuit.

8. 8. A power amplifier circuit according to claim 7, a fifth transistor formed on the semiconductor substrate, the fifth transistor having a collector and a base electrically connected to each other, the fifth current being a part of the control current being supplied to the collector and the base, and the fifth transistor outputting the second current from the emitter; Further comprising: the collector and the base of the third transistor are electrically connected to each other; The collector and the base of the fourth transistor are electrically connected. Power amplifier circuit.

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